[WIP] Support clock propagation delay annotated to routing resource graph

[tangxifan]

Context & Current Behaviour

VTR has offered the RRGraph Edge attribute to annotate delay to each edge of the routing resource graph.

https://docs.verilogtorouting.org/en/latest/vpr/file_formats/#rr-graph-edge-attribute-override-file-format-txt

However, when there is a custom clock network, for example, the programmable clock network in OpenFPGA, the clock signals are not routed through global routing or the dedicated network.
Therefore, the edge attribute can not capture the clock propagation delay per sink.
However, the clock propagation delay is critical for timing convergence during placement and routing.

Proposed Behaviour

File Format

Another file format should be created to overload the clock propagation delay to each clock sink of programmable blocks in a routing resource graph.
The file format may be as simple as a text file

For example, each node pair represents a clock source and a sink node, and the delay are in the unit of second.
The source node is an alias clk<int>, where the integer starts with 0 and represents the clock index. For instance, clk0, clk1.
The alias is used as the actual clock source node could be either

• a virtual clock source node (created by a dedicated network) or
• an I/O block which is mapped to the clock input. But in the mode of --clock_modeling ideal, the I/O mapping for clock does not impact the actual delay. Even each time the clock is randomly placed, the clock delay is fixed for each pair.

This will not work on --clock_modeling route``

#(node, node) delay [sec.]
(clk0, 64)   5.9e-11 # This is for clock0
(clk0, 54812) 4.2e-11 # This is for clock0
...
(clk1, 54812) 4.2e-11 # This is for clock1

Command-line option

A new command-line option can be added to VPR where user can specify the file path.

vpr --read_rr_graph_clock_delay <file>

Sanity checks will be applied to ensure that all the nodes are valid in the routing resource graph.

Question: How should we consider clock uncertainty?

Timing analysis

VPR's STA engine should accept the clock propagation delay and consider it in the timing analysis.
The clock propagation delay for each sink and the clock skew between each pair of sinks.