diff --git a/doc/src/arch/reference.rst b/doc/src/arch/reference.rst index d7ae7268994..b8fccc6579a 100644 --- a/doc/src/arch/reference.rst +++ b/doc/src/arch/reference.rst @@ -2337,8 +2337,8 @@ The ```` tag and its contents are described below. :req_param y_offset: The y location of the receiving CLB relative to the driving CLB. :req_param z_offset: The z location of the receiving CLB relative to the driving CLB. :opt_param switch_name: [Optional, defaults to delay-less switch if not specified] The name of the ```` from ```` to be used for this direct connection. - :opt_param from_side: The associated from_pin's block size (must be one of ``left``, ``right``, ``top``, ``bottom`` or left unspecified) - :opt_param to_side: The associated to_pin's block size (must be one of ``left``, ``right``, ``top``, ``bottom`` or left unspecified) + :opt_param from_side: The associated from_pin's block side (must be one of ``left``, ``right``, ``top``, ``bottom`` or left unspecified) + :opt_param to_side: The associated to_pin's block side (must be one of ``left``, ``right``, ``top``, ``bottom`` or left unspecified) Describes a dedicated connection between two complex block pins that skips general interconnect. This is useful for describing structures such as carry chains as well as adjacent neighbour connections. diff --git a/libs/libarchfpga/src/arch_check.cpp b/libs/libarchfpga/src/arch_check.cpp index 022e2d57ded..c8fb00299c4 100644 --- a/libs/libarchfpga/src/arch_check.cpp +++ b/libs/libarchfpga/src/arch_check.cpp @@ -101,7 +101,7 @@ void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_sub_ti if (pb_type->num_pins > (sub_tile->num_phy_pins / sub_tile->capacity.total())) { archfpga_throw(__FILE__, __LINE__, "Logical Block (%s) has more pins than the Sub Tile (%s).\n", - logical_block->name, sub_tile->name); + logical_block->name.c_str(), sub_tile->name.c_str()); } auto& pin_direct_maps = physical_tile->tile_block_pin_directs_map.at(logical_block->index); @@ -110,7 +110,7 @@ void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_sub_ti if (pb_type->num_pins != (int)pin_direct_map.size()) { archfpga_throw(__FILE__, __LINE__, "Logical block (%s) and Sub tile (%s) have a different number of ports.\n", - logical_block->name, physical_tile->name); + logical_block->name.c_str(), physical_tile->name.c_str()); } for (auto pin_map : pin_direct_map) { @@ -126,7 +126,7 @@ void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_sub_ti || sub_tile_port->equivalent != block_port->equivalent) { archfpga_throw(__FILE__, __LINE__, "Logical block (%s) and Physical tile (%s) do not have equivalent port specifications. Sub tile port %s, logical block port %s\n", - logical_block->name, sub_tile->name, sub_tile_port->name, block_port->name); + logical_block->name.c_str(), sub_tile->name.c_str(), sub_tile_port->name, block_port->name); } } } diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index e77c70f5ed6..80b21308e9f 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -152,17 +152,11 @@ void free_arch(t_arch* arch) { return; } - delete[] arch->Switches; - arch->Switches = nullptr; - free_arch_models(arch->models); - for (int i = 0; i < arch->num_directs; ++i) { - vtr::free(arch->Directs[i].name); - vtr::free(arch->Directs[i].from_pin); - vtr::free(arch->Directs[i].to_pin); - } - vtr::free(arch->Directs); + vtr::release_memory(arch->switches); + + vtr::release_memory(arch->directs); vtr::free(arch->architecture_id); @@ -235,7 +229,7 @@ t_model* free_arch_model(t_model* model) { return next_model; } -//Frees all the model portss in a linked list +//Frees all the model ports in a linked list void free_arch_model_ports(t_model_ports* model_ports) { t_model_ports* model_port = model_ports; while (model_port) { @@ -256,16 +250,17 @@ t_model_ports* free_arch_model_port(t_model_ports* model_port) { } void free_type_descriptors(std::vector& type_descriptors) { - for (auto& type : type_descriptors) { - vtr::free(type.name); + for (t_physical_tile_type& type : type_descriptors) { + vtr::release_memory(type.name); + if (type.index == EMPTY_TYPE_INDEX) { continue; } - for (auto& sub_tile : type.sub_tiles) { - vtr::free(sub_tile.name); + for (t_sub_tile& sub_tile : type.sub_tiles) { + vtr::release_memory(sub_tile.name); - for (auto port : sub_tile.ports) { + for (t_physical_tile_port& port : sub_tile.ports) { vtr::free(port.name); } } @@ -276,8 +271,8 @@ void free_type_descriptors(std::vector& type_descriptors) void free_type_descriptors(std::vector& type_descriptors) { free_all_pb_graph_nodes(type_descriptors); - for (auto& type : type_descriptors) { - vtr::free(type.name); + for (t_logical_block_type& type : type_descriptors) { + vtr::release_memory(type.name); if (type.index == EMPTY_TYPE_INDEX) { continue; } @@ -522,7 +517,7 @@ t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, in t_physical_tile_type get_empty_physical_type(const char* name /*= EMPTY_BLOCK_NAME*/) { t_physical_tile_type type; - type.name = vtr::strdup(name); + type.name = name; type.num_pins = 0; type.width = 1; type.height = 1; @@ -540,7 +535,7 @@ t_physical_tile_type get_empty_physical_type(const char* name /*= EMPTY_BLOCK_NA t_logical_block_type get_empty_logical_type(const char* name /*=EMPTY_BLOCK_NAME*/) { t_logical_block_type type; - type.name = vtr::strdup(name); + type.name = name; type.pb_type = nullptr; return type; @@ -1104,7 +1099,6 @@ void SyncModelsPbTypes(t_arch* arch, void SyncModelsPbTypes_rec(t_arch* arch, t_pb_type* pb_type) { - int i, j, p; t_model *model_match_prim, *cur_model; t_model_ports* model_port; vtr::t_linked_vptr* old; @@ -1143,7 +1137,7 @@ void SyncModelsPbTypes_rec(t_arch* arch, } cur_model = cur_model->next; } - if (found != true) { + if (!found) { archfpga_throw(get_arch_file_name(), 0, "No matching model for pb_type %s\n", pb_type->blif_model); } @@ -1154,7 +1148,7 @@ void SyncModelsPbTypes_rec(t_arch* arch, model_match_prim->pb_types->next = old; model_match_prim->pb_types->data_vptr = pb_type; - for (p = 0; p < pb_type->num_ports; p++) { + for (int p = 0; p < pb_type->num_ports; p++) { found = false; /* TODO: Parse error checking - check if INPUT matches INPUT and OUTPUT matches OUTPUT (not yet done) */ model_port = model_match_prim->inputs; @@ -1203,17 +1197,16 @@ void SyncModelsPbTypes_rec(t_arch* arch, } model_port = model_port->next; } - if (found != true) { + if (!found) { archfpga_throw(get_arch_file_name(), 0, "No matching model port for port %s in pb_type %s\n", pb_type->ports[p].name, pb_type->name); } } } else { - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - SyncModelsPbTypes_rec(arch, - &(pb_type->modes[i].pb_type_children[j])); + for (int i = 0; i < pb_type->num_modes; i++) { + for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + SyncModelsPbTypes_rec(arch, &(pb_type->modes[i].pb_type_children[j])); } } } @@ -1229,11 +1222,11 @@ void SyncModelsPbTypes_rec(t_arch* arch, void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation, t_pb_type* parent_pb_type) { int i_port; - bool clock_valid = false; //Determine if annotation's clock is same as primtive's clock + bool clock_valid = false; //Determine if annotation's clock is same as primitive's clock if (!parent_pb_type || !annotation) { archfpga_throw(__FILE__, __LINE__, - "Annotation_clock check encouters invalid annotation or primitive.\n"); + "Annotation_clock check encounters invalid annotation or primitive.\n"); } for (i_port = 0; i_port < parent_pb_type->num_ports; i_port++) { @@ -1253,18 +1246,17 @@ void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation, } } -const t_segment_inf* find_segment(const t_arch* arch, std::string name) { - for (size_t i = 0; i < (arch->Segments).size(); ++i) { - const t_segment_inf* seg = &arch->Segments[i]; - if (seg->name == name) { - return seg; +const t_segment_inf* find_segment(const t_arch* arch, std::string_view name) { + for (const auto& segment : arch->Segments) { + if (segment.name == name) { + return &segment; } } return nullptr; } -bool segment_exists(const t_arch* arch, std::string name) { +bool segment_exists(const t_arch* arch, std::string_view name) { return find_segment(arch, name) != nullptr; } @@ -1342,7 +1334,7 @@ const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_ty return nullptr; } -const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb_type, std::string in_port, std::string out_port) { +const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb_type, std::string_view in_port, std::string_view out_port) { for (int iannot = 0; iannot < pb_type->num_annotations; ++iannot) { const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot]; for (const auto& annot_in_str : vtr::split(annot->input_pins)) { @@ -1386,9 +1378,9 @@ void link_physical_logical_types(std::vector& PhysicalTile std::sort(equivalent_sites.begin(), equivalent_sites.end(), criteria); - for (auto& logical_block : LogicalBlockTypes) { + for (t_logical_block_type& logical_block : LogicalBlockTypes) { for (auto site : equivalent_sites) { - if (0 == strcmp(logical_block.name, site->pb_type->name)) { + if (logical_block.name == site->pb_type->name) { logical_block.equivalent_tiles.push_back(&physical_tile); break; } @@ -1396,14 +1388,14 @@ void link_physical_logical_types(std::vector& PhysicalTile } } - for (auto& logical_block : LogicalBlockTypes) { + for (t_logical_block_type& logical_block : LogicalBlockTypes) { if (logical_block.index == EMPTY_TYPE_INDEX) continue; auto& equivalent_tiles = logical_block.equivalent_tiles; if ((int)equivalent_tiles.size() <= 0) { archfpga_throw(__FILE__, __LINE__, - "Logical Block %s does not have any equivalent tiles.\n", logical_block.name); + "Logical Block %s does not have any equivalent tiles.\n", logical_block.name.c_str()); } std::unordered_map ignored_pins_check_map; @@ -1439,7 +1431,7 @@ void link_physical_logical_types(std::vector& PhysicalTile if (result == direct_map.end()) { archfpga_throw(__FILE__, __LINE__, "Logical pin %d not present in pin mapping between Tile %s and Block %s.\n", - pin, tile->name, logical_block.name); + pin, tile->name.c_str(), logical_block.name.c_str()); } int sub_tile_pin_index = result->second.pin; @@ -1453,7 +1445,7 @@ void link_physical_logical_types(std::vector& PhysicalTile archfpga_throw(__FILE__, __LINE__, "Physical Tile %s has a different value for the ignored pin (physical pin: %d, logical pin: %d) " "different from the corresponding pins of the other equivalent site %s\n.", - tile->name, phy_index, pin, logical_block.name); + tile->name.c_str(), phy_index, pin, logical_block.name.c_str()); } auto global_result = global_pins_check_map.insert(std::pair(pin, is_global)); @@ -1461,7 +1453,7 @@ void link_physical_logical_types(std::vector& PhysicalTile archfpga_throw(__FILE__, __LINE__, "Physical Tile %s has a different value for the global pin (physical pin: %d, logical pin: %d) " "different from the corresponding pins of the other equivalent sites\n.", - tile->name, phy_index, pin); + tile->name.c_str(), phy_index, pin); } } } @@ -1471,27 +1463,25 @@ void link_physical_logical_types(std::vector& PhysicalTile /* Sets up the pin classes for the type. */ void setup_pin_classes(t_physical_tile_type* type) { - int i, k; - int pin_count; int num_class; - for (i = 0; i < type->num_pins; i++) { + for (int i = 0; i < type->num_pins; i++) { type->pin_class.push_back(OPEN); type->is_ignored_pin.push_back(true); type->is_pin_global.push_back(true); } - pin_count = 0; + int pin_count = 0; t_class_range class_range; /* Equivalent pins share the same class, non-equivalent pins belong to different pin classes */ - for (auto& sub_tile : type->sub_tiles) { + for (const t_sub_tile& sub_tile : type->sub_tiles) { int capacity = sub_tile.capacity.total(); class_range.low = type->class_inf.size(); class_range.high = class_range.low - 1; - for (i = 0; i < capacity; ++i) { - for (const auto& port : sub_tile.ports) { + for (int i = 0; i < capacity; ++i) { + for (const t_physical_tile_port& port : sub_tile.ports) { if (port.equivalent != PortEquivalence::NONE) { t_class class_inf; num_class = (int)type->class_inf.size(); @@ -1505,7 +1495,7 @@ void setup_pin_classes(t_physical_tile_type* type) { class_inf.type = DRIVER; } - for (k = 0; k < port.num_pins; ++k) { + for (int k = 0; k < port.num_pins; ++k) { class_inf.pinlist.push_back(pin_count); type->pin_class[pin_count] = num_class; // clock pins and other specified global ports are initially specified @@ -1525,7 +1515,7 @@ void setup_pin_classes(t_physical_tile_type* type) { type->class_inf.push_back(class_inf); class_range.high++; } else if (port.equivalent == PortEquivalence::NONE) { - for (k = 0; k < port.num_pins; ++k) { + for (int k = 0; k < port.num_pins; ++k) { t_class class_inf; num_class = (int)type->class_inf.size(); class_inf.num_pins = 1; @@ -1544,7 +1534,7 @@ void setup_pin_classes(t_physical_tile_type* type) { // as ignored pins (i.e. connections are not created in the rr_graph and // nets connected to the port are ignored as well). type->is_ignored_pin[pin_count] = port.is_clock || port.is_non_clock_global; - // clock pins and other specified global ports are flaged as global + // clock pins and other specified global ports are flagged as global type->is_pin_global[pin_count] = port.is_clock || port.is_non_clock_global; if (port.is_clock) { diff --git a/libs/libarchfpga/src/arch_util.h b/libs/libarchfpga/src/arch_util.h index f502d6c783a..c39cf77b94f 100644 --- a/libs/libarchfpga/src/arch_util.h +++ b/libs/libarchfpga/src/arch_util.h @@ -95,8 +95,8 @@ void SyncModelsPbTypes_rec(t_arch* arch, void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation, t_pb_type* parent_pb_type); -bool segment_exists(const t_arch* arch, std::string name); -const t_segment_inf* find_segment(const t_arch* arch, std::string name); +bool segment_exists(const t_arch* arch, std::string_view name); +const t_segment_inf* find_segment(const t_arch* arch, std::string_view name); bool is_library_model(const char* model_name); bool is_library_model(const t_model* model); @@ -107,7 +107,7 @@ bool block_type_contains_blif_model(t_logical_block_type_ptr type, const std::st bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::string& blif_model_name); const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* port, enum e_pin_to_pin_delay_annotations annot_type); -const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb_type, std::string in_port, std::string out_port); +const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb_type, std::string_view in_port, std::string_view out_port); /** * @brief Updates the physical and logical types based on the equivalence between one and the other. diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp index 777d655c3e6..4fb52c415f2 100644 --- a/libs/libarchfpga/src/echo_arch.cpp +++ b/libs/libarchfpga/src/echo_arch.cpp @@ -81,8 +81,8 @@ void EchoArch(const char* EchoFile, } fprintf(Echo, "*************************************************\n\n"); fprintf(Echo, "*************************************************\n"); - for (auto& Type : PhysicalTileTypes) { - fprintf(Echo, "Type: \"%s\"\n", Type.name); + for (const t_physical_tile_type& Type : PhysicalTileTypes) { + fprintf(Echo, "Type: \"%s\"\n", Type.name.c_str()); fprintf(Echo, "\tcapacity: %d\n", Type.capacity); fprintf(Echo, "\twidth: %d\n", Type.width); fprintf(Echo, "\theight: %d\n", Type.height); @@ -112,7 +112,7 @@ void EchoArch(const char* EchoFile, auto equivalent_sites = get_equivalent_sites_set(&Type); for (auto LogicalBlock : equivalent_sites) { - fprintf(Echo, "\nEquivalent Site: %s\n", LogicalBlock->name); + fprintf(Echo, "\nEquivalent Site: %s\n", LogicalBlock->name.c_str()); } fprintf(Echo, "\n"); } @@ -132,8 +132,6 @@ void EchoArch(const char* EchoFile, //Added May 2013 Daniel Chen, help dump arch info after loading from XML void PrintArchInfo(FILE* Echo, const t_arch* arch) { - int i, j; - fprintf(Echo, "Printing architecture... \n\n"); //Layout fprintf(Echo, "*************************************************\n"); @@ -253,29 +251,29 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { //13 is hard coded because format of %e is always 1.123456e+12 //It always consists of 10 alphanumeric digits, a decimal //and a sign - for (i = 0; i < arch->num_switches; i++) { - if (arch->Switches[i].type() == SwitchType::MUX) { - fprintf(Echo, "\tSwitch[%d]: name %s type mux\n", i + 1, arch->Switches[i].name.c_str()); - } else if (arch->Switches[i].type() == SwitchType::TRISTATE) { - fprintf(Echo, "\tSwitch[%d]: name %s type tristate\n", i + 1, arch->Switches[i].name.c_str()); - } else if (arch->Switches[i].type() == SwitchType::SHORT) { - fprintf(Echo, "\tSwitch[%d]: name %s type short\n", i + 1, arch->Switches[i].name.c_str()); - } else if (arch->Switches[i].type() == SwitchType::BUFFER) { - fprintf(Echo, "\tSwitch[%d]: name %s type buffer\n", i + 1, arch->Switches[i].name.c_str()); + for (int i = 0; i < (int)arch->switches.size(); i++) { + if (arch->switches[i].type() == SwitchType::MUX) { + fprintf(Echo, "\tSwitch[%d]: name %s type mux\n", i + 1, arch->switches[i].name.c_str()); + } else if (arch->switches[i].type() == SwitchType::TRISTATE) { + fprintf(Echo, "\tSwitch[%d]: name %s type tristate\n", i + 1, arch->switches[i].name.c_str()); + } else if (arch->switches[i].type() == SwitchType::SHORT) { + fprintf(Echo, "\tSwitch[%d]: name %s type short\n", i + 1, arch->switches[i].name.c_str()); + } else if (arch->switches[i].type() == SwitchType::BUFFER) { + fprintf(Echo, "\tSwitch[%d]: name %s type buffer\n", i + 1, arch->switches[i].name.c_str()); } else { - VTR_ASSERT(arch->Switches[i].type() == SwitchType::PASS_GATE); - fprintf(Echo, "\tSwitch[%d]: name %s type pass_gate\n", i + 1, arch->Switches[i].name.c_str()); + VTR_ASSERT(arch->switches[i].type() == SwitchType::PASS_GATE); + fprintf(Echo, "\tSwitch[%d]: name %s type pass_gate\n", i + 1, arch->switches[i].name.c_str()); } - fprintf(Echo, "\t\t\t\tR %e Cin %e Cout %e\n", arch->Switches[i].R, - arch->Switches[i].Cin, arch->Switches[i].Cout); + fprintf(Echo, "\t\t\t\tR %e Cin %e Cout %e\n", arch->switches[i].R, + arch->switches[i].Cin, arch->switches[i].Cout); fprintf(Echo, "\t\t\t\t#Tdel values %d buf_size %e mux_trans_size %e\n", - (int)arch->Switches[i].Tdel_map_.size(), arch->Switches[i].buf_size, - arch->Switches[i].mux_trans_size); - if (arch->Switches[i].power_buffer_type == POWER_BUFFER_TYPE_AUTO) { + (int)arch->switches[i].Tdel_map_.size(), arch->switches[i].buf_size, + arch->switches[i].mux_trans_size); + if (arch->switches[i].power_buffer_type == POWER_BUFFER_TYPE_AUTO) { fprintf(Echo, "\t\t\t\tpower_buffer_size auto\n"); } else { fprintf(Echo, "\t\t\t\tpower_buffer_size %e\n", - arch->Switches[i].power_buffer_size); + arch->switches[i].power_buffer_size); } } @@ -283,7 +281,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { //Segment List fprintf(Echo, "*************************************************\n"); fprintf(Echo, "Segment List:\n"); - for (i = 0; i < (int)(arch->Segments).size(); i++) { + for (int i = 0; i < (int)(arch->Segments).size(); i++) { const struct t_segment_inf& seg = arch->Segments[i]; fprintf(Echo, "\tSegment[%d]: frequency %d length %d R_metal %e C_metal %e\n", @@ -293,23 +291,23 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { if (seg.directionality == UNI_DIRECTIONAL) { //wire_switch == arch_opin_switch fprintf(Echo, "\t\t\t\ttype unidir mux_name for within die connections: %s\n", - arch->Switches[seg.arch_wire_switch].name.c_str()); + arch->switches[seg.arch_wire_switch].name.c_str()); //if there is more than one layer available, print the segment switch name that is used for connection between two dice for (const auto& layout : arch->grid_layouts) { int num_layers = (int)layout.layers.size(); if (num_layers > 1) { fprintf(Echo, "\t\t\t\ttype unidir mux_name for between two dice connections: %s\n", - arch->Switches[seg.arch_opin_between_dice_switch].name.c_str()); + arch->switches[seg.arch_opin_between_dice_switch].name.c_str()); } } } else { //Should be bidir fprintf(Echo, "\t\t\t\ttype bidir wire_switch %s arch_opin_switch %s\n", - arch->Switches[seg.arch_wire_switch].name.c_str(), - arch->Switches[seg.arch_opin_switch].name.c_str()); + arch->switches[seg.arch_wire_switch].name.c_str(), + arch->switches[seg.arch_opin_switch].name.c_str()); } fprintf(Echo, "\t\t\t\tcb "); - for (j = 0; j < (int)seg.cb.size(); j++) { + for (int j = 0; j < (int)seg.cb.size(); j++) { if (seg.cb[j]) { fprintf(Echo, "1 "); } else { @@ -319,7 +317,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { fprintf(Echo, "\n"); fprintf(Echo, "\t\t\t\tsb "); - for (j = 0; j < (int)seg.sb.size(); j++) { + for (int j = 0; j < (int)seg.sb.size(); j++) { if (seg.sb[j]) { fprintf(Echo, "1 "); } else { @@ -332,13 +330,13 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { //Direct List fprintf(Echo, "*************************************************\n"); fprintf(Echo, "Direct List:\n"); - for (i = 0; i < arch->num_directs; i++) { + for (int i = 0; i < (int)arch->directs.size(); i++) { fprintf(Echo, "\tDirect[%d]: name %s from_pin %s to_pin %s\n", i + 1, - arch->Directs[i].name, arch->Directs[i].from_pin, - arch->Directs[i].to_pin); + arch->directs[i].name.c_str(), arch->directs[i].from_pin.c_str(), + arch->directs[i].to_pin.c_str()); fprintf(Echo, "\t\t\t\t x_offset %d y_offset %d z_offset %d\n", - arch->Directs[i].x_offset, arch->Directs[i].y_offset, - arch->Directs[i].sub_tile_offset); + arch->directs[i].x_offset, arch->directs[i].y_offset, + arch->directs[i].sub_tile_offset); } fprintf(Echo, "*************************************************\n\n"); @@ -347,7 +345,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { fprintf(Echo, "*************************************************\n"); fprintf(Echo, "NoC Router Connection List:\n"); - for (auto noc_router : arch->noc->router_list) { + for (const auto& noc_router : arch->noc->router_list) { fprintf(Echo, "NoC router %d is connected to:\t", noc_router.id); for (auto noc_conn_id : noc_router.connection_list) { fprintf(Echo, "%d\t", noc_conn_id); @@ -373,7 +371,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { fprintf(Echo, "*************************************************\n"); fprintf(Echo, "Clock:\n"); if (arch->clocks) { - for (i = 0; i < arch->clocks->num_global_clocks; i++) { + for (int i = 0; i < arch->clocks->num_global_clocks; i++) { if (arch->clocks->clock_inf[i].autosize_buffer) { fprintf(Echo, "\tClock[%d]: buffer_size auto C_wire %e", i + 1, arch->clocks->clock_inf->C_wire); @@ -393,11 +391,10 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) { } static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level) { - int i, j, k; char* tabs; tabs = (char*)vtr::malloc((level + 1) * sizeof(char)); - for (i = 0; i < level; i++) { + for (int i = 0; i < level; i++) { tabs[i] = '\t'; } tabs[level] = '\0'; @@ -407,25 +404,25 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level) { fprintf(Echo, "%s\tclass_type: %d\n", tabs, pb_type->class_type); fprintf(Echo, "%s\tnum_modes: %d\n", tabs, pb_type->num_modes); fprintf(Echo, "%s\tnum_ports: %d\n", tabs, pb_type->num_ports); - for (i = 0; i < pb_type->num_ports; i++) { + for (int i = 0; i < pb_type->num_ports; i++) { fprintf(Echo, "%s\tport %s type %d num_pins %d\n", tabs, pb_type->ports[i].name, pb_type->ports[i].type, pb_type->ports[i].num_pins); } if (pb_type->num_modes > 0) { /*one or more modes*/ - for (i = 0; i < pb_type->num_modes; i++) { + for (int i = 0; i < pb_type->num_modes; i++) { fprintf(Echo, "%s\tmode %s:\n", tabs, pb_type->modes[i].name); - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { PrintPb_types_rec(Echo, &pb_type->modes[i].pb_type_children[j], level + 2); } - for (j = 0; j < pb_type->modes[i].num_interconnect; j++) { + for (int j = 0; j < pb_type->modes[i].num_interconnect; j++) { fprintf(Echo, "%s\t\tinterconnect %d %s %s\n", tabs, pb_type->modes[i].interconnect[j].type, pb_type->modes[i].interconnect[j].input_string, pb_type->modes[i].interconnect[j].output_string); - for (k = 0; + for (int k = 0; k < pb_type->modes[i].interconnect[j].num_annotations; k++) { fprintf(Echo, "%s\t\t\tannotation %s %s %d: %s\n", tabs, @@ -453,7 +450,7 @@ static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level) { if (strcmp(pb_type->model->name, MODEL_NAMES) && strcmp(pb_type->model->name, MODEL_INPUT) && strcmp(pb_type->model->name, MODEL_OUTPUT)) { - for (k = 0; k < pb_type->num_annotations; k++) { + for (int k = 0; k < pb_type->num_annotations; k++) { fprintf(Echo, "%s\t\t\tannotation %s %s %s %d: %s\n", tabs, pb_type->annotations[k].clock, pb_type->annotations[k].input_pins, diff --git a/libs/libarchfpga/src/parse_switchblocks.cpp b/libs/libarchfpga/src/parse_switchblocks.cpp index c0b55bcb7fd..1e8908713bf 100644 --- a/libs/libarchfpga/src/parse_switchblocks.cpp +++ b/libs/libarchfpga/src/parse_switchblocks.cpp @@ -41,16 +41,16 @@ using vtr::t_formula_data; /*---- Functions for Parsing Switchblocks from Architecture ----*/ //Load an XML wireconn specification into a t_wireconn_inf -t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const t_arch_switch_inf* switches, int num_switches); +static t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const std::vector& switches); //Process the desired order of a wireconn static void parse_switchpoint_order(const char* order, SwitchPointOrder& switchpoint_order); //Process a wireconn defined in the inline style (using attributes) -void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches); +static void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector& switches); //Process a wireconn defined in the multinode style (more advanced specification) -void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches); +static void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector& switches); //Process a or sub-node of a multinode wireconn t_wire_switchpoints parse_wireconn_from_to_node(pugi::xml_node node, const pugiutil::loc_data& loc_data); @@ -69,7 +69,7 @@ static void parse_num_conns(std::string num_conns, t_wireconn_inf& wireconn); static void set_switch_func_type(SB_Side_Connection& conn, const char* func_type); /* parse switch_override in wireconn */ -static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const t_arch_switch_inf* switches, int num_switches); +static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const std::vector& switches); /* checks for correctness of a unidir switchblock. */ static void check_unidir_switchblock(const t_switchblock_inf* sb); @@ -85,7 +85,7 @@ static void check_wireconn(const t_arch* arch, const t_wireconn_inf& wireconn); /*---- Functions for Parsing Switchblocks from Architecture ----*/ /* Reads-in the wire connections specified for the switchblock in the xml arch file */ -void read_sb_wireconns(const t_arch_switch_inf* switches, int num_switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data) { +void read_sb_wireconns(const std::vector& switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data) { /* Make sure that Node is a switchblock */ check_node(Node, "switchblock", loc_data); @@ -100,31 +100,29 @@ void read_sb_wireconns(const t_arch_switch_inf* switches, int num_switches, pugi SubElem = get_first_child(Node, "wireconn", loc_data); } for (int i = 0; i < num_wireconns; i++) { - t_wireconn_inf wc = parse_wireconn(SubElem, loc_data, switches, num_switches); // need to pass in switch info for switch override + t_wireconn_inf wc = parse_wireconn(SubElem, loc_data, switches); // need to pass in switch info for switch override sb->wireconns.push_back(wc); SubElem = SubElem.next_sibling(SubElem.name()); } - - return; } -t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const t_arch_switch_inf* switches, int num_switches) { +static t_wireconn_inf parse_wireconn(pugi::xml_node node, const pugiutil::loc_data& loc_data, const std::vector& switches) { t_wireconn_inf wc; size_t num_children = count_children(node, "from", loc_data, ReqOpt::OPTIONAL); num_children += count_children(node, "to", loc_data, ReqOpt::OPTIONAL); if (num_children == 0) { - parse_wireconn_inline(node, loc_data, wc, switches, num_switches); + parse_wireconn_inline(node, loc_data, wc, switches); } else { VTR_ASSERT(num_children > 0); - parse_wireconn_multinode(node, loc_data, wc, switches, num_switches); + parse_wireconn_multinode(node, loc_data, wc, switches); } return wc; } -void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches) { +static void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector& switches) { //Parse an inline wireconn definition, using attributes expect_only_attributes(node, {"num_conns", "from_type", "to_type", "from_switchpoint", "to_switchpoint", "from_order", "to_order", "switch_override"}, loc_data); @@ -156,10 +154,10 @@ void parse_wireconn_inline(pugi::xml_node node, const pugiutil::loc_data& loc_da // parse switch overrides if they exist: char_prop = get_attribute(node, "switch_override", loc_data, ReqOpt::OPTIONAL).value(); - parse_switch_override(char_prop, wc, switches, num_switches); + parse_switch_override(char_prop, wc, switches); } -void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const t_arch_switch_inf* switches, int num_switches) { +void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc_data, t_wireconn_inf& wc, const std::vector& switches) { expect_only_children(node, {"from", "to"}, loc_data); /* get the connection style */ @@ -173,7 +171,7 @@ void parse_wireconn_multinode(pugi::xml_node node, const pugiutil::loc_data& loc parse_switchpoint_order(char_prop, wc.to_switchpoint_order); char_prop = get_attribute(node, "switch_override", loc_data, ReqOpt::OPTIONAL).value(); - parse_switch_override(char_prop, wc, switches, num_switches); + parse_switch_override(char_prop, wc, switches); size_t num_from_children = count_children(node, "from", loc_data); size_t num_to_children = count_children(node, "to", loc_data); @@ -378,11 +376,9 @@ void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiu /* get the next switchblock function */ SubElem = SubElem.next_sibling(SubElem.name()); } - - return; } -static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const t_arch_switch_inf* switches, int num_switches) { +static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const std::vector& switches) { // sentinel value to use default driving switch for the receiving wire type if (switch_override == std::string("")) { wireconn.switch_override_indx = DEFAULT_SWITCH; //Default @@ -390,7 +386,7 @@ static void parse_switch_override(const char* switch_override, t_wireconn_inf& w } // iterate through the valid switch names in the arch looking for the requested switch_override - for (int i = 0; i < num_switches; i++) { + for (int i = 0; i < (int)switches.size(); i++) { if (0 == strcmp(switch_override, switches[i].name.c_str())) { wireconn.switch_override_indx = i; return; diff --git a/libs/libarchfpga/src/parse_switchblocks.h b/libs/libarchfpga/src/parse_switchblocks.h index a7686031818..93777f965b6 100644 --- a/libs/libarchfpga/src/parse_switchblocks.h +++ b/libs/libarchfpga/src/parse_switchblocks.h @@ -11,7 +11,7 @@ void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data); /* Reads-in the wire connections specified for the switchblock in the xml arch file */ -void read_sb_wireconns(const t_arch_switch_inf* switches, int num_switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data); +void read_sb_wireconns(const std::vector& switches, pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data); /* checks for correctness of switch block read-in from the XML architecture file */ void check_switchblock(const t_switchblock_inf* sb, const t_arch* arch); diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index dfa110f393f..3bdabaee2a7 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -7,7 +7,7 @@ static bool switch_type_is_buffered(SwitchType type); static bool switch_type_is_configurable(SwitchType type); -static e_directionality switch_type_directionaity(SwitchType type); +static e_directionality switch_type_directionality(SwitchType type); //Ensure the constant has external linkage to avoid linking errors constexpr int t_arch_switch_inf::UNDEFINED_FANIN; @@ -29,7 +29,7 @@ bool t_arch_switch_inf::configurable() const { } e_directionality t_arch_switch_inf::directionality() const { - return switch_type_directionaity(type()); + return switch_type_directionality(type()); } float t_arch_switch_inf::Tdel(int fanin) const { @@ -76,8 +76,8 @@ void t_rr_switch_inf::set_type(SwitchType type_val) { } static bool switch_type_is_buffered(SwitchType type) { - //Muxes and Tristates isolate thier input and output into - //seperate DC connected sub-circuits + //Muxes and Tristates isolate their input and output into + //separate DC connected sub-circuits return type == SwitchType::MUX || type == SwitchType::TRISTATE || type == SwitchType::BUFFER; @@ -89,7 +89,7 @@ static bool switch_type_is_configurable(SwitchType type) { || type == SwitchType::BUFFER); } -static e_directionality switch_type_directionaity(SwitchType type) { +static e_directionality switch_type_directionality(SwitchType type) { if (type == SwitchType::SHORT || type == SwitchType::PASS_GATE) { //Shorts and pass gates can conduct in either direction @@ -133,7 +133,7 @@ int t_physical_tile_type::get_sub_tile_loc_from_pin(int pin_num) const { } bool t_physical_tile_type::is_empty() const { - return std::string(name) == std::string(EMPTY_BLOCK_NAME); + return name == std::string(EMPTY_BLOCK_NAME); } /* @@ -141,7 +141,7 @@ bool t_physical_tile_type::is_empty() const { */ bool t_logical_block_type::is_empty() const { - return std::string(name) == std::string(EMPTY_BLOCK_NAME); + return name == std::string(EMPTY_BLOCK_NAME); } /** diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 1f2dc44c7c9..4d415697554 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -649,7 +649,7 @@ constexpr int DEFAULT_SWITCH = -2; * */ struct t_physical_tile_type { - char* name = nullptr; + std::string name; int num_pins = 0; int num_inst_pins = 0; int num_input_pins = 0; @@ -772,7 +772,7 @@ struct t_capacity_range { * These two blocks can be identified as equivalent, hence they can belong to the same sub tile. */ struct t_sub_tile { - char* name = nullptr; + std::string name; // Mapping between the subtile's pins and the physical pins corresponding // to the physical tile type. @@ -932,7 +932,7 @@ struct t_physical_tile_port { * A logical block must correspond to at least one physical tile. */ struct t_logical_block_type { - char* name = nullptr; + std::string name; /* Clustering info */ t_pb_type* pb_type = nullptr; @@ -1380,11 +1380,11 @@ class t_pb_graph_pin { float thld = std::numeric_limits::quiet_NaN(); /* For sequential logic elements the hold time */ float tco_min = std::numeric_limits::quiet_NaN(); /* For sequential logic elements the minimum clock to output time */ float tco_max = std::numeric_limits::quiet_NaN(); /* For sequential logic elements the maximum clock to output time */ - t_pb_graph_pin* associated_clock_pin = nullptr; /* For sequentail elements, the associated clock */ + t_pb_graph_pin* associated_clock_pin = nullptr; /* For sequential elements, the associated clock */ /* This member is used when flat-routing and router_opt_choke_points are enabled. * It is used to identify choke points. - * This is only valid for IPINs, and it only contain the pins that are reachable to the pin by a forwarding path. + * This is only valid for IPINs, and it only contains the pins that are reachable to the pin by a forwarding path. * It doesn't take into account feed-back connection. * */ std::unordered_set connected_sinks_ptc; /* ptc numbers of sinks which are directly or indirectly connected to this pin */ @@ -1697,51 +1697,46 @@ enum class BufferSize { ABSOLUTE }; -/* Lists all the important information about a switch type read from the * - * architecture file. * - * [0 .. Arch.num_switch] * - * buffered: Does this switch include a buffer? * - * R: Equivalent resistance of the buffer/switch. * - * Cin: Input capacitance. * - * Cout: Output capacitance. * - * Cinternal: Since multiplexers and tristate buffers are modeled as a * - * parallel stream of pass transistors feeding into a buffer, * - * we would expect an additional "internal capacitance" * - * to arise when the pass transistor is enabled and the signal * - * must propogate to the buffer. See diagram of one stream below: * - * * - * Pass Transistor * - * | * - * ----- * - * ----- Buffer * - * | | |\ * - * ------ -------| \-------- * - * | | | / | * - * ===== ===== |/ ===== * - * ===== ===== ===== * - * | | | * - * Input C Internal C Output C * - * * - * Tdel_map: A map where the key is the number of inputs and the entry * - * is the corresponding delay. If there is only one entry at key * - * UNDEFINED, then delay is a constant (doesn't vary with fan-in). * - * A map saves us the trouble of sorting, and has lower access * - * time for interpolation/extrapolation purposes * - * mux_trans_size: The area of each transistor in the segment's driving mux * - * measured in minimum width transistor units * - * buf_size: The area of the buffer. If set to zero, area should be * - * calculated from R */ +/** + * @struct t_arch_switch_inf + * @brief Lists all the important information about a switch type read from the architecture file. + */ struct t_arch_switch_inf { public: static constexpr int UNDEFINED_FANIN = -1; std::string name; + /// Equivalent resistance of the buffer/switch float R = 0.; + /// Input capacitance float Cin = 0.; + /// Output capacitance float Cout = 0.; + /** + * @brief The internal capacitance. + * @details Since multiplexers and tristate buffers are modeled as a + * parallel stream of pass transistors feeding into a buffer, + * we would expect an additional "internal capacitance + * to arise when the pass transistor is enabled and the signal + * must propagate to the buffer. See diagram of one stream below: + * + * Pass Transistor + * | + * ----- + * ----- Buffer + * | | |\ + * ------ -------| \ ----- + * | | | / | + * ===== ===== |/ ===== + * ===== ===== ===== + * | | | + * Input C Internal C Output C + */ float Cinternal = 0.; + /// The area of each transistor in the segment's driving mux measured in minimum width transistor units float mux_trans_size = 1.; BufferSize buf_size_type = BufferSize::AUTO; + /// The area of the buffer. If set to zero, area should be calculated from R float buf_size = 0.; e_power_buffer_type power_buffer_type = POWER_BUFFER_TYPE_AUTO; float power_buffer_size = 0.; @@ -1774,6 +1769,15 @@ struct t_arch_switch_inf { private: SwitchType type_ = SwitchType::INVALID; + + /** + * @brief Maps the number of inputs to a delay. + * @details A map where the key is the number of inputs and the entry + * is the corresponding delay. If there is only one entry at key + * UNDEFINED, then delay is a constant (doesn't vary with fan-in). + * A map saves us the trouble of sorting, and has lower access + * time for interpolation/extrapolation purposes + */ std::map Tdel_map_; friend void PrintArchInfo(FILE*, const t_arch*); @@ -1823,7 +1827,7 @@ struct t_rr_switch_inf { SwitchType type() const; //Returns true if this switch type isolates its input and output into - //seperate DC-connected subcircuits + //separate DC-connected subcircuits bool buffered() const; //Returns true if this switch type is configurable @@ -1836,31 +1840,30 @@ struct t_rr_switch_inf { SwitchType type_ = SwitchType::INVALID; }; -/* Lists all the important information about a direct chain connection. * - * [0 .. det_routing_arch.num_direct] * - * name: Name of this direct chain connection * - * from_pin: The type of the pin that drives this chain connection * - * In the format of . * - * to_pin: The type of pin that is driven by this chain connection * - * In the format of . * - * x_offset: The x offset from the source to the sink of this connection * - * y_offset: The y offset from the source to the sink of this connection * - * z_offset: The z offset from the source to the sink of this connection * - * switch_type: The index into the switch list for the switch used by this * - * direct * - * line: The line number in the .arch file that specifies this * - * particular placement macro. * +/** + * @struct t_direct_inf + * @brief Lists all the important information about a direct chain connection. */ struct t_direct_inf { - char* name; - char* from_pin; - char* to_pin; + /// Name of this direct chain connection + std::string name; + /// The type of the pin that drives this chain connection in the format of . + std::string from_pin; + /// The type of pin that is driven by this chain connection in the format of . + std::string to_pin; + /// The x offset from the source to the sink of this connection int x_offset; + /// The y offset from the source to the sink of this connection int y_offset; + /// The subtile offset from the source to the sink of this connection int sub_tile_offset; + /// The index into the switch list for the switch used by this direct int switch_type; + /// The associated from_pin’s block side e_side from_side; + /// The associated to_pin’s block side e_side to_side; + /// The line number in the architecture file that specifies this particular placement macro. int line; }; @@ -1894,7 +1897,7 @@ struct t_wireconn_inf { * elements (if 'from' is larger than 'to'), or in some elements of 'to' having * no driving connections (if 'to' is larger than 'from'). * 'to': The number of generated connections is set equal to the size of the 'to' set. - * This ensures that each element of the 'to' set has precisely one incomming connection. + * This ensures that each element of the 'to' set has precisely one incoming connection. * Note: this may result in 'from' elements driving multiple 'to' elements (if 'to' is * larger than 'from'), or some 'from' elements driving to 'to' elements (if 'from' is * larger than 'to') @@ -1948,7 +1951,7 @@ struct t_switchblock_inf { e_directionality directionality; /* the directionality of this switchblock (unidir/bidir) */ int x = -1; /* The exact x-axis location that this SB is used, meaningful when type is set to E_XY_specified */ - int y = -1; /* The exact y-axis location that this SB is used, meanignful when type is set to E_XY_specified */ + int y = -1; /* The exact y-axis location that this SB is used, meaningful when type is set to E_XY_specified */ /* We can also define a region to apply this SB to all locations falls into this region using regular expression in the architecture file*/ t_sb_loc_spec reg_x; @@ -2049,7 +2052,8 @@ struct t_arch { mutable vtr::string_internment strings; std::vector interned_strings; - char* architecture_id; //Secure hash digest of the architecture file to uniquely identify this architecture + /// Secure hash digest of the architecture file to uniquely identify this architecture + char* architecture_id; t_chan_width_dist Chans; enum e_switch_block_type SBType; @@ -2059,10 +2063,12 @@ struct t_arch { int Fs; float grid_logic_tile_area; std::vector Segments; - t_arch_switch_inf* Switches = nullptr; - int num_switches; - t_direct_inf* Directs = nullptr; - int num_directs = 0; + + /// Contains information from all switch types defined in the architecture file. + std::vector switches; + + /// Contains information about all direct chain connections in the architecture + std::vector directs; t_model* models = nullptr; t_model* model_library = nullptr; @@ -2115,7 +2121,7 @@ struct t_arch { t_clock_arch_spec clock_arch; // Clock related data types - // if we have an embedded NoC in the architecture, then we store it here + /// Stores NoC-related architectural information when there is an embedded NoC t_noc_inf* noc = nullptr; }; diff --git a/libs/libarchfpga/src/physical_types_util.cpp b/libs/libarchfpga/src/physical_types_util.cpp index 43a0fbc54da..2256f81d66c 100644 --- a/libs/libarchfpga/src/physical_types_util.cpp +++ b/libs/libarchfpga/src/physical_types_util.cpp @@ -430,7 +430,7 @@ int get_sub_tile_physical_pin(int sub_tile_index, archfpga_throw(__FILE__, __LINE__, "Couldn't find the corresponding physical tile pin of the logical block pin %d." "Physical Tile Type: %s, Logical Block Type: %s.\n", - pin, physical_tile->name, logical_block->name); + pin, physical_tile->name.c_str(), logical_block->name.c_str()); } return result->second.pin; @@ -450,7 +450,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_ if (sub_tile_index == OPEN) { archfpga_throw(__FILE__, __LINE__, "Found no instances of logical block type '%s' within physical tile type '%s'. ", - logical_block->name, physical_tile->name); + logical_block->name.c_str(), physical_tile->name.c_str()); } return sub_tile_index; @@ -488,7 +488,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_ if (sub_tile_index == OPEN) { archfpga_throw(__FILE__, __LINE__, "Found no instances of logical block type '%s' within physical tile type '%s'. ", - logical_block->name, physical_tile->name); + logical_block->name.c_str(), physical_tile->name.c_str()); } return sub_tile_index; @@ -633,7 +633,7 @@ std::pair get_capacity_location_from_physical_pin(t_physical_tile_type archfpga_throw(__FILE__, __LINE__, "Couldn't find sub tile that contains the pin %d in physical tile %s.\n", - pin, physical_tile->name); + pin, physical_tile->name.c_str()); } int get_physical_pin_from_capacity_location(t_physical_tile_type_ptr physical_tile, int relative_pin, int capacity_location) { @@ -652,7 +652,7 @@ int get_physical_pin_from_capacity_location(t_physical_tile_type_ptr physical_ti archfpga_throw(__FILE__, __LINE__, "Couldn't find sub tile that contains the relative pin %d at the capacity location %d in physical tile %s.\n", - relative_pin, capacity_location, physical_tile->name); + relative_pin, capacity_location, physical_tile->name.c_str()); } bool is_opin(int ipin, t_physical_tile_type_ptr type) { /* Returns true if this clb pin is an output, false otherwise. */ @@ -809,14 +809,14 @@ std::vector block_type_class_index_to_pin_names(t_physical_tile_typ if (is_pin_on_tile(type, pin_physical_start)) { VTR_ASSERT(is_pin_on_tile(type, pin_physical_end) == true); port_name = sub_tile.ports[iport].name; - block_name = vtr::string_fmt("%s[%d]", type->name, icapacity); + block_name = vtr::string_fmt("%s[%d]", type->name.c_str(), icapacity); } else { VTR_ASSERT(is_pin_on_tile(type, pin_physical_end) == false); auto pb_pin = get_pb_pin_from_pin_physical_num(type, pin_physical_start); port_name = pb_pin->port->name; auto pb_graph_node = get_pb_graph_node_from_pin_physical_num(type, pin_physical_start); block_name = vtr::string_fmt("%s[%d].%s", - type->name, + type->name.c_str(), icapacity, pb_graph_node->hierarchical_type_name().c_str()); } diff --git a/libs/libarchfpga/src/physical_types_util.h b/libs/libarchfpga/src/physical_types_util.h index 4d9c3013682..aa7b2617834 100644 --- a/libs/libarchfpga/src/physical_types_util.h +++ b/libs/libarchfpga/src/physical_types_util.h @@ -284,7 +284,7 @@ int get_sub_tile_physical_pin(int sub_tile_index, * Given that each sub_tile's port that has exactly the same name has to be equivalent * one to the other, it is indifferent which port is returned. */ -t_physical_tile_port find_tile_port_by_name(t_physical_tile_type_ptr type, const char* port_name); +t_physical_tile_port find_tile_port_by_name(t_physical_tile_type_ptr type, std::string_view port_name); /** * @brief Returns the physical tile port given the port name and the corresponding sub tile diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index d1062ae0480..8737503da3b 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -194,9 +194,9 @@ static t_model* get_model(t_arch* arch, std::string model) { /** @brief Returns the physical or logical type by its name */ template -static T* get_type_by_name(const char* type_name, std::vector& types) { +static T* get_type_by_name(std::string_view type_name, std::vector& types) { for (auto& type : types) { - if (0 == strcmp(type.name, type_name)) { + if (type.name == type_name) { return &type; } } @@ -1076,10 +1076,10 @@ struct ArchReader { continue; // Check for duplicates - auto is_duplicate = [name](t_logical_block_type l) { return std::string(l.name) == name; }; + auto is_duplicate = [name](const t_logical_block_type& l)-> bool { return l.name == name; }; VTR_ASSERT(std::find_if(ltypes_.begin(), ltypes_.end(), is_duplicate) == ltypes_.end()); - ltype.name = vtr::strdup(name.c_str()); + ltype.name = name; ltype.index = ++index; auto pb_type = new t_pb_type; @@ -1969,7 +1969,7 @@ struct ArchReader { if (!has_valid_sites) continue; - ptype.name = vtr::strdup(name.c_str()); + ptype.name = name; ptype.index = ++index; ptype.width = ptype.height = ptype.area = 1; ptype.capacity = 0; @@ -2089,7 +2089,7 @@ struct ArchReader { // Create constant complex block t_logical_block_type block; - block.name = vtr::strdup(const_block_.c_str()); + block.name = const_block_; block.index = ltypes_.size(); auto pb_type = new t_pb_type; @@ -2199,7 +2199,7 @@ struct ArchReader { std::vector> const_cells{arch_->gnd_cell, arch_->vcc_cell}; // Create constant tile t_physical_tile_type constant; - constant.name = vtr::strdup(const_block_.c_str()); + constant.name = const_block_; constant.index = ptypes_.size(); constant.width = constant.height = constant.area = 1; constant.capacity = 1; @@ -2374,15 +2374,13 @@ struct ArchReader { size_t num_switches = pip_timing_models.size() + 2; std::string switch_name; - arch_->num_switches = num_switches; - if (num_switches > 0) { - arch_->Switches = new t_arch_switch_inf[num_switches]; + arch_->switches.resize(num_switches); } float R, Cin, Cint, Cout, Tdel; for (size_t i = 0; i < num_switches; ++i) { - t_arch_switch_inf* as = &arch_->Switches[i]; + t_arch_switch_inf* as = &arch_->switches[i]; R = Cin = Cint = Cout = Tdel = 0.0; SwitchType type; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 577171b1c9e..3950eb1b15b 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -318,38 +318,38 @@ static void ProcessComplexBlocks(pugi::xml_node Node, bool timing_enabled, const pugiutil::loc_data& loc_data); -static void ProcessSwitches(pugi::xml_node Node, - t_arch_switch_inf** Switches, - int* NumSwitches, - const bool timing_enabled, - const pugiutil::loc_data& loc_data); -static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, const int switch_index, t_arch_switch_inf* Switches, const pugiutil::loc_data& loc_data); -static void ProcessDirects(pugi::xml_node Parent, t_direct_inf** Directs, int* NumDirects, const t_arch_switch_inf* Switches, const int NumSwitches, const pugiutil::loc_data& loc_data); +static std::vector ProcessSwitches(pugi::xml_node Node, + const bool timing_enabled, + const pugiutil::loc_data& loc_data); + +static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, t_arch_switch_inf& arch_switch, const pugiutil::loc_data& loc_data); + +static std::vector ProcessDirects(pugi::xml_node Parent, + const std::vector& switches, + const pugiutil::loc_data& loc_data); + static void ProcessClockMetalLayers(pugi::xml_node parent, std::unordered_map& metal_layers, pugiutil::loc_data& loc_data); static void ProcessClockNetworks(pugi::xml_node parent, std::vector& clock_networks, - const t_arch_switch_inf* switches, - const int num_switches, + const std::vector& switches, pugiutil::loc_data& loc_data); static void ProcessClockSwitchPoints(pugi::xml_node parent, t_clock_network_arch& clock_network, - const t_arch_switch_inf* switches, - const int num_switches, + const std::vector& switches, pugiutil::loc_data& loc_data); static void ProcessClockRouting(pugi::xml_node parent, std::vector& clock_connections, - const t_arch_switch_inf* switches, - const int num_switches, + const std::vector& switches, pugiutil::loc_data& loc_data); -static void ProcessSegments(pugi::xml_node Parent, - std::vector& Segs, - const t_arch_switch_inf* Switches, - const int NumSwitches, - const bool timing_enabled, - const bool switchblocklist_required, - const pugiutil::loc_data& loc_data); + +static std::vector ProcessSegments(pugi::xml_node Parent, + const std::vector& switches, + const bool timing_enabled, + const bool switchblocklist_required, + const pugiutil::loc_data& loc_data); + static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiutil::loc_data& loc_data); static void ProcessCB_SB(pugi::xml_node Node, std::vector& list, const pugiutil::loc_data& loc_data); static void ProcessPower(pugi::xml_node parent, @@ -368,12 +368,19 @@ static bool attribute_to_bool(const pugi::xml_node node, const pugi::xml_attribute attr, const pugiutil::loc_data& loc_data); -static int find_switch_by_name(const t_arch& arch, const std::string& switch_name); +/** + * @brief Searches for a switch whose matches with the given name. + * @param switches Contains all the architecture switches. + * @param switch_name The name with which switch names are compared. + * @return A negative integer if no switch was found with the given name; otherwise + * the index of the matching switch is returned. + */ +static int find_switch_by_name(const std::vector& switches, std::string_view switch_name); static e_side string_to_side(const std::string& side_str); template -static T* get_type_by_name(const char* type_name, std::vector& types); +static T* get_type_by_name(std::string_view type_name, std::vector& types); /* * @@ -441,8 +448,7 @@ void XmlReadArch(const char* ArchFile, /* Process switches */ Next = get_single_child(architecture, "switchlist", loc_data); - ProcessSwitches(Next, &(arch->Switches), &(arch->num_switches), - timing_enabled, loc_data); + arch->switches = ProcessSwitches(Next, timing_enabled, loc_data); /* Process switchblocks. This depends on switches */ bool switchblocklist_required = (arch->SBType == CUSTOM); //require this section only if custom switchblocks are used @@ -450,8 +456,7 @@ void XmlReadArch(const char* ArchFile, /* Process segments. This depends on switches */ Next = get_single_child(architecture, "segmentlist", loc_data); - ProcessSegments(Next, arch->Segments, - arch->Switches, arch->num_switches, timing_enabled, switchblocklist_required, loc_data); + arch->Segments = ProcessSegments(Next, arch->switches, timing_enabled, switchblocklist_required, loc_data); Next = get_single_child(architecture, "switchblocklist", loc_data, SWITCHBLOCKLIST_REQD); if (Next) { @@ -472,9 +477,7 @@ void XmlReadArch(const char* ArchFile, /* Process directs */ Next = get_single_child(architecture, "directlist", loc_data, ReqOpt::OPTIONAL); if (Next) { - ProcessDirects(Next, &(arch->Directs), &(arch->num_directs), - arch->Switches, arch->num_switches, - loc_data); + arch->directs = ProcessDirects(Next, arch->switches, loc_data); } /* Process Clock Networks */ @@ -484,15 +487,15 @@ void XmlReadArch(const char* ArchFile, expect_only_children(Next, expected_children, loc_data); ProcessClockMetalLayers(Next, arch->clock_arch.clock_metal_layers, loc_data); + ProcessClockNetworks(Next, arch->clock_arch.clock_networks_arch, - arch->Switches, - arch->num_switches, + arch->switches, loc_data); + ProcessClockRouting(Next, arch->clock_arch.clock_connections_arch, - arch->Switches, - arch->num_switches, + arch->switches, loc_data); } @@ -750,7 +753,7 @@ static std::pair ProcessPinString(pugi::xml_node Locations, int token_index = 0; auto token = tokens[token_index]; - if (token.type != TOKEN_STRING || 0 != strcmp(token.data, type->name)) { + if (token.type != TOKEN_STRING || token.data != type->name) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Wrong physical type name of the port: %s\n", pin_loc_string); } @@ -775,7 +778,7 @@ static std::pair ProcessPinString(pugi::xml_node Locations, if (port == nullptr) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Port %s for %s could not be found: %s\n", - type->name, token.data, + type->name.c_str(), token.data, pin_loc_string); } int abs_first_pin_idx = port->absolute_first_pin_index; @@ -2135,7 +2138,7 @@ static void ProcessSwitchblockLocations(pugi::xml_node switchblock_locations, if (sb_switch_override_attr) { std::string sb_switch_override_str = sb_switch_override_attr.as_string(); //Use the specified switch - sb_switch_override = find_switch_by_name(arch, sb_switch_override_str); + sb_switch_override = find_switch_by_name(arch.switches, sb_switch_override_str); if (sb_switch_override == OPEN) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(switchblock_locations), @@ -2184,7 +2187,7 @@ static void ProcessSwitchblockLocations(pugi::xml_node switchblock_locations, if (internal_switch_attr) { std::string internal_switch_name = internal_switch_attr.as_string(); //Use the specified switch - internal_switch = find_switch_by_name(arch, internal_switch_name); + internal_switch = find_switch_by_name(arch.switches, internal_switch_name); if (internal_switch == OPEN) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(switchblock_locations), @@ -2935,7 +2938,7 @@ static void ProcessTiles(pugi::xml_node Node, auto [_, success] = tile_type_descriptors.insert(PhysicalTileType.name); if (!success) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(CurTileType), - "Duplicate tile descriptor name: '%s'.\n", PhysicalTileType.name); + "Duplicate tile descriptor name: '%s'.\n", PhysicalTileType.name.c_str()); } //Warn that gridlocations is no longer supported @@ -2996,7 +2999,7 @@ static void ProcessTileProps(pugi::xml_node Node, /* Load type name */ auto Prop = get_attribute(Node, "name", loc_data).value(); - PhysicalTileType->name = vtr::strdup(Prop); + PhysicalTileType->name = Prop; /* Load properties */ PhysicalTileType->width = get_attribute(Node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1); @@ -3005,7 +3008,7 @@ static void ProcessTileProps(pugi::xml_node Node, if (atof(Prop) < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), - "Area for type %s must be non-negative\n", PhysicalTileType->name); + "Area for type %s must be non-negative\n", PhysicalTileType->name.c_str()); } } @@ -3041,7 +3044,7 @@ static t_pin_counts ProcessSubTilePorts(pugi::xml_node Parent, if (!subtile_success) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), "Duplicate port names in subtile '%s': port '%s'\n", - SubTile->name, port.name); + SubTile->name.c_str(), port.name); } //Push port @@ -3153,7 +3156,7 @@ static void ProcessTileEquivalentSites(pugi::xml_node Parent, if (count_children(Parent, "site", loc_data) < 1) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), - "There are no sites corresponding to this tile: %s.\n", SubTile->name); + "There are no sites corresponding to this tile: %s.\n", SubTile->name.c_str()); } CurSite = Parent.first_child(); @@ -3194,7 +3197,9 @@ static void ProcessEquivalentSiteDirectConnection(pugi::xml_node Parent, if (num_pins != LogicalBlockType->pb_type->num_pins) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), - "Pin definition differ between site %s and tile %s. User-defined pin mapping is required.\n", LogicalBlockType->pb_type->name, SubTile->name); + "Pin definition differ between site %s and tile %s. User-defined pin mapping is required.\n", + LogicalBlockType->pb_type->name, + SubTile->name.c_str()); } vtr::bimap directs_map; @@ -3221,7 +3226,7 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, if (count_children(Parent, "direct", loc_data) < 1) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), - "There are no direct pin mappings between site %s and tile %s.\n", site_name.c_str(), SubTile->name); + "There are no direct pin mappings between site %s and tile %s.\n", site_name.c_str(), SubTile->name.c_str()); } vtr::bimap directs_map; @@ -3248,7 +3253,7 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), "The number of pins specified in the direct pin mapping is " "not equivalent for Physical Tile %s and Logical Block %s.\n", - SubTile->name, LogicalBlockType->name); + SubTile->name.c_str(), LogicalBlockType->name.c_str()); } int num_pins = from_pins.second - from_pins.first; @@ -3261,7 +3266,7 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), "Duplicate logical pin (%d) to physical pin (%d) mappings found for " "Physical Tile %s and Logical Block %s.\n", - logical_pin.pin, physical_pin.pin, SubTile->name, LogicalBlockType->name); + logical_pin.pin, physical_pin.pin, SubTile->name.c_str(), LogicalBlockType->name.c_str()); } } @@ -3307,7 +3312,7 @@ static void ProcessPinLocations(pugi::xml_node Locations, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Sub Tile %s has a different pin location pattern (%s) with respect " "to the sibling sub tiles", - SubTile->name, Prop); + SubTile->name.c_str(), Prop); } } else { pin_locs->distribution = distribution; @@ -3351,18 +3356,18 @@ static void ProcessPinLocations(pugi::xml_node Locations, if ((x_offset < 0) || (x_offset >= PhysicalTileType->width)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), "'%d' is an invalid horizontal offset for type '%s' (must be within [0, %d]).\n", - x_offset, PhysicalTileType->name, PhysicalTileType->width - 1); + x_offset, PhysicalTileType->name.c_str(), PhysicalTileType->width - 1); } if ((y_offset < 0) || (y_offset >= PhysicalTileType->height)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), "'%d' is an invalid vertical offset for type '%s' (must be within [0, %d]).\n", - y_offset, PhysicalTileType->name, PhysicalTileType->height - 1); + y_offset, PhysicalTileType->name.c_str(), PhysicalTileType->height - 1); } if ((layer_offset < 0) || layer_offset >= num_of_avail_layer) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), "'%d' is an invalid layer offset for type '%s' (must be within [0, num_avail_layer-1]).\n", - y_offset, PhysicalTileType->name, PhysicalTileType->height - 1); + y_offset, PhysicalTileType->name.c_str(), PhysicalTileType->height - 1); } //Check for duplicate side specifications, since the code below silently overwrites if there are duplicates @@ -3395,8 +3400,8 @@ static void ProcessPinLocations(pugi::xml_node Locations, for (int w = 0; w < PhysicalTileType->width; ++w) { for (int h = 0; h < PhysicalTileType->height; ++h) { for (e_side side : TOTAL_2D_SIDES) { - for (auto token : pin_locs->assignments[sub_tile_index][w][h][l][side]) { - InstPort inst_port(token.c_str()); + for (const std::string& token : pin_locs->assignments[sub_tile_index][w][h][l][side]) { + InstPort inst_port(token); //A pin specification should contain only the block name, and not any instance count information if (inst_port.instance_low_index() != InstPort::UNSPECIFIED || inst_port.instance_high_index() != InstPort::UNSPECIFIED) { @@ -3409,7 +3414,7 @@ static void ProcessPinLocations(pugi::xml_node Locations, if (inst_port.instance_name() != SubTile->name) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Mismatched sub tile name in pin location specification (expected '%s' was '%s')", - SubTile->name, inst_port.instance_name().c_str()); + SubTile->name.c_str(), inst_port.instance_name().c_str()); } int pin_low_idx = inst_port.port_low_index(); @@ -3433,7 +3438,7 @@ static void ProcessPinLocations(pugi::xml_node Locations, } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Failed to find port named '%s' on block '%s'", - inst_port.port_name().c_str(), SubTile->name); + inst_port.port_name().c_str(), SubTile->name.c_str()); } } VTR_ASSERT(pin_low_idx >= 0); @@ -3456,7 +3461,7 @@ static void ProcessPinLocations(pugi::xml_node Locations, //Missing archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "Pin '%s.%s[%d]' has no pin location specified (a location is required for pattern=\"custom\")", - SubTile->name, port.name, ipin); + SubTile->name.c_str(), port.name, ipin); } } } @@ -3488,7 +3493,7 @@ static void ProcessSubTiles(pugi::xml_node Node, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), "No sub tile found for the Physical Tile %s.\n" "At least one sub tile is needed to correctly describe the Physical Tile.\n", - PhysicalTileType->name); + PhysicalTileType->name.c_str()); } // used to find duplicate subtile names @@ -3507,14 +3512,14 @@ static void ProcessSubTiles(pugi::xml_node Node, expect_only_attributes(CurSubTile, {"name", "capacity"}, loc_data); /* Load type name */ - auto name = vtr::strdup(get_attribute(CurSubTile, "name", loc_data).value()); + const char* name = get_attribute(CurSubTile, "name", loc_data).value(); //Check Sub Tile name duplicates auto [_, success] = sub_tile_names.insert(name); if (!success) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), "Duplicate Sub Tile names in tile '%s': Sub Tile'%s'\n", - PhysicalTileType->name, name); + PhysicalTileType->name.c_str(), name); } SubTile.name = name; @@ -3608,17 +3613,17 @@ static void ProcessComplexBlocks(pugi::xml_node Node, /* Load type name */ auto Prop = get_attribute(CurBlockType, "name", loc_data).value(); - LogicalBlockType.name = vtr::strdup(Prop); + LogicalBlockType.name = Prop; auto [_, success] = pb_type_descriptors.insert(LogicalBlockType.name); if (!success) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(CurBlockType), - "Duplicate pb_type descriptor name: '%s'.\n", LogicalBlockType.name); + "Duplicate pb_type descriptor name: '%s'.\n", LogicalBlockType.name.c_str()); } /* Load pb_type info to assign to the Logical Block Type */ LogicalBlockType.pb_type = new t_pb_type; - LogicalBlockType.pb_type->name = vtr::strdup(LogicalBlockType.name); + LogicalBlockType.pb_type->name = vtr::strdup(LogicalBlockType.name.c_str()); ProcessPb_Type(CurBlockType, LogicalBlockType.pb_type, nullptr, timing_enabled, arch, loc_data, pb_type_idx); LogicalBlockType.index = index; @@ -3634,16 +3639,15 @@ static void ProcessComplexBlocks(pugi::xml_node Node, } } -static void ProcessSegments(pugi::xml_node Parent, - std::vector& Segs, - const t_arch_switch_inf* Switches, - const int NumSwitches, - const bool timing_enabled, - const bool switchblocklist_required, - const pugiutil::loc_data& loc_data) { - int i, j, length; +static std::vector ProcessSegments(pugi::xml_node Parent, + const std::vector& switches, + const bool timing_enabled, + const bool switchblocklist_required, + const pugiutil::loc_data& loc_data) { const char* tmp; + std::vector Segs; + pugi::xml_node SubElem; pugi::xml_node Node; @@ -3662,7 +3666,7 @@ static void ProcessSegments(pugi::xml_node Parent, bool x_axis_seg_found = false; /*Flags to see if we have any x-directed segment type specified*/ bool y_axis_seg_found = false; /*Flags to see if we have any y-directed segment type specified*/ - for (i = 0; i < NumSegs; ++i) { + for (int i = 0; i < NumSegs; ++i) { /* Get segment name */ tmp = get_attribute(Node, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { @@ -3682,7 +3686,7 @@ static void ProcessSegments(pugi::xml_node Parent, } /* Get segment length */ - length = 1; /* DEFAULT */ + int length = 1; /* DEFAULT */ tmp = get_attribute(Node, "length", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (tmp) { if (strcmp(tmp, "longline") == 0) { @@ -3786,16 +3790,12 @@ static void ProcessSegments(pugi::xml_node Parent, tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(""); if (strlen(tmp) != 0) { /* Match names */ - for (j = 0; j < NumSwitches; ++j) { - if (0 == strcmp(tmp, Switches[j].name.c_str())) { - break; /* End loop so j is where we want it */ - } - } - if (j >= NumSwitches) { + int switch_idx = find_switch_by_name(switches, tmp); + if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), "'%s' is not a valid mux name.\n", tmp); } - Segs[i].arch_opin_between_dice_switch = j; + Segs[i].arch_opin_between_dice_switch = switch_idx; } /* Get the wire and opin switches, or mux switch if unidir */ @@ -3807,12 +3807,8 @@ static void ProcessSegments(pugi::xml_node Parent, //check if tag is defined in the architecture, otherwise we should look for and if(tmp){ /* Match names */ - for (j = 0; j < NumSwitches; ++j) { - if (0 == strcmp(tmp, Switches[j].name.c_str())) { - break; /* End loop so j is where we want it */ - } - } - if (j >= NumSwitches) { + int switch_idx = find_switch_by_name(switches, tmp); + if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), "'%s' is not a valid mux name.\n", tmp); } @@ -3820,8 +3816,8 @@ static void ProcessSegments(pugi::xml_node Parent, /* Unidir muxes must have the same switch * for wire and opin fanin since there is * really only the mux in unidir. */ - Segs[i].arch_wire_switch = j; - Segs[i].arch_opin_switch = j; + Segs[i].arch_wire_switch = switch_idx; + Segs[i].arch_opin_switch = switch_idx; } else { //if a general mux is not defined, we should look for specific mux for each direction in the architecture file SubElem = get_single_child(Node, "mux_inc", loc_data, ReqOpt::OPTIONAL); @@ -3831,12 +3827,8 @@ static void ProcessSegments(pugi::xml_node Parent, "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); } else{ /* Match names */ - for (j = 0; j < NumSwitches; ++j) { - if (0 == strcmp(tmp, Switches[j].name.c_str())) { - break; /* End loop so j is where we want it */ - } - } - if (j >= NumSwitches) { + int switch_idx = find_switch_by_name(switches, tmp); + if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), "'%s' is not a valid mux name.\n", tmp); } @@ -3844,8 +3836,8 @@ static void ProcessSegments(pugi::xml_node Parent, /* Unidir muxes must have the same switch * for wire and opin fanin since there is * really only the mux in unidir. */ - Segs[i].arch_wire_switch = j; - Segs[i].arch_opin_switch = j; + Segs[i].arch_wire_switch = switch_idx; + Segs[i].arch_opin_switch = switch_idx; } SubElem = get_single_child(Node, "mux_dec", loc_data, ReqOpt::OPTIONAL); @@ -3855,12 +3847,8 @@ static void ProcessSegments(pugi::xml_node Parent, "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); } else{ /* Match names */ - for (j = 0; j < NumSwitches; ++j) { - if (0 == strcmp(tmp, Switches[j].name.c_str())) { - break; /* End loop so j is where we want it */ - } - } - if (j >= NumSwitches) { + int switch_idx = find_switch_by_name(switches, tmp); + if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), "'%s' is not a valid mux name.\n", tmp); } @@ -3868,8 +3856,8 @@ static void ProcessSegments(pugi::xml_node Parent, /* Unidir muxes must have the same switch * for wire and opin fanin since there is * really only the mux in unidir. */ - Segs[i].arch_wire_switch_dec = j; - Segs[i].arch_opin_switch_dec = j; + Segs[i].arch_wire_switch_dec = switch_idx; + Segs[i].arch_opin_switch_dec = switch_idx; } } } @@ -3879,35 +3867,27 @@ static void ProcessSegments(pugi::xml_node Parent, tmp = get_attribute(SubElem, "name", loc_data).value(); /* Match names */ - for (j = 0; j < NumSwitches; ++j) { - if (0 == strcmp(tmp, Switches[j].name.c_str())) { - break; /* End loop so j is where we want it */ - } - } - if (j >= NumSwitches) { + int switch_idx = find_switch_by_name(switches, tmp); + if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), "'%s' is not a valid wire_switch name.\n", tmp); } - Segs[i].arch_wire_switch = j; + Segs[i].arch_wire_switch = switch_idx; SubElem = get_single_child(Node, "opin_switch", loc_data); tmp = get_attribute(SubElem, "name", loc_data).value(); /* Match names */ - for (j = 0; j < NumSwitches; ++j) { - if (0 == strcmp(tmp, Switches[j].name.c_str())) { - break; /* End loop so j is where we want it */ - } - } - if (j >= NumSwitches) { + switch_idx = find_switch_by_name(switches, tmp); + if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), "'%s' is not a valid opin_switch name.\n", tmp); } - Segs[i].arch_opin_switch = j; + Segs[i].arch_opin_switch = switch_idx; } /* Setup the CB list if they give one, otherwise use full */ Segs[i].cb.resize(length); - for (j = 0; j < length; ++j) { + for (int j = 0; j < length; ++j) { Segs[i].cb[j] = true; } SubElem = get_single_child(Node, "cb", loc_data, ReqOpt::OPTIONAL); @@ -3917,7 +3897,7 @@ static void ProcessSegments(pugi::xml_node Parent, /* Setup the SB list if they give one, otherwise use full */ Segs[i].sb.resize(length + 1); - for (j = 0; j < (length + 1); ++j) { + for (int j = 0; j < (length + 1); ++j) { Segs[i].sb[j] = true; } SubElem = get_single_child(Node, "sb", loc_data, ReqOpt::OPTIONAL); @@ -3936,6 +3916,8 @@ static void ProcessSegments(pugi::xml_node Parent, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), "Atleast one segment per-axis needs to get specified if no segments with non-specified (default) axis attribute exist."); } + + return Segs; } @@ -4077,7 +4059,7 @@ static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiu SubElem = get_first_child(Node, "switchfuncs", loc_data); read_sb_switchfuncs(SubElem, &sb, loc_data); - read_sb_wireconns(arch->Switches, arch->num_switches, Node, &sb, loc_data); + read_sb_wireconns(arch->switches, Node, &sb, loc_data); /* run error checks on switch blocks */ check_switchblock(&sb, arch); @@ -4148,12 +4130,9 @@ static void ProcessCB_SB(pugi::xml_node Node, std::vector& list, const pug } } -static void ProcessSwitches(pugi::xml_node Parent, - t_arch_switch_inf** Switches, - int* NumSwitches, - const bool timing_enabled, - const pugiutil::loc_data& loc_data) { - int i, j; +static std::vector ProcessSwitches(pugi::xml_node Parent, + const bool timing_enabled, + const pugiutil::loc_data& loc_data) { const char* type_name; const char* switch_name; ReqOpt TIMING_ENABLE_REQD = BoolToReqOpt(timing_enabled); @@ -4161,18 +4140,18 @@ static void ProcessSwitches(pugi::xml_node Parent, pugi::xml_node Node; /* Count the children and check they are switches */ - *NumSwitches = count_children(Parent, "switch", loc_data); + int n_switches = count_children(Parent, "switch", loc_data); + std::vector switches; /* Alloc switch list */ - *Switches = nullptr; - if (*NumSwitches > 0) { - (*Switches) = new t_arch_switch_inf[(*NumSwitches)]; + if (n_switches > 0) { + switches.resize(n_switches); } /* Load the switches. */ Node = get_first_child(Parent, "switch", loc_data); - for (i = 0; i < *NumSwitches; ++i) { - t_arch_switch_inf& arch_switch = (*Switches)[i]; + for (int i = 0; i < n_switches; ++i) { + t_arch_switch_inf& arch_switch = switches[i]; switch_name = get_attribute(Node, "name", loc_data).value(); @@ -4186,8 +4165,8 @@ static void ProcessSwitches(pugi::xml_node Parent, type_name = get_attribute(Node, "type", loc_data).value(); /* Check for switch name collisions */ - for (j = 0; j < i; ++j) { - if (0 == strcmp((*Switches)[j].name.c_str(), switch_name)) { + for (int j = 0; j < i; ++j) { + if (0 == strcmp(switches[j].name.c_str(), switch_name)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), "Two switches with the same name '%s' were found.\n", switch_name); @@ -4279,12 +4258,14 @@ static void ProcessSwitches(pugi::xml_node Parent, arch_switch.intra_tile = false; } - //Load the Tdel (which may be specfied with sub-tags) - ProcessSwitchTdel(Node, timing_enabled, i, (*Switches), loc_data); + //Load the Tdel (which may be specified with sub-tags) + ProcessSwitchTdel(Node, timing_enabled, arch_switch, loc_data); /* Get next switch element */ Node = Node.next_sibling(Node.name()); } + + return switches; } /* Processes the switch delay. Switch delay can be specified in two ways. @@ -4296,20 +4277,17 @@ static void ProcessSwitches(pugi::xml_node Parent, * * are specified as children of the switch node. In this case, Tdel * is not included as a property of the switch node (first way). */ -static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, const int switch_index, t_arch_switch_inf* Switches, const pugiutil::loc_data& loc_data) { - float Tdel_prop_value; - int num_Tdel_children; - +static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, t_arch_switch_inf& arch_switch, const pugiutil::loc_data& loc_data) { /* check if switch node has the Tdel property */ bool has_Tdel_prop = false; - Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED); + float Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED); if (Tdel_prop_value != UNDEFINED) { has_Tdel_prop = true; } /* check if switch node has Tdel children */ bool has_Tdel_children = false; - num_Tdel_children = count_children(Node, "Tdel", loc_data, ReqOpt::OPTIONAL); + int num_Tdel_children = count_children(Node, "Tdel", loc_data, ReqOpt::OPTIONAL); if (num_Tdel_children != 0) { has_Tdel_children = true; } @@ -4323,7 +4301,7 @@ static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, co /* get pointer to the switch's Tdel map, then read-in delay data into this map */ if (has_Tdel_prop) { /* delay specified as a constant */ - Switches[switch_index].set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, Tdel_prop_value); + arch_switch.set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, Tdel_prop_value); } else if (has_Tdel_children) { /* Delay specified as a function of switch fan-in. * Go through each Tdel child, read-in num_inputs and the delay value. @@ -4338,7 +4316,7 @@ static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, co archfpga_throw(loc_data.filename_c_str(), loc_data.line(Tdel_child), "Tdel node specified num_inputs (%d) that has already been specified by another Tdel node", num_inputs); } else { - Switches[switch_index].set_Tdel(num_inputs, Tdel_value); + arch_switch.set_Tdel(num_inputs, Tdel_value); seen_fanins.insert(num_inputs); } Tdel_child = Tdel_child.next_sibling(Tdel_child.name()); @@ -4350,50 +4328,38 @@ static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, co "Switch should contain intrinsic delay information if timing is enabled"); } else { /* set a default value */ - Switches[switch_index].set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, 0.); + arch_switch.set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, 0.); } } } -static void ProcessDirects(pugi::xml_node Parent, t_direct_inf** Directs, int* NumDirects, const t_arch_switch_inf* Switches, const int NumSwitches, const pugiutil::loc_data& loc_data) { - int i, j; - const char* direct_name; - const char* from_pin_name; - const char* to_pin_name; - const char* switch_name; - - pugi::xml_node Node; - +static std::vector ProcessDirects(pugi::xml_node Parent, + const std::vector& switches, + const pugiutil::loc_data& loc_data) { /* Count the children and check they are direct connections */ expect_only_children(Parent, {"direct"}, loc_data); - *NumDirects = count_children(Parent, "direct", loc_data); - - /* Alloc direct list */ - *Directs = nullptr; - if (*NumDirects > 0) { - *Directs = (t_direct_inf*)vtr::malloc(*NumDirects * sizeof(t_direct_inf)); - memset(*Directs, 0, (*NumDirects * sizeof(t_direct_inf))); - } + int num_directs = count_children(Parent, "direct", loc_data); + std::vector directs(num_directs); /* Load the directs. */ - Node = get_first_child(Parent, "direct", loc_data); - for (i = 0; i < *NumDirects; ++i) { + pugi::xml_node Node = get_first_child(Parent, "direct", loc_data); + for (int i = 0; i < num_directs; ++i) { expect_only_attributes(Node, {"name", "from_pin", "to_pin", "x_offset", "y_offset", "z_offset", "switch_name", "from_side", "to_side"}, loc_data); - direct_name = get_attribute(Node, "name", loc_data).value(); + const char* direct_name = get_attribute(Node, "name", loc_data).value(); /* Check for direct name collisions */ - for (j = 0; j < i; ++j) { - if (0 == strcmp((*Directs)[j].name, direct_name)) { + for (int j = 0; j < i; ++j) { + if (directs[j].name == direct_name) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), "Two directs with the same name '%s' were found.\n", direct_name); } } - (*Directs)[i].name = vtr::strdup(direct_name); + directs[i].name = direct_name; /* Figure out the source pin and sink pin name */ - from_pin_name = get_attribute(Node, "from_pin", loc_data).value(); - to_pin_name = get_attribute(Node, "to_pin", loc_data).value(); + const char* from_pin_name = get_attribute(Node, "from_pin", loc_data).value(); + const char* to_pin_name = get_attribute(Node, "to_pin", loc_data).value(); /* Check that to_pin and the from_pin are not the same */ if (0 == strcmp(to_pin_name, from_pin_name)) { @@ -4401,46 +4367,44 @@ static void ProcessDirects(pugi::xml_node Parent, t_direct_inf** Directs, int* N "The source pin and sink pin are the same: %s.\n", to_pin_name); } - (*Directs)[i].from_pin = vtr::strdup(from_pin_name); - (*Directs)[i].to_pin = vtr::strdup(to_pin_name); + directs[i].from_pin = from_pin_name; + directs[i].to_pin = to_pin_name; - (*Directs)[i].x_offset = get_attribute(Node, "x_offset", loc_data).as_int(0); - (*Directs)[i].y_offset = get_attribute(Node, "y_offset", loc_data).as_int(0); - (*Directs)[i].sub_tile_offset = get_attribute(Node, "z_offset", loc_data).as_int(0); + directs[i].x_offset = get_attribute(Node, "x_offset", loc_data).as_int(0); + directs[i].y_offset = get_attribute(Node, "y_offset", loc_data).as_int(0); + directs[i].sub_tile_offset = get_attribute(Node, "z_offset", loc_data).as_int(0); std::string from_side_str = get_attribute(Node, "from_side", loc_data, ReqOpt::OPTIONAL).value(); - (*Directs)[i].from_side = string_to_side(from_side_str); + directs[i].from_side = string_to_side(from_side_str); std::string to_side_str = get_attribute(Node, "to_side", loc_data, ReqOpt::OPTIONAL).value(); - (*Directs)[i].to_side = string_to_side(to_side_str); + directs[i].to_side = string_to_side(to_side_str); //Set the optional switch type - switch_name = get_attribute(Node, "switch_name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + const char* switch_name = get_attribute(Node, "switch_name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); if (switch_name != nullptr) { //Look-up the user defined switch - for (j = 0; j < NumSwitches; j++) { - if (0 == strcmp(switch_name, Switches[j].name.c_str())) { - break; //Found the switch - } - } - if (j >= NumSwitches) { + int switch_idx = find_switch_by_name(switches, switch_name); + if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), "Could not find switch named '%s' in switch list.\n", switch_name); } - (*Directs)[i].switch_type = j; //Save the correct switch index + directs[i].switch_type = switch_idx; //Save the correct switch index } else { //If not defined, use the delayless switch by default //TODO: find a better way of indicating this. Ideally, we would //specify the delayless switch index here, but it does not appear //to be defined at this point. - (*Directs)[i].switch_type = -1; + directs[i].switch_type = -1; } - (*Directs)[i].line = loc_data.line(Node); + directs[i].line = loc_data.line(Node); /* Should I check that the direct chain offset is not greater than the chip? How? */ /* Get next direct element */ Node = Node.next_sibling(Node.name()); } + + return directs; } static void ProcessClockMetalLayers(pugi::xml_node parent, @@ -4478,8 +4442,7 @@ static void ProcessClockMetalLayers(pugi::xml_node parent, static void ProcessClockNetworks(pugi::xml_node parent, std::vector& clock_networks, - const t_arch_switch_inf* switches, - const int num_switches, + const std::vector& switches, pugiutil::loc_data& loc_data) { std::vector expected_spine_attributes = {"name", "num_inst", "metal_layer", "starty", "endy", "x", "repeatx", "repeaty"}; std::vector expected_rib_attributes = {"name", "num_inst", "metal_layer", "startx", "endx", "y", "repeatx", "repeaty"}; @@ -4533,7 +4496,7 @@ static void ProcessClockNetworks(pugi::xml_node parent, clock_network.repeat.x = repeatx; clock_network.repeat.y = repeaty; - ProcessClockSwitchPoints(curr_type, clock_network, switches, num_switches, loc_data); + ProcessClockSwitchPoints(curr_type, clock_network, switches, loc_data); } // Parse rib @@ -4571,7 +4534,7 @@ static void ProcessClockNetworks(pugi::xml_node parent, clock_network.repeat.x = repeatx; clock_network.repeat.y = repeaty; - ProcessClockSwitchPoints(curr_type, clock_network, switches, num_switches, loc_data); + ProcessClockSwitchPoints(curr_type, clock_network, switches, loc_data); } // Currently their is only support for ribs and spines @@ -4589,8 +4552,7 @@ static void ProcessClockNetworks(pugi::xml_node parent, static void ProcessClockSwitchPoints(pugi::xml_node parent, t_clock_network_arch& clock_network, - const t_arch_switch_inf* switches, - const int num_switches, + const std::vector& switches, pugiutil::loc_data& loc_data) { std::vector expected_spine_drive_attributes = {"name", "type", "yoffset", "switch_name"}; std::vector expected_rib_drive_attributes = {"name", "type", "xoffset", "switch_name"}; @@ -4603,7 +4565,7 @@ static void ProcessClockSwitchPoints(pugi::xml_node parent, //TODO: currently only supporting one drive and one tap. Should change to support // multiple taps - VTR_ASSERT(num_switches != 2); + VTR_ASSERT(switches.size() != 2); //TODO: ensure switch name is unique for every switch of this clock network for (int i = 0; i < num_clock_switches; i++) { @@ -4626,13 +4588,8 @@ static void ProcessClockSwitchPoints(pugi::xml_node parent, // get switch index const char* switch_name = get_attribute(curr_switch, "switch_name", loc_data).value(); - int switch_idx; - for (switch_idx = 0; switch_idx < num_switches; switch_idx++) { - if (0 == strcmp(switch_name, switches[switch_idx].name.c_str())) { - break; // switch_idx has been found - } - } - if (switch_idx >= num_switches) { + int switch_idx = find_switch_by_name(switches, switch_name); + if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(curr_switch), "'%s' is not a valid switch name.\n", switch_name); } @@ -4677,8 +4634,7 @@ static void ProcessClockSwitchPoints(pugi::xml_node parent, static void ProcessClockRouting(pugi::xml_node parent, std::vector& clock_connections, - const t_arch_switch_inf* switches, - const int num_switches, + const std::vector& switches, pugiutil::loc_data& loc_data) { std::vector expected_attributes = {"from", "to", "switch", "fc_val", "locationx", "locationy"}; @@ -4698,13 +4654,8 @@ static void ProcessClockRouting(pugi::xml_node parent, const char* locationy = get_attribute(curr_connection, "locationy", loc_data, ReqOpt::OPTIONAL).value(); float fc = get_attribute(curr_connection, "fc_val", loc_data).as_float(0.); - int switch_idx; - for (switch_idx = 0; switch_idx < num_switches; switch_idx++) { - if (0 == strcmp(switch_name, switches[switch_idx].name.c_str())) { - break; // switch_idx has been found - } - } - if (switch_idx >= num_switches) { + int switch_idx = find_switch_by_name(switches, switch_name); + if (switch_idx < 0) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(curr_connection), "'%s' is not a valid switch name.\n", switch_name); } @@ -4780,10 +4731,9 @@ static void ProcessPower(pugi::xml_node parent, } } -/* Get the clock architcture */ +/* Get the clock architecture */ static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pugiutil::loc_data& loc_data) { pugi::xml_node Node; - int i; const char* tmp; clocks->num_global_clocks = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL); @@ -4798,7 +4748,7 @@ static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pug /* Load the clock info. */ Node = get_first_child(Parent, "clock", loc_data); - for (i = 0; i < clocks->num_global_clocks; ++i) { + for (int i = 0; i < clocks->num_global_clocks; ++i) { tmp = get_attribute(Node, "buffer_size", loc_data).value(); if (strcmp(tmp, "auto") == 0) { clocks->clock_inf[i].autosize_buffer = true; @@ -4836,15 +4786,15 @@ static bool attribute_to_bool(const pugi::xml_node node, return false; } -static int find_switch_by_name(const t_arch& arch, const std::string& switch_name) { - for (int iswitch = 0; iswitch < arch.num_switches; ++iswitch) { - const t_arch_switch_inf& arch_switch = arch.Switches[iswitch]; +static int find_switch_by_name(const std::vector& switches, std::string_view switch_name) { + for (int iswitch = 0; iswitch < (int)switches.size(); ++iswitch) { + const t_arch_switch_inf& arch_switch = switches[iswitch]; if (arch_switch.name == switch_name) { return iswitch; } } - return OPEN; + return -1; } static e_side string_to_side(const std::string& side_str) { @@ -4867,9 +4817,9 @@ static e_side string_to_side(const std::string& side_str) { } template -static T* get_type_by_name(const char* type_name, std::vector& types) { +static T* get_type_by_name(std::string_view type_name, std::vector& types) { for (auto& type : types) { - if (0 == strcmp(type.name, type_name)) { + if (type.name == type_name) { return &type; } } diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 06617fa620a..d23d3022baa 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -285,7 +285,7 @@ void check_rr_graph(const RRGraphView& rr_graph, continue; } VTR_LOG_ERROR("in check_rr_graph: node %d (%s) at (%d,%d) block=%s side=%s pin=%s has no fanin.\n", - inode, rr_graph.node_type_string(rr_node), rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), block_type->name, TOTAL_2D_SIDE_STRINGS[node_side], pin_name.c_str()); + inode, rr_graph.node_type_string(rr_node), rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node), block_type->name.c_str(), TOTAL_2D_SIDE_STRINGS[node_side], pin_name.c_str()); } } } else { diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index f13a1c7b686..c106073cf64 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -1449,7 +1449,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { report_error( "Incorrect number of pins (%zu != %u) in %zu pin_class in block %s", size, class_inf->num_pins, - class_idx, tile->name); + class_idx, tile->name.c_str()); } } inline const std::pair add_pin_class_pin(std::tuple& context, int ptc) final { @@ -1472,7 +1472,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { report_error( "Incorrect number of pins (%zu != %u) in %zu pin_class in block %s", pin_count, class_inf->num_pins, - class_idx, tile->name); + class_idx, tile->name.c_str()); } } @@ -1511,7 +1511,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { return tile->index; } inline const char* get_block_type_name(const t_physical_tile_type*& tile) final { - return tile->name; + return tile->name.c_str(); } inline int get_block_type_width(const t_physical_tile_type*& tile) final { return tile->width; @@ -1536,10 +1536,10 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { */ inline void set_block_type_name(const char* name, std::pair& context) final { const t_physical_tile_type* tile = context.first; - if (strcmp(tile->name, name) != 0) { + if (tile->name != name) { report_error( "Architecture file does not match RR graph's block name: arch uses name %s, RR graph uses name %s", - tile->name, name); + tile->name.c_str(), name); } } diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index 6b5634de641..b0193ea52c3 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -748,9 +748,9 @@ static void print_rr_index_info(const vtr::vectorname, physical_tile_->capacity); + prefix_unsplit.c_str(), fasm_prefixes.size(), physical_tile_->name.c_str(), physical_tile_->capacity); } grid_prefix = fasm_prefixes[sub_tile]; blk_prefix_ = grid_prefix + "."; diff --git a/utils/fasm/test/test_fasm.cpp b/utils/fasm/test/test_fasm.cpp index 2b750e76652..9ee9a142b48 100644 --- a/utils/fasm/test/test_fasm.cpp +++ b/utils/fasm/test/test_fasm.cpp @@ -228,7 +228,7 @@ static std::string get_pin_feature (size_t inode) { if (sub_tile_pin >= pin_lo && sub_tile_pin < pin_hi) { int port_pin = sub_tile_pin - pin_lo; - return vtr::string_fmt("PIN_%d_%d_%s_%s_%d", ilow, jlow, sub_tile_type->name, port.name, port_pin); + return vtr::string_fmt("PIN_%d_%d_%s_%s_%d", ilow, jlow, sub_tile_type->name.c_str(), port.name, port_pin); } } diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index d0a6ff6034e..debd89c8bd6 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -332,8 +332,7 @@ int main(int argc, const char **argv) { vpr_setup.RouterOpts, &vpr_setup.RoutingArch, vpr_setup.Segments, - Arch.Directs, - Arch.num_directs, + Arch.directs, is_flat); if(route_options.profile_source) { diff --git a/vpr/src/analytical_place/full_legalizer.cpp b/vpr/src/analytical_place/full_legalizer.cpp index 8f78785e6fe..1383a73b99b 100644 --- a/vpr/src/analytical_place/full_legalizer.cpp +++ b/vpr/src/analytical_place/full_legalizer.cpp @@ -6,10 +6,12 @@ */ #include "full_legalizer.h" + #include #include #include #include + #include "partial_placement.h" #include "ShowSetup.h" #include "ap_netlist_fwd.h" @@ -24,6 +26,7 @@ #include "pack.h" #include "physical_types.h" #include "place_constraints.h" +#include "place_macro.h" #include "vpr_api.h" #include "vpr_context.h" #include "vpr_error.h" @@ -56,13 +59,15 @@ class APClusterPlacer { private: // Get the macro for the given cluster block. t_pl_macro get_macro(ClusterBlockId clb_blk_id) { + const auto& place_macros = g_vpr_ctx.placement().blk_loc_registry().place_macros(); // Basically stolen from initial_placement.cpp:place_one_block // TODO: Make this a cleaner interface and share the code. - int imacro; - get_imacro_from_iblk(&imacro, clb_blk_id, g_vpr_ctx.placement().pl_macros); + int imacro = place_macros.get_imacro_from_iblk(clb_blk_id); + // If this block is part of a macro, return it. - if (imacro != -1) - return g_vpr_ctx.placement().pl_macros[imacro]; + if (imacro != -1) { + return place_macros[imacro]; + } // If not, create a "fake" macro with a single element. t_pl_macro_member macro_member; t_pl_offset block_offset(0, 0, 0, 0); @@ -84,11 +89,10 @@ class APClusterPlacer { APClusterPlacer() { // FIXME: This was stolen from place/place.cpp // it used a static method, just taking what I think I will need. - - auto& block_locs = g_vpr_ctx.mutable_placement().mutable_block_locs(); - auto& grid_blocks = g_vpr_ctx.mutable_placement().mutable_grid_blocks(); auto& blk_loc_registry = g_vpr_ctx.mutable_placement().mutable_blk_loc_registry(); - init_placement_context(block_locs, grid_blocks); + const auto& directs = g_vpr_ctx.device().arch->directs; + + init_placement_context(blk_loc_registry, directs); // stolen from place/place.cpp:alloc_and_load_try_swap_structs // FIXME: set cube_bb to false by hand, should be passed in. @@ -96,8 +100,7 @@ class APClusterPlacer { g_vpr_ctx.mutable_placement().compressed_block_grids = create_compressed_block_grids(); // Initialize the macros - const t_arch* arch = g_vpr_ctx.device().arch; - g_vpr_ctx.mutable_placement().pl_macros = alloc_and_load_placement_macros(arch->Directs, arch->num_directs); + blk_loc_registry.mutable_place_macros().alloc_and_load_placement_macros(directs); // TODO: The next few steps will be basically a direct copy of the initial // placement code since it does everything we need! It would be nice @@ -107,7 +110,7 @@ class APClusterPlacer { blk_loc_registry.clear_all_grid_locs(); // Deal with the placement constraints. - propagate_place_constraints(); + propagate_place_constraints(blk_loc_registry.place_macros()); mark_fixed_blocks(blk_loc_registry); diff --git a/vpr/src/base/CheckArch.cpp b/vpr/src/base/CheckArch.cpp index ee9204e96bf..93e77db3429 100644 --- a/vpr/src/base/CheckArch.cpp +++ b/vpr/src/base/CheckArch.cpp @@ -22,32 +22,32 @@ static void CheckSwitches(const t_arch& Arch) { int ipin_cblock_switch_index_between_dice = UNDEFINED; /* Check transistors in switches won't be less than minimum size */ - t_arch_switch_inf* CurSwitch = Arch.Switches; - for (int i = 0; i < Arch.num_switches; i++) { + for (int i = 0; i < (int)Arch.switches.size(); i++) { + const t_arch_switch_inf& CurSwitch = Arch.switches[i]; /* This assumes all segments have the same directionality */ - if (CurSwitch->buffered() + if (CurSwitch.buffered() && Arch.Segments[0].directionality == BI_DIRECTIONAL) { /* Largest resistance tri-state buffer would have a minimum * width transistor in the buffer pull-down and a min-width * pass transistoron the output. * Hence, largest R = 2 * largest_transistor_R. */ - if (CurSwitch->R > 2 * Arch.R_minW_nmos) { + if (CurSwitch.R > 2 * Arch.R_minW_nmos) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), 0, "Switch %s R value (%g) is greater than 2 * R_minW_nmos (%g).\n" "Refer to switchlist section of '%s'\n", - CurSwitch->name.c_str(), CurSwitch->R, (2 * Arch.R_minW_nmos)); + CurSwitch.name.c_str(), CurSwitch.R, (2 * Arch.R_minW_nmos)); } } else { /* Pass transistor switch */ - if (CurSwitch->R > Arch.R_minW_nmos) { + if (CurSwitch.R > Arch.R_minW_nmos) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), 0, "Switch %s R value (%g) is greater than R_minW_nmos (%g).\n" "Refer to switchlist section of '%s'\n", - CurSwitch->name.c_str(), CurSwitch->R, Arch.R_minW_nmos, get_arch_file_name()); + CurSwitch.name.c_str(), CurSwitch.R, Arch.R_minW_nmos, get_arch_file_name()); } } for (auto cb_switch_name = 0; cb_switch_name < (int)Arch.ipin_cblock_switch_name.size(); cb_switch_name++) { /* find the ipin cblock switch index, if it exists */ - if (Arch.Switches[i].name == Arch.ipin_cblock_switch_name[cb_switch_name]) { + if (Arch.switches[i].name == Arch.ipin_cblock_switch_name[cb_switch_name]) { if (cb_switch_name == 0) { ipin_cblock_switch_index = i; } else { @@ -64,13 +64,13 @@ static void CheckSwitches(const t_arch& Arch) { * index to point to a switch with a routing resource switch with a representative Tdel value. * See rr_graph.c:alloc_and_load_rr_switch_inf for more info */ if (ipin_cblock_switch_index != UNDEFINED) { - if (!Arch.Switches[ipin_cblock_switch_index].fixed_Tdel()) { + if (!Arch.switches[ipin_cblock_switch_index].fixed_Tdel()) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Not currently allowing an ipin cblock switch to have fanin dependent values"); } } if (ipin_cblock_switch_index_between_dice != UNDEFINED) { - if (!Arch.Switches[ipin_cblock_switch_index_between_dice].fixed_Tdel()) { + if (!Arch.switches[ipin_cblock_switch_index_between_dice].fixed_Tdel()) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Not currently allowing an ipin cblock switch to have fanin dependent values"); } diff --git a/vpr/src/base/SetupGrid.cpp b/vpr/src/base/SetupGrid.cpp index a7aaf214dd2..08e23567877 100644 --- a/vpr/src/base/SetupGrid.cpp +++ b/vpr/src/base/SetupGrid.cpp @@ -424,7 +424,7 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt if (startx > grid_width - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification startx (%s = %d) falls outside device horizontal range [%d,%d]\n", - type->name, xspec.start_expr.c_str(), startx, 0, grid_width - 1); + type->name.c_str(), xspec.start_expr.c_str(), startx, 0, grid_width - 1); } continue; //No instances will be created } @@ -432,7 +432,7 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt if (starty > grid_height - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification starty (%s = %d) falls outside device vertical range [%d,%d]\n", - type->name, yspec.start_expr.c_str(), starty, 0, grid_height - 1); + type->name.c_str(), yspec.start_expr.c_str(), starty, 0, grid_height - 1); } continue; //No instances will be created } @@ -441,14 +441,14 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt if (endx > grid_width - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification endx (%s = %d) falls outside device horizontal range [%d,%d]\n", - type->name, xspec.end_expr.c_str(), endx, 0, grid_width - 1); + type->name.c_str(), xspec.end_expr.c_str(), endx, 0, grid_width - 1); } } if (endy > grid_height - 1) { if (warn_out_of_range) { VTR_LOG_WARN("Block type '%s' grid location specification endy (%s = %d) falls outside device vertical range [%d,%d]\n", - type->name, yspec.end_expr.c_str(), endy, 0, grid_height - 1); + type->name.c_str(), yspec.end_expr.c_str(), endy, 0, grid_height - 1); } } @@ -456,13 +456,13 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt if (endx < startx) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification endx (%s = %d) can not come before startx (%s = %d) for block type '%s'", - xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->name); + xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->name.c_str()); } if (endy < starty) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification endy (%s = %d) can not come before starty (%s = %d) for block type '%s'", - yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->name); + yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->name.c_str()); } //The minimum increment is the block dimension @@ -471,7 +471,7 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification incrx for block type '%s' must be at least" " block width (%d) to avoid overlapping instances (was %s = %d)", - type->name, type->width, xspec.incr_expr.c_str(), incrx); + type->name.c_str(), type->width, xspec.incr_expr.c_str(), incrx); } VTR_ASSERT(type->height > 0); @@ -479,7 +479,7 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification incry for block type '%s' must be at least" " block height (%d) to avoid overlapping instances (was %s = %d)", - type->name, type->height, yspec.incr_expr.c_str(), incry); + type->name.c_str(), type->height, yspec.incr_expr.c_str(), incry); } //The minimum repeat is the region dimension @@ -488,7 +488,7 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification repeatx for block type '%s' must be at least" " the region width (%d) to avoid overlapping instances (was %s = %d)", - type->name, region_width, xspec.repeat_expr.c_str(), repeatx); + type->name.c_str(), region_width, xspec.repeat_expr.c_str(), repeatx); } size_t region_height = endy - starty + 1; //+1 since start/end are both inclusive @@ -496,7 +496,7 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Grid location specification repeaty for block type '%s' must be at least" " the region height (%d) to avoid overlapping instances (was %s = %d)", - type->name, region_height, xspec.repeat_expr.c_str(), repeaty); + type->name.c_str(), region_height, xspec.repeat_expr.c_str(), repeaty); } //VTR_LOG("Applying grid_loc_def for '%s' priority %d startx=%s=%zu, endx=%s=%zu, starty=%s=%zu, endx=%s=%zu,\n", @@ -538,7 +538,7 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt if (!seen_types.count(&type)) { VTR_LOG_WARN("Block type '%s' was not specified in device grid layout\n", - type.name); + type.name.c_str()); } } @@ -610,8 +610,8 @@ static void set_grid_block_type(int priority, " Existing block type '%s' at (%zu,%zu) has the same priority (%d) as new overlapping type '%s'." " The last specification will apply.\n", x_root, y_root, - max_priority_type_loc.type->name, max_priority_type_loc.x, max_priority_type_loc.y, - priority, type->name); + max_priority_type_loc.type->name.c_str(), max_priority_type_loc.x, max_priority_type_loc.y, + priority, type->name.c_str()); } //Mark all the grid tiles 'covered' by this block with the appropriate type @@ -733,19 +733,19 @@ static void CheckGrid(const DeviceGrid& grid) { if (tile_type != type) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, "Grid Location (%d,%d,%d) should have type '%s' (based on root location) but has type '%s'\n", - i, j, layer_num, type->name, type->name); + i, j, layer_num, type->name.c_str(), type->name.c_str()); } if (tile_width_offset != x_offset) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, "Grid Location (%d,%d,%d) of type '%s' should have width offset '%d' (based on root location) but has '%d'\n", - i, j, layer_num, type->name, x_offset, tile_width_offset); + i, j, layer_num, type->name.c_str(), x_offset, tile_width_offset); } if (tile_height_offset != y_offset) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, "Grid Location (%d,%d,%d) of type '%s' should have height offset '%d' (based on root location) but has '%d'\n", - i, j, layer_num, type->name, y_offset, tile_height_offset); + i, j, layer_num, type->name.c_str(), y_offset, tile_height_offset); } } } diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 583b5d805aa..13439e200c8 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -39,8 +39,7 @@ static void SetupRoutingArch(const t_arch& Arch, t_det_routing_arch* RoutingArch static void SetupTiming(const t_options& Options, const bool TimingEnabled, t_timing_inf* Timing); static void SetupSwitches(const t_arch& Arch, t_det_routing_arch* RoutingArch, - const t_arch_switch_inf* ArchSwitches, - int NumArchSwitches); + const std::vector& arch_switches); static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysis_opts); static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch); @@ -227,7 +226,7 @@ void SetupVPR(const t_options* options, segments = arch->Segments; - SetupSwitches(*arch, routingArch, arch->Switches, arch->num_switches); + SetupSwitches(*arch, routingArch, arch->switches); SetupRoutingArch(*arch, routingArch); SetupTiming(*options, timingenabled, timing); SetupPackerOpts(*options, packerOpts); @@ -355,12 +354,11 @@ static void SetupTiming(const t_options& Options, const bool TimingEnabled, t_ti */ static void SetupSwitches(const t_arch& Arch, t_det_routing_arch* RoutingArch, - const t_arch_switch_inf* ArchSwitches, - int NumArchSwitches) { + const std::vector& arch_switches) { auto& device_ctx = g_vpr_ctx.mutable_device(); - int switches_to_copy = NumArchSwitches; - int num_arch_switches = NumArchSwitches; + int switches_to_copy = (int)arch_switches.size(); + int num_arch_switches = (int)arch_switches.size();; find_ipin_cblock_switch_index(Arch, RoutingArch->wire_to_arch_ipin_switch, RoutingArch->wire_to_arch_ipin_switch_between_dice); @@ -370,10 +368,10 @@ static void SetupSwitches(const t_arch& Arch, /* Alloc the list now that we know the final num_arch_switches value */ device_ctx.arch_switch_inf.resize(num_arch_switches); for (int iswitch = 0; iswitch < switches_to_copy; iswitch++) { - device_ctx.arch_switch_inf[iswitch] = ArchSwitches[iswitch]; + device_ctx.arch_switch_inf[iswitch] = arch_switches[iswitch]; // TODO: AM: Since I am not sure whether replacing arch_switch_in with all_sw_inf, which contains the // information about intra-tile switched, would not break anything, for the time being, I decided to not remove it - device_ctx.all_sw_inf[iswitch] = ArchSwitches[iswitch]; + device_ctx.all_sw_inf[iswitch] = arch_switches[iswitch]; } /* Delayless switch for connecting sinks and sources with their pins. */ @@ -788,8 +786,8 @@ static void SetupServerOpts(const t_options& Options, t_server_opts* ServerOpts) static void find_ipin_cblock_switch_index(const t_arch& Arch, int& wire_to_arch_ipin_switch, int& wire_to_arch_ipin_switch_between_dice) { for (auto cb_switch_name_index = 0; cb_switch_name_index < (int)Arch.ipin_cblock_switch_name.size(); cb_switch_name_index++) { int ipin_cblock_switch_index = UNDEFINED; - for (int iswitch = 0; iswitch < Arch.num_switches; ++iswitch) { - if (Arch.Switches[iswitch].name == Arch.ipin_cblock_switch_name[cb_switch_name_index]) { + for (int iswitch = 0; iswitch < (int)Arch.switches.size(); ++iswitch) { + if (Arch.switches[iswitch].name == Arch.ipin_cblock_switch_name[cb_switch_name_index]) { if (ipin_cblock_switch_index != UNDEFINED) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Found duplicate switches named '%s'\n", Arch.ipin_cblock_switch_name[cb_switch_name_index].c_str()); diff --git a/vpr/src/base/blk_loc_registry.cpp b/vpr/src/base/blk_loc_registry.cpp index 3841524a450..70f809cdcd9 100644 --- a/vpr/src/base/blk_loc_registry.cpp +++ b/vpr/src/base/blk_loc_registry.cpp @@ -44,6 +44,14 @@ int BlkLocRegistry::net_pin_to_tile_pin_index(const ClusterNetId net_id, int net return this->tile_pin_index(pin_id); } +const PlaceMacros& BlkLocRegistry::place_macros() const { + return place_macros_; +} + +PlaceMacros& BlkLocRegistry::mutable_place_macros() { + return place_macros_; +} + void BlkLocRegistry::set_block_location(ClusterBlockId blk_id, const t_pl_loc& location) { const auto& device_ctx = g_vpr_ctx.device(); const auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -265,3 +273,18 @@ void BlkLocRegistry::revert_move_blocks(const t_pl_blocks_to_be_moved& blocks_af expected_transaction_ = e_expected_transaction::APPLY; } + +t_physical_tile_loc BlkLocRegistry::get_coordinate_of_pin(ClusterPinId pin) const { + const auto& cluster_ctx = g_vpr_ctx.clustering(); + + int pnum = tile_pin_index(pin); + ClusterBlockId block = cluster_ctx.clb_nlist.pin_block(pin); + + t_physical_tile_loc tile_loc; + t_pl_loc block_loc = block_locs()[block].loc; + tile_loc.x = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; + tile_loc.y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; + tile_loc.layer_num = block_loc.layer; + + return tile_loc; +} diff --git a/vpr/src/base/blk_loc_registry.h b/vpr/src/base/blk_loc_registry.h index 17df9883e0e..9d3704f2c1c 100644 --- a/vpr/src/base/blk_loc_registry.h +++ b/vpr/src/base/blk_loc_registry.h @@ -5,6 +5,7 @@ #include "vtr_vector_map.h" #include "vpr_types.h" #include "grid_block.h" +#include "place_macro.h" struct t_block_loc; struct t_pl_blocks_to_be_moved; @@ -16,7 +17,6 @@ struct t_pl_blocks_to_be_moved; * 2) grid_blocks stores which blocks (if any) are placed at a given location. * 3) physical_pins stores the mapping between the pins of a clustered block and * the pins of the physical tile where the clustered blocks is placed. - * */ class BlkLocRegistry { public: @@ -37,6 +37,13 @@ class BlkLocRegistry { ///@brief Clustered pin placement mapping with physical pin vtr::vector_map physical_pins_; + /** + * @brief Contains information about placement macros. + * A placement macro is a set of clustered blocks that must be placed + * in a way that is compliant with relative locations specified by the macro. + */ + PlaceMacros place_macros_; + public: const vtr::vector_map& block_locs() const; vtr::vector_map& mutable_block_locs(); @@ -53,6 +60,12 @@ class BlkLocRegistry { ///@brief Returns the physical pin of the tile, related to the given ClusterNedId, and the net pin index. int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index) const; + ///@brief Returns a constant reference to placement macros. + const PlaceMacros& place_macros() const; + + ///@brief Returns a mutable reference to placement macros. + PlaceMacros& mutable_place_macros(); + /** * @brief Performs error checking to see if location is legal for block type, * and sets the location and grid usage of the block if it is legal. @@ -122,6 +135,13 @@ class BlkLocRegistry { */ void revert_move_blocks(const t_pl_blocks_to_be_moved& blocks_affected); + /** + * @brief Returns the coordinates of a cluster pin + * @param pin The unique Id of the cluster pin whose coordinates is desired. + * @return The coordinates of the given pin. + */ + t_physical_tile_loc get_coordinate_of_pin(ClusterPinId pin) const; + enum class e_expected_transaction { APPLY, COMMIT_REVERT diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp index 66d0208031f..df77dae97ca 100644 --- a/vpr/src/base/place_and_route.cpp +++ b/vpr/src/base/place_and_route.cpp @@ -190,8 +190,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, arch->Chans, det_routing_arch, segment_inf, - arch->Directs, - arch->num_directs, + arch->directs, false); } success = route(router_net_list, @@ -203,8 +202,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, timing_info, delay_calc, arch->Chans, - arch->Directs, - arch->num_directs, + arch->directs, (attempt_count == 0) ? ScreenUpdatePriority::MAJOR : ScreenUpdatePriority::MINOR, is_flat); @@ -330,7 +328,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, placer_opts.place_chan_width = current; try_place(placement_net_list, placer_opts, annealing_sched, router_opts, analysis_opts, noc_opts, arch->Chans, det_routing_arch, segment_inf, - arch->Directs, arch->num_directs, + arch->directs, false); } @@ -344,8 +342,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, timing_info, delay_calc, arch->Chans, - arch->Directs, - arch->num_directs, + arch->directs, ScreenUpdatePriority::MINOR, is_flat); @@ -387,7 +384,7 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, det_routing_arch, segment_inf, router_opts, - arch->Directs, arch->num_directs, + arch->directs, &warnings, is_flat); @@ -456,7 +453,7 @@ t_chan_width init_chan(int cfactor, const t_chan_width_dist& chan_width_dist, t_ VTR_ASSERT(num_channels > 0); float separation = 1.0 / num_channels; /* Norm. distance between two channels. */ - for (size_t i = 0; i < grid.width(); ++i) { //-2 for no perim channels + for (size_t i = 0; i < grid.width(); ++i) { float x = float(i) / num_channels; chan_width.y_list[i] = compute_chan_width(cfactor, chan_y_dist, x, separation, graph_directionality); chan_width.y_list[i] = std::max(chan_width.y_list[i], 1); //Minimum channel width 1 diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index 4f2d5f6da06..2f0d1ff8716 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -283,9 +283,7 @@ static void processComplexBlock(pugi::xml_node clb_block, int* num_primitives, const pugiutil::loc_data& loc_data, ClusteredNetlist* clb_nlist) { - bool found; - int i, num_tokens = 0; - t_token* tokens; + int num_tokens = 0; const t_pb_type* pb_type = nullptr; auto& device_ctx = g_vpr_ctx.device(); @@ -294,7 +292,7 @@ static void processComplexBlock(pugi::xml_node clb_block, //Parse cb attributes auto block_name = pugiutil::get_attribute(clb_block, "name", loc_data); auto block_inst = pugiutil::get_attribute(clb_block, "instance", loc_data); - tokens = GetTokensFromString(block_inst.value(), &num_tokens); + t_token* tokens = GetTokensFromString(block_inst.value(), &num_tokens); if (num_tokens != 4 || tokens[0].type != TOKEN_STRING || tokens[1].type != TOKEN_OPEN_SQUARE_BRACKET || tokens[2].type != TOKEN_INT @@ -305,9 +303,9 @@ static void processComplexBlock(pugi::xml_node clb_block, } VTR_ASSERT(ClusterBlockId(vtr::atoi(tokens[2].data)) == index); - found = false; - for (const auto& type : device_ctx.logical_block_types) { - if (strcmp(type.name, tokens[0].data) == 0) { + bool found = false; + for (const t_logical_block_type& type : device_ctx.logical_block_types) { + if (type.name == tokens[0].data) { t_pb* pb = new t_pb; pb->name = vtr::strdup(block_name.value()); clb_nlist->create_block(block_name.value(), pb, &type); @@ -330,7 +328,7 @@ static void processComplexBlock(pugi::xml_node clb_block, auto clb_mode = pugiutil::get_attribute(clb_block, "mode", loc_data); found = false; - for (i = 0; i < pb_type->num_modes; i++) { + for (int i = 0; i < pb_type->num_modes; i++) { if (strcmp(clb_mode.value(), pb_type->modes[i].name) == 0) { clb_nlist->block_pb(index)->mode = i; found = true; @@ -364,7 +362,7 @@ void processAttrsParams(pugi::xml_node Parent, const char* child_name, T& atom_n std::string cval = Cur.text().get(); bool found = false; // Look for corresponding key-value in range from AtomNetlist - for (auto bitem : atom_net_range) { + for (const auto& bitem : atom_net_range) { if (bitem.first == cname) { if (bitem.second != cval) { // Found in AtomNetlist range, but values don't match @@ -384,7 +382,7 @@ void processAttrsParams(pugi::xml_node Parent, const char* child_name, T& atom_n } } // Check for attrs/params in AtomNetlist but not in .net file - for (auto bitem : atom_net_range) { + for (const auto& bitem : atom_net_range) { if (kvs.find(bitem.first) == kvs.end()) vpr_throw(VPR_ERROR_NET_F, netlist_file_name, loc_data.line(Parent), ".net file and .blif file do not match, %s %s missing in .net file.\n", diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 8f7df673b68..e824f20f712 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -494,7 +494,7 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { if (is_empty_type(&type)) continue; VTR_LOG("\tNetlist\n\t\t%d\tblocks of type: %s\n", - num_type_instances[&type], type.name); + num_type_instances[&type], type.name.c_str()); VTR_LOG("\tArchitecture\n"); for (const auto equivalent_tile : type.equivalent_tiles) { @@ -503,7 +503,7 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { num_instances = (int)device_ctx.grid.num_instances(equivalent_tile, -1); VTR_LOG("\t\t%d\tblocks of type: %s\n", - num_instances, equivalent_tile->name); + num_instances, equivalent_tile->name.c_str()); } } VTR_LOG("\n"); @@ -516,7 +516,7 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { } if (device_ctx.grid.num_instances(&type, -1) != 0) { - VTR_LOG("\tPhysical Tile %s:\n", type.name); + VTR_LOG("\tPhysical Tile %s:\n", type.name.c_str()); auto equivalent_sites = get_equivalent_sites_set(&type); @@ -526,7 +526,7 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { if (num_inst != 0) { util = float(num_type_instances[logical_block]) / num_inst; } - VTR_LOG("\tBlock Utilization: %.2f Logical Block: %s\n", util, logical_block->name); + VTR_LOG("\tBlock Utilization: %.2f Logical Block: %s\n", util, logical_block->name.c_str()); } } } @@ -837,8 +837,7 @@ void vpr_place(const Netlist<>& net_list, t_vpr_setup& vpr_setup, const t_arch& arch.Chans, &vpr_setup.RoutingArch, vpr_setup.Segments, - arch.Directs, - arch.num_directs, + arch.directs, is_flat); auto& filename_opts = vpr_setup.FileNameOpts; @@ -857,20 +856,16 @@ void vpr_load_placement(t_vpr_setup& vpr_setup, const t_arch& arch) { const auto& device_ctx = g_vpr_ctx.device(); auto& place_ctx = g_vpr_ctx.mutable_placement(); + auto& blk_loc_registry = place_ctx.mutable_blk_loc_registry(); const auto& filename_opts = vpr_setup.FileNameOpts; //Initialize placement data structures, which will be filled when loading placement - auto& block_locs = place_ctx.mutable_block_locs(); - GridBlock& grid_blocks = place_ctx.mutable_grid_blocks(); - init_placement_context(block_locs, grid_blocks); + init_placement_context(blk_loc_registry, arch.directs); //Load an existing placement from a file place_ctx.placement_id = read_place(filename_opts.NetFile.c_str(), filename_opts.PlaceFile.c_str(), - place_ctx.mutable_blk_loc_registry(), + blk_loc_registry, filename_opts.verify_file_digests, device_ctx.grid); - - //Ensure placement macros are loaded so that they can be drawn after placement (e.g. during routing) - place_ctx.pl_macros = alloc_and_load_placement_macros(arch.Directs, arch.num_directs); } RouteStatus vpr_route_flow(const Netlist<>& net_list, @@ -1039,8 +1034,7 @@ RouteStatus vpr_route_fixed_W(const Netlist<>& net_list, timing_info, delay_calc, arch.Chans, - arch.Directs, - arch.num_directs, + arch.directs, ScreenUpdatePriority::MAJOR, is_flat); @@ -1140,7 +1134,7 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi det_routing_arch, vpr_setup.Segments, router_opts, - arch.Directs, arch.num_directs, + arch.directs, &warnings, is_flat); //Initialize drawing, now that we have an RR graph diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index f9b90d0b60b..73a252a516a 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -362,9 +362,6 @@ struct PlacementContext : public Context { */ void unlock_loc_vars() { VTR_ASSERT_SAFE(!loc_vars_are_accessible_); loc_vars_are_accessible_ = true; } - ///@brief The pl_macros array stores all the placement macros (usually carry chains). - std::vector pl_macros; - ///@brief Stores ClusterBlockId of all movable clustered blocks (blocks that are not locked down to a single location) std::vector movable_blocks; diff --git a/vpr/src/base/vpr_types.cpp b/vpr/src/base/vpr_types.cpp index ff0755b58b0..c4a381d59f6 100644 --- a/vpr/src/base/vpr_types.cpp +++ b/vpr/src/base/vpr_types.cpp @@ -139,7 +139,7 @@ std::string t_ext_pin_util_targets::to_string() const { for (unsigned int itype = 0; itype < device_ctx.physical_tile_types.size(); ++itype) { if (is_empty_type(&device_ctx.physical_tile_types[itype])) continue; - auto blk_name = device_ctx.physical_tile_types[itype].name; + const std::string& blk_name = device_ctx.physical_tile_types[itype].name; ss << blk_name << ":"; @@ -264,7 +264,7 @@ std::string t_pack_high_fanout_thresholds::to_string() const { for (unsigned int itype = 0; itype < device_ctx.physical_tile_types.size(); ++itype) { if (is_empty_type(&device_ctx.physical_tile_types[itype])) continue; - auto blk_name = device_ctx.physical_tile_types[itype].name; + const std::string& blk_name = device_ctx.physical_tile_types[itype].name; ss << blk_name << ":"; diff --git a/vpr/src/draw/draw_basic.cpp b/vpr/src/draw/draw_basic.cpp index 68379fce558..64b3d49979f 100644 --- a/vpr/src/draw/draw_basic.cpp +++ b/vpr/src/draw/draw_basic.cpp @@ -797,10 +797,10 @@ void draw_placement_macros(ezgl::renderer* g) { } t_draw_coords* draw_coords = get_draw_coords_vars(); - const auto& place_ctx = g_vpr_ctx.placement(); const auto& block_locs = draw_state->get_graphics_blk_loc_registry_ref().block_locs(); + const auto& place_macros = draw_state->get_graphics_blk_loc_registry_ref().place_macros(); - for (const t_pl_macro& pl_macro : place_ctx.pl_macros) { + for (const t_pl_macro& pl_macro : place_macros.macros()) { //TODO: for now we just draw the bounding box of the macro, which is incorrect for non-rectangular macros... int xlow = std::numeric_limits::max(); diff --git a/vpr/src/pack/cluster.cpp b/vpr/src/pack/cluster.cpp index 93683858f3f..be4d54696be 100644 --- a/vpr/src/pack/cluster.cpp +++ b/vpr/src/pack/cluster.cpp @@ -250,7 +250,7 @@ std::map do_clustering(const t_packer_opts& pa VTR_LOGV(verbosity > 2, "Complex block %d: '%s' (%s) ", total_clb_num, cluster_legalizer.get_cluster_pb(legalization_cluster_id)->name, - cluster_legalizer.get_cluster_type(legalization_cluster_id)->name); + cluster_legalizer.get_cluster_type(legalization_cluster_id)->name.c_str()); VTR_LOGV(verbosity > 2, "."); //Progress dot for seed-block fflush(stdout); diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index 892d508f107..1f10e556ad1 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -507,7 +507,7 @@ bool try_intra_lb_route(t_lb_router_data* router_data, --inet; auto& atom_ctx = g_vpr_ctx.atom(); VTR_LOGV(verbosity > 3, "Net '%s' is impossible to route within proposed %s cluster\n", - atom_ctx.nlist.net_name(lb_nets[inet].atom_net_id).c_str(), router_data->lb_type->name); + atom_ctx.nlist.net_name(lb_nets[inet].atom_net_id).c_str(), router_data->lb_type->name.c_str()); is_routed = false; } router_data->pres_con_fac *= router_data->params.pres_fac_mult; diff --git a/vpr/src/pack/cluster_util.cpp b/vpr/src/pack/cluster_util.cpp index 25b4af68441..53cc2d6a818 100644 --- a/vpr/src/pack/cluster_util.cpp +++ b/vpr/src/pack/cluster_util.cpp @@ -1061,13 +1061,13 @@ void start_new_cluster(ClusterLegalizer& cluster_legalizer, } if (success) { - VTR_LOGV(verbosity > 2, "\tPASSED_SEED: Block Type %s\n", type->name); + VTR_LOGV(verbosity > 2, "\tPASSED_SEED: Block Type %s\n", type->name.c_str()); // If clustering succeeds return the new_cluster_id and type. legalization_cluster_id = new_cluster_id; block_type = type; break; } else { - VTR_LOGV(verbosity > 2, "\tFAILED_SEED: Block Type %s\n", type->name); + VTR_LOGV(verbosity > 2, "\tFAILED_SEED: Block Type %s\n", type->name.c_str()); } } diff --git a/vpr/src/pack/constraints_report.cpp b/vpr/src/pack/constraints_report.cpp index 6b671331c74..4d6b9a87e57 100644 --- a/vpr/src/pack/constraints_report.cpp +++ b/vpr/src/pack/constraints_report.cpp @@ -46,7 +46,7 @@ bool floorplan_constraints_regions_overfull(const ClusterLegalizer& cluster_lega floorplanning_ctx.overfull_partition_regions.push_back(pr); VTR_LOG("\n\nA partition including the following regions has been assigned %d blocks of type %s, " "but only has %d tiles of that type\n", - num_assigned_blocks, block_type.name, num_tiles); + num_assigned_blocks, block_type.name.c_str(), num_tiles); for (const Region& reg : regions) { const vtr::Rect& rect = reg.get_rect(); const auto [layer_low, layer_high] = reg.get_layer_range(); diff --git a/vpr/src/pack/lb_type_rr_graph.cpp b/vpr/src/pack/lb_type_rr_graph.cpp index 81a9437ef10..12082386275 100644 --- a/vpr/src/pack/lb_type_rr_graph.cpp +++ b/vpr/src/pack/lb_type_rr_graph.cpp @@ -48,7 +48,7 @@ static void print_lb_type_rr_graph(FILE* fp, const std::vector* alloc_and_load_all_lb_type_rr_graph() { std::vector* lb_type_rr_graphs; @@ -139,7 +139,7 @@ void echo_lb_type_rr_graphs(char* filename, std::vector* lb_t for (const auto& type : device_ctx.logical_block_types) { if (!is_empty_type(&type)) { fprintf(fp, "--------------------------------------------------------------\n"); - fprintf(fp, "Intra-Logic Block Routing Resource For Type %s\n", type.name); + fprintf(fp, "Intra-Logic Block Routing Resource For Type %s\n", type.name.c_str()); fprintf(fp, "--------------------------------------------------------------\n"); fprintf(fp, "\n"); print_lb_type_rr_graph(fp, lb_type_rr_graphs[type.index]); diff --git a/vpr/src/pack/noc_aware_cluster_util.cpp b/vpr/src/pack/noc_aware_cluster_util.cpp index 87f981605de..d807e5aa187 100644 --- a/vpr/src/pack/noc_aware_cluster_util.cpp +++ b/vpr/src/pack/noc_aware_cluster_util.cpp @@ -31,7 +31,7 @@ void update_noc_reachability_partitions(const std::vector& noc_atom const auto& grid = g_vpr_ctx.device().grid; t_logical_block_type_ptr logic_block_type = infer_logic_block_type(grid); - const char* logical_block_name = logic_block_type != nullptr ? logic_block_type->name : ""; + const char* logical_block_name = logic_block_type != nullptr ? logic_block_type->name.c_str() : ""; const size_t high_fanout_threshold = high_fanout_thresholds.get_threshold(logical_block_name); // get the total number of atoms diff --git a/vpr/src/pack/output_clustering.cpp b/vpr/src/pack/output_clustering.cpp index c659837c5fb..83949655b2b 100644 --- a/vpr/src/pack/output_clustering.cpp +++ b/vpr/src/pack/output_clustering.cpp @@ -7,6 +7,7 @@ #include #include #include +#include #include "cluster_legalizer.h" #include "clustered_netlist.h" @@ -28,11 +29,9 @@ #include "vpr_utils.h" #include "pack.h" -#define LINELENGTH 1024 -#define TAB_LENGTH 4 static void print_clustering_stats_header(); -static void print_clustering_stats(char* block_name, int num_block_type, float num_inputs_clocks, float num_outputs); +static void print_clustering_stats(std::string_view block_name, int num_block_type, float num_inputs_clocks, float num_outputs); /**************** Subroutine definitions ************************************/ @@ -192,13 +191,13 @@ static void print_clustering_stats_header() { VTR_LOG("---------- -------- ------------------------------------ --------------------------\n"); } -static void print_clustering_stats(char* block_name, int num_block_type, float num_inputs_clocks, float num_outputs) { +static void print_clustering_stats(std::string_view block_name, int num_block_type, float num_inputs_clocks, float num_outputs) { VTR_LOG( "%10s " "%8d " "%36g " "%26g ", - block_name, + block_name.data(), num_block_type, num_inputs_clocks, num_outputs); diff --git a/vpr/src/pack/pack.cpp b/vpr/src/pack/pack.cpp index 566ca03e3ae..dae3443900c 100644 --- a/vpr/src/pack/pack.cpp +++ b/vpr/src/pack/pack.cpp @@ -214,13 +214,13 @@ bool try_pack(t_packer_opts* packer_opts, resource_avail += ", "; } - resource_reqs += std::string(iter->first->name) + ": " + std::to_string(iter->second); + resource_reqs += iter->first->name + ": " + std::to_string(iter->second); int num_instances = 0; for (auto type : iter->first->equivalent_tiles) num_instances += grid.num_instances(type, -1); - resource_avail += std::string(iter->first->name) + ": " + std::to_string(num_instances); + resource_avail += iter->first->name + ": " + std::to_string(num_instances); } VPR_FATAL_ERROR(VPR_ERROR_OTHER, "Failed to find device which satisfies resource requirements required: %s (available %s)", resource_reqs.c_str(), resource_avail.c_str()); @@ -352,7 +352,7 @@ static bool try_size_device_grid(const t_arch& arch, if (util > 1.) { fits_on_device = false; } - VTR_LOG("\tBlock Utilization: %.2f Type: %s\n", util, type.name); + VTR_LOG("\tBlock Utilization: %.2f Type: %s\n", util, type.name.c_str()); } VTR_LOG("\n"); diff --git a/vpr/src/pack/pack_report.cpp b/vpr/src/pack/pack_report.cpp index c571a2737d9..2dded7cda8b 100644 --- a/vpr/src/pack/pack_report.cpp +++ b/vpr/src/pack/pack_report.cpp @@ -66,7 +66,7 @@ void report_packing_pin_usage(std::ostream& os, const VprContext& ctx) { if (total_input_pins[type] != 0) { os << "\t\tHistogram:\n"; auto input_histogram = build_histogram(inputs_used[type], 10, 0, total_input_pins[type]); - for (auto line : format_histogram(input_histogram)) { + for (const std::string& line : format_histogram(input_histogram)) { os << "\t\t" << line << "\n"; } } diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index 3b7c272cfc4..0c6745b85e2 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -199,9 +199,9 @@ void echo_pb_graph(char* filename) { fprintf(fp, "Physical Blocks Graph\n"); fprintf(fp, "--------------------------------------------\n\n"); - auto& device_ctx = g_vpr_ctx.device(); - for (auto& type : device_ctx.logical_block_types) { - fprintf(fp, "type %s\n", type.name); + const auto& device_ctx = g_vpr_ctx.device(); + for (const t_logical_block_type& type : device_ctx.logical_block_types) { + fprintf(fp, "type %s\n", type.name.c_str()); if (type.pb_graph_head) echo_pb_rec(type.pb_graph_head, 1, fp); } diff --git a/vpr/src/place/RL_agent_util.cpp b/vpr/src/place/RL_agent_util.cpp index e861c7b9407..bb662c988d0 100644 --- a/vpr/src/place/RL_agent_util.cpp +++ b/vpr/src/place/RL_agent_util.cpp @@ -32,7 +32,7 @@ std::pair, std::unique_ptr> create * - 1st state: includes 4 moves (Uniform / Median / Centroid / * * WeightedCentroid) * * If agent should propose block type as well as the mentioned * - * move types, 1st state Q-table size is: * + * move types, 1st state Q-table size is: * * 4 move types * number of block types in the netlist * * if not, the Q-table size is : 4 * * * diff --git a/vpr/src/place/analytic_placer.cpp b/vpr/src/place/analytic_placer.cpp index 4bb632fbdb7..9d1f2406656 100644 --- a/vpr/src/place/analytic_placer.cpp +++ b/vpr/src/place/analytic_placer.cpp @@ -5,7 +5,7 @@ # include # include # include -# include +# include # include "vpr_types.h" # include "vtr_time.h" @@ -104,22 +104,6 @@ struct EquationSystem { } }; -// helper function to find the index of macro that contains blk -// returns index in placementCtx.pl_macros, -// returns NO_MACRO if blk not in any macros -int imacro(ClusterBlockId blk) { - int macro_index; - get_imacro_from_iblk(¯o_index, blk, g_vpr_ctx.mutable_placement().pl_macros); - return macro_index; -} - -// helper fucntion to find the head (first block) of macro containing blk -// returns the ID of the head block -ClusterBlockId macro_head(ClusterBlockId blk) { - int macro_index = imacro(blk); - return g_vpr_ctx.mutable_placement().pl_macros[macro_index].members[0].blk_index; -} - // Stop optimizing once this many iterations of solve-legalize lead to negligible wirelength improvement constexpr int HEAP_STALLED_ITERATIONS_STOP = 15; @@ -232,7 +216,7 @@ void AnalyticPlacer::ap_place() { // cut-spreading logic blocks of type "blk_type", this will mostly legalize lower bound placement spread_start = timer.elapsed_sec(); CutSpreader spreader{this, blk_type}; // Legalizer - if (strcmp(blk_type->name, "io") != 0) { + if (blk_type->name != "io") { /* skip cut-spreading for IO blocks; they tend to cluster on 1 edge of the FPGA due to how cut-spreader works * in HeAP, cut-spreading is invoked only on LUT, DSP, RAM etc. * here, greedy legalization by spreader.strict_legalize() should be sufficient for IOs @@ -256,7 +240,7 @@ void AnalyticPlacer::ap_place() { // upper bound placement complete run_t = timer.elapsed_sec() - run_start; - print_run_stats(iter, timer.elapsed_sec(), run_t, blk_type->name, solve_blks.size(), solve_t, + print_run_stats(iter, timer.elapsed_sec(), run_t, blk_type->name.c_str(), solve_blks.size(), solve_t, spread_t, legal_t, solved_hpwl, spread_hpwl, legal_hpwl); } @@ -304,6 +288,7 @@ void AnalyticPlacer::build_legal_locations() { void AnalyticPlacer::init() { const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; auto& init_block_locs = blk_loc_registry_ref_.block_locs(); + auto& place_macros = blk_loc_registry_ref_.place_macros(); for (auto blk_id : clb_nlist.blocks()) { blk_locs.insert(blk_id, BlockLocation{}); @@ -325,7 +310,7 @@ void AnalyticPlacer::init() { if (!init_block_locs[blk_id].is_fixed && has_connections(blk_id)) // not fixed and has connections // matrix equation is formulated based on connections, so requires at least one connection - if (imacro(blk_id) == NO_MACRO || macro_head(blk_id) == blk_id) { + if (place_macros.get_imacro_from_iblk(blk_id) == NO_MACRO || place_macros.macro_head(blk_id) == blk_id) { // not in macro or head of macro // for macro, only the head (base) block of the macro is a free variable, the location of other macro // blocks can be calculated using offset of the head. They are not free variables in the equation system @@ -385,7 +370,7 @@ int AnalyticPlacer::total_hpwl() { */ void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - PlacementContext& place_ctx = g_vpr_ctx.mutable_placement(); + const auto& place_macros = blk_loc_registry_ref_.place_macros(); int row = 0; solve_blks.clear(); @@ -401,9 +386,11 @@ void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { } } // update row_num of macro members - for (auto& macro : place_ctx.pl_macros) - for (auto& member : macro.members) - row_num[member.blk_index] = row_num[macro_head(member.blk_index)]; + for (auto& macro : blk_loc_registry_ref_.place_macros().macros()) { + for (auto& member : macro.members) { + row_num[member.blk_index] = row_num[place_macros.macro_head(member.blk_index)]; + } + } } /* @@ -412,7 +399,7 @@ void AnalyticPlacer::setup_solve_blks(t_logical_block_type_ptr blkTypes) { * when formulating the matrix equations), an update for members is necessary */ void AnalyticPlacer::update_macros() { - for (auto& macro : g_vpr_ctx.mutable_placement().pl_macros) { + for (auto& macro : blk_loc_registry_ref_.place_macros().macros()) { ClusterBlockId head_id = macro.members[0].blk_index; bool mac_can_be_placed = macro_can_be_placed(macro, blk_locs[head_id].loc, true, blk_loc_registry_ref_); @@ -475,7 +462,7 @@ void AnalyticPlacer::stamp_weight_on_matrix(EquationSystem& es, ClusterBlockId var, ClusterBlockId eqn, double weight) { - PlacementContext& place_ctx = g_vpr_ctx.mutable_placement(); + const auto& place_macros = blk_loc_registry_ref_.place_macros(); // Return the x or y position of a block auto blk_p = [&](ClusterBlockId blk_id) { return dir ? blk_locs[blk_id].loc.y : blk_locs[blk_id].loc.x; }; @@ -490,8 +477,8 @@ void AnalyticPlacer::stamp_weight_on_matrix(EquationSystem& es, } else { // var is not movable, stamp weight on rhs vector es.add_rhs(eqn_row, -v_pos * weight); } - if (imacro(var) != NO_MACRO) { // var is part of a macro, stamp on rhs vector - auto& members = place_ctx.pl_macros[imacro(var)].members; + if (place_macros.get_imacro_from_iblk(var) != NO_MACRO) { // var is part of a macro, stamp on rhs vector + auto& members = place_macros[place_macros.get_imacro_from_iblk(var)].members; for (auto& member : members) { // go through macro members to find the right member block if (member.blk_index == var) es.add_rhs(eqn_row, -(dir ? member.offset.y : member.offset.x) * weight); @@ -778,7 +765,7 @@ void AnalyticPlacer::print_place(const char* place_file) { for (auto blk_id : clb_nlist.blocks()) { fprintf(fp, "%-25s %-18s %-12s %-25s %-5d %-5d %-10d #%-13zu %-8s\n", clb_nlist.block_name(blk_id).c_str(), - clb_nlist.block_type(blk_id)->name, + clb_nlist.block_type(blk_id)->name.c_str(), clb_nlist.block_type(blk_id)->pb_type->name, clb_nlist.block_pb(blk_id)->name, blk_locs[blk_id].loc.x, diff --git a/vpr/src/place/analytic_placer.h b/vpr/src/place/analytic_placer.h index a1f4ff8dcbe..b73b3486f57 100644 --- a/vpr/src/place/analytic_placer.h +++ b/vpr/src/place/analytic_placer.h @@ -99,22 +99,6 @@ extern int DONT_SOLVE; // sentinel for blks not part of a placement macro extern int NO_MACRO; -/* - * @brief helper function to find the index of macro that contains blk - * returns index in placementCtx.pl_macros, NO_MACRO if blk not in any macros - */ -int imacro(ClusterBlockId blk); - -/* - * @brief helper function to find the head block of the macro that contains blk - * placement macro head is the base of the macro, where the locations of the other macro members can be - * calculated using base.loc + member.offset. - * Only the placement of macro head is calculated directly from AP, the position of other macro members need - * to be calculated later using above formula. - * - * returns the ID of the head block - */ -ClusterBlockId macro_head(ClusterBlockId blk); class AnalyticPlacer { public: diff --git a/vpr/src/place/centroid_move_generator.cpp b/vpr/src/place/centroid_move_generator.cpp index 9f00a5b89a4..45ba9121719 100644 --- a/vpr/src/place/centroid_move_generator.cpp +++ b/vpr/src/place/centroid_move_generator.cpp @@ -1,26 +1,18 @@ #include "centroid_move_generator.h" #include "vpr_types.h" #include "globals.h" -#include "directed_moves_util.h" #include "place_constraints.h" #include "placer_state.h" #include "move_utils.h" #include - -// Static member variable definitions -vtr::vector> CentroidMoveGenerator::noc_group_clusters_; -vtr::vector> CentroidMoveGenerator::noc_group_routers_; -vtr::vector CentroidMoveGenerator::cluster_to_noc_grp_; -std::map CentroidMoveGenerator::noc_router_to_noc_group_; - - CentroidMoveGenerator::CentroidMoveGenerator(PlacerState& placer_state, e_reward_function reward_function, vtr::RngContainer& rng) : MoveGenerator(placer_state, reward_function, rng) - , noc_attraction_w_(0.0f) + , weighted_(false) + , noc_attraction_weight_(0.0f) , noc_attraction_enabled_(false) {} CentroidMoveGenerator::CentroidMoveGenerator(PlacerState& placer_state, @@ -29,25 +21,18 @@ CentroidMoveGenerator::CentroidMoveGenerator(PlacerState& placer_state, float noc_attraction_weight, size_t high_fanout_net) : MoveGenerator(placer_state, reward_function, rng) - , noc_attraction_w_(noc_attraction_weight) + , noc_attraction_weight_(noc_attraction_weight) , noc_attraction_enabled_(true) { VTR_ASSERT(noc_attraction_weight > 0.0 && noc_attraction_weight <= 1.0); - - // check if static member variables are already initialized - if (!noc_group_clusters_.empty() && !noc_group_routers_.empty() && - !cluster_to_noc_grp_.empty() && !noc_router_to_noc_group_.empty()) { - return; - } else { - initialize_noc_groups(high_fanout_net); - } + initialize_noc_groups(high_fanout_net); } e_create_move CentroidMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, t_propose_action& proposed_action, float rlim, const t_placer_opts& placer_opts, - const PlacerCriticalities* /*criticalities*/) { + const PlacerCriticalities* criticalities) { auto& placer_state = placer_state_.get(); const auto& block_locs = placer_state.block_locs(); const auto& device_ctx = g_vpr_ctx.device(); @@ -75,8 +60,6 @@ e_create_move CentroidMoveGenerator::propose_move(t_pl_blocks_to_be_moved& block return e_create_move::ABORT; } - - t_pl_loc from = block_locs[b_from].loc; t_logical_block_type_ptr cluster_from_type = cluster_ctx.clb_nlist.block_type(b_from); t_physical_tile_type_ptr grid_from_type = device_ctx.grid.get_physical_type({from.x, from.y, from.layer}); @@ -86,10 +69,10 @@ e_create_move CentroidMoveGenerator::propose_move(t_pl_blocks_to_be_moved& block place_move_ctx.first_rlim, placer_opts.place_dm_rlim}; - t_pl_loc to, centroid; + t_pl_loc to; /* Calculate the centroid location*/ - calculate_centroid_loc(b_from, false, centroid, nullptr, noc_attraction_enabled_, noc_attraction_w_, blk_loc_registry); + t_pl_loc centroid = calculate_centroid_loc_(b_from, weighted_ ? criticalities : nullptr); // Centroid location is not necessarily a valid location, and the downstream location expects a valid // layer for the centroid location. So if the layer is not valid, we set it to the same layer as from loc. @@ -110,11 +93,11 @@ e_create_move CentroidMoveGenerator::propose_move(t_pl_blocks_to_be_moved& block } const std::vector& CentroidMoveGenerator::get_noc_group_routers(NocGroupId noc_grp_id) { - return CentroidMoveGenerator::noc_group_routers_[noc_grp_id]; + return noc_group_routers_[noc_grp_id]; } NocGroupId CentroidMoveGenerator::get_cluster_noc_group(ClusterBlockId blk_id) { - return CentroidMoveGenerator::cluster_to_noc_grp_[blk_id]; + return cluster_to_noc_grp_[blk_id]; } void CentroidMoveGenerator::initialize_noc_groups(size_t high_fanout_net) { @@ -215,3 +198,114 @@ void CentroidMoveGenerator::initialize_noc_groups(size_t high_fanout_net) { } } } + +t_pl_loc CentroidMoveGenerator::calculate_centroid_loc_(ClusterBlockId b_from, + const PlacerCriticalities* criticalities) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& blk_loc_registry = placer_state_.get().blk_loc_registry(); + const auto& block_locs = blk_loc_registry.block_locs(); + + float acc_weight = 0; + float acc_x = 0; + float acc_y = 0; + float acc_layer = 0; + float weight = 1; + + int from_block_layer_num = block_locs[b_from].loc.layer; + VTR_ASSERT(from_block_layer_num != OPEN); + + //iterate over the from block pins + for (ClusterPinId pin_id : cluster_ctx.clb_nlist.block_pins(b_from)) { + ClusterNetId net_id = cluster_ctx.clb_nlist.pin_net(pin_id); + + if (cluster_ctx.clb_nlist.net_is_ignored(net_id)) { + continue; + } + + /* Ignore the special case nets which only connects a block to itself * + * Experimentally, it was found that this case greatly degrade QoR */ + if (cluster_ctx.clb_nlist.net_sinks(net_id).size() == 1) { + ClusterBlockId source = cluster_ctx.clb_nlist.net_driver_block(net_id); + ClusterPinId sink_pin = *cluster_ctx.clb_nlist.net_sinks(net_id).begin(); + ClusterBlockId sink = cluster_ctx.clb_nlist.pin_block(sink_pin); + if (sink == source) { + continue; + } + } + + //if the pin is driver iterate over all the sinks + if (cluster_ctx.clb_nlist.pin_type(pin_id) == PinType::DRIVER) { + if (cluster_ctx.clb_nlist.net_is_ignored(net_id)) + continue; + + for (auto sink_pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { + /* Ignore if one of the sinks is the block itself * + * This case rarely happens but causes QoR degradation */ + if (pin_id == sink_pin_id) + continue; + int ipin = cluster_ctx.clb_nlist.pin_net_index(sink_pin_id); + if (criticalities != nullptr) { + weight = criticalities->criticality(net_id, ipin); + } else { + weight = 1; + } + + t_physical_tile_loc tile_loc = blk_loc_registry.get_coordinate_of_pin(sink_pin_id); + + acc_x += tile_loc.x * weight; + acc_y += tile_loc.y * weight; + acc_layer += tile_loc.layer_num * weight; + acc_weight += weight; + } + } + + //else the pin is sink --> only care about its driver + else { + int ipin = cluster_ctx.clb_nlist.pin_net_index(pin_id); + if (criticalities != nullptr) { + weight = criticalities->criticality(net_id, ipin); + } else { + weight = 1; + } + + ClusterPinId source_pin = cluster_ctx.clb_nlist.net_driver(net_id); + + t_physical_tile_loc tile_loc = blk_loc_registry.get_coordinate_of_pin(source_pin); + + acc_x += tile_loc.x * weight; + acc_y += tile_loc.y * weight; + acc_layer += tile_loc.layer_num * weight; + acc_weight += weight; + } + } + + if (noc_attraction_enabled_) { + NocGroupId noc_grp_id = CentroidMoveGenerator::get_cluster_noc_group(b_from); + + // check if the block belongs to a NoC group + if (noc_grp_id != NocGroupId::INVALID()) { + // get the routers in the associated NoC group + const auto& noc_routers = CentroidMoveGenerator::get_noc_group_routers(noc_grp_id); + float single_noc_weight = (acc_weight * noc_attraction_weight_) / (float)noc_routers.size(); + + acc_x *= (1.0f - noc_attraction_weight_); + acc_y *= (1.0f - noc_attraction_weight_); + acc_weight *= (1.0f - noc_attraction_weight_); + + for (ClusterBlockId router_blk_id : noc_routers) { + t_block_loc router_loc = block_locs[router_blk_id]; + acc_x += router_loc.loc.x * single_noc_weight; + acc_y += router_loc.loc.y * single_noc_weight; + acc_weight += single_noc_weight; + } + } + } + + t_pl_loc centroid; + //Calculate the centroid location + centroid.x = (int)std::round(acc_x / acc_weight); + centroid.y = (int)std::round(acc_y / acc_weight); + centroid.layer = (int)std::round(acc_layer / acc_weight); + + return centroid; +} \ No newline at end of file diff --git a/vpr/src/place/centroid_move_generator.h b/vpr/src/place/centroid_move_generator.h index 86b69ef2f00..17d5ec82924 100644 --- a/vpr/src/place/centroid_move_generator.h +++ b/vpr/src/place/centroid_move_generator.h @@ -60,7 +60,7 @@ class CentroidMoveGenerator : public MoveGenerator { * @param noc_grp_id The NoC group ID whose NoC routers are requested. * @return The clustered block ID of all NoC routers in the given NoC group. */ - static const std::vector& get_noc_group_routers(NocGroupId noc_grp_id); + const std::vector& get_noc_group_routers(NocGroupId noc_grp_id); /** * Returns the NoC group ID of clustered block. @@ -68,7 +68,7 @@ class CentroidMoveGenerator : public MoveGenerator { * @return The NoC group ID of the given clustered block or INVALID if * the given clustered block does not belong to any NoC groups. */ - static NocGroupId get_cluster_noc_group(ClusterBlockId blk_id); + NocGroupId get_cluster_noc_group(ClusterBlockId blk_id); private: e_create_move propose_move(t_pl_blocks_to_be_moved& blocks_affected, @@ -77,29 +77,46 @@ class CentroidMoveGenerator : public MoveGenerator { const t_placer_opts& placer_opts, const PlacerCriticalities* /*criticalities*/) override; + /** + * @brief Calculates the exact centroid location + * When NoC attraction is enabled, the computed centroid is slightly adjusted towards the location + * of NoC routers that are in the same NoC group b_from. + * + * @param b_from The block Id of the moving block + * @param criticalities A pointer to the placer criticalities which is used when + * calculating weighted centroid (send a NULL pointer in case of centroid) + * + * @return The calculated location is returned in centroid parameter that is sent by reference + */ + t_pl_loc calculate_centroid_loc_(ClusterBlockId b_from, + const PlacerCriticalities* criticalities); + + protected: + bool weighted_; + private: /** A value in range [0, 1] that specifies how much the centroid location * computation is biased towards the associated NoC routers*/ - float noc_attraction_w_; + float noc_attraction_weight_; /** Indicates whether the centroid calculation is NoC-biased.*/ bool noc_attraction_enabled_; /** Stores the ids of all non-router clustered blocks for each NoC group*/ - static vtr::vector> noc_group_clusters_; + vtr::vector> noc_group_clusters_; /** Stores NoC routers in each NoC group*/ - static vtr::vector> noc_group_routers_; + vtr::vector> noc_group_routers_; /** Specifies the NoC group that each block belongs to. A block cannot belong to more * than one NoC because this means those NoC groups can reach each other and form * a single NoC group. We use NocGroupId::INVALID to show that a block does not belong * to any NoC groups. This happens when a block is not reachable from any NoC router. * */ - static vtr::vector cluster_to_noc_grp_; + vtr::vector cluster_to_noc_grp_; /** Specifies the NoC group for each NoC router*/ - static std::map noc_router_to_noc_group_; + std::map noc_router_to_noc_group_; /** * @brief This function forms NoC groups by finding connected components @@ -109,7 +126,7 @@ class CentroidMoveGenerator : public MoveGenerator { * @param high_fanout_net All nets with a fanout larger than this number are * ignored when forming NoC groups. */ - static void initialize_noc_groups(size_t high_fanout_net); + void initialize_noc_groups(size_t high_fanout_net); }; #endif diff --git a/vpr/src/place/compressed_grid.cpp b/vpr/src/place/compressed_grid.cpp index dbf8e4fde56..0e78e6b99b7 100644 --- a/vpr/src/place/compressed_grid.cpp +++ b/vpr/src/place/compressed_grid.cpp @@ -179,7 +179,7 @@ void echo_compressed_grids(const char* filename, const std::vectorblk_loc_registry_ref_.place_macros(); size_t max_x = g_vpr_ctx.device().grid.width(); size_t max_y = g_vpr_ctx.device().grid.height(); @@ -146,9 +147,9 @@ void CutSpreader::init() { auto loc = ap->blk_locs[blk].loc; occupancy[loc.x][loc.y]++; // compute extent of macro member - if (imacro(blk) != NO_MACRO) { // if blk is a macro member + if (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) { // if blk is a macro member // only update macro heads' extent in blk_extents - set_macro_ext(macro_head(blk), loc.x, loc.y); + set_macro_ext(place_macros.macro_head(blk), loc.x, loc.y); } } } @@ -157,10 +158,10 @@ void CutSpreader::init() { ClusterBlockId blk = ClusterBlockId{(int)i}; if (clb_nlist.block_type(blk) == blk_type) { // Transfer macro extents to the actual macros structure; - if (imacro(blk) != NO_MACRO) { // if blk is a macro member + if (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) { // if blk is a macro member // update macro_extent for all macro members in macros // for single blocks (not in macro), macros[x][y] = {x, y, x, y} - vtr::Rect& me = blk_extents[macro_head(blk)]; + vtr::Rect& me = blk_extents[place_macros.macro_head(blk)]; auto loc = ap->blk_locs[blk].loc; auto& lme = macro_extent[loc.x][loc.y]; lme.expand_bounding_box(me); @@ -406,7 +407,7 @@ void CutSpreader::expand_regions() { std::pair CutSpreader::cut_region(SpreaderRegion& r, bool dir) { const DeviceContext& device_ctx = g_vpr_ctx.device(); const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - const auto& pl_macros = g_vpr_ctx.placement().pl_macros; + const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); // TODO: CutSpreader is not compatible with 3D FPGA VTR_ASSERT(device_ctx.grid.get_num_layers() == 1); @@ -504,7 +505,7 @@ std::pair CutSpreader::cut_region(SpreaderRegion& r, bool dir) { // while left subarea is over-utilized, move logic blocks to the right subarea one at a time while (pivot > 0 && rl.overused(ap->ap_cfg.beta)) { auto& move_blk = cut_blks.at(pivot); - int size = (imacro(move_blk) != NO_MACRO) ? pl_macros[imacro(move_blk)].members.size() : 1; + int size = (place_macros.get_imacro_from_iblk(move_blk) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(move_blk)].members.size() : 1; rl.n_blks -= size; rr.n_blks += size; pivot--; @@ -512,7 +513,7 @@ std::pair CutSpreader::cut_region(SpreaderRegion& r, bool dir) { // while right subarea is over-utilized, move logic blocks to the left subarea one at a time while (pivot < int(cut_blks.size()) - 1 && rr.overused(ap->ap_cfg.beta)) { auto& move_blk = cut_blks.at(pivot + 1); - int size = (imacro(move_blk) != NO_MACRO) ? pl_macros[imacro(move_blk)].members.size() : 1; + int size = (place_macros.get_imacro_from_iblk(move_blk) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(move_blk)].members.size() : 1; rl.n_blks += size; rr.n_blks -= size; pivot++; @@ -618,7 +619,7 @@ int CutSpreader::initial_source_cut(SpreaderRegion& r, bool dir, int& clearance_l, int& clearance_r) { - const auto& pl_macros = g_vpr_ctx.placement().pl_macros; + const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); // pivot is the midpoint of cut_blks in terms of total block size (counting macro members) // this ensures the initial partitions have similar number of blocks @@ -626,7 +627,7 @@ int CutSpreader::initial_source_cut(SpreaderRegion& r, int pivot = 0; // midpoint in terms of index of cut_blks for (auto& blk : cut_blks) { // if blk is part of macro (only macro heads in cut_blks, no macro members), add that macro's size - pivot_blks += (imacro(blk) != NO_MACRO) ? pl_macros[imacro(blk)].members.size() : 1; + pivot_blks += (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(blk)].members.size() : 1; if (pivot_blks >= r.n_blks / 2) break; pivot++; @@ -671,16 +672,16 @@ int CutSpreader::initial_target_cut(SpreaderRegion& r, int& right_blks_n, int& left_tiles_n, int& right_tiles_n) { - const auto& pl_macros = g_vpr_ctx.mutable_placement().pl_macros; + const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); // To achieve smallest difference in utilization, first move all tiles to right partition left_blks_n = 0, right_blks_n = 0; left_tiles_n = 0, right_tiles_n = r.n_tiles; // count number of blks in each partition, from initial source cut for (int i = 0; i <= init_source_cut; i++) - left_blks_n += (imacro(cut_blks.at(i)) != NO_MACRO) ? pl_macros[imacro(cut_blks.at(i))].members.size() : 1; + left_blks_n += (place_macros.get_imacro_from_iblk(cut_blks.at(i)) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(cut_blks.at(i))].members.size() : 1; for (int i = init_source_cut + 1; i < int(cut_blks.size()); i++) - right_blks_n += (imacro(cut_blks.at(i)) != NO_MACRO) ? pl_macros[imacro(cut_blks.at(i))].members.size() : 1; + right_blks_n += (place_macros.get_imacro_from_iblk(cut_blks.at(i)) != NO_MACRO) ? place_macros[place_macros.get_imacro_from_iblk(cut_blks.at(i))].members.size() : 1; int best_tgt_cut = -1; double best_deltaU = std::numeric_limits::max(); @@ -807,13 +808,13 @@ void CutSpreader::linear_spread_subarea(std::vector& cut_blks, void CutSpreader::strict_legalize() { auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist; const auto& block_locs = ap->blk_loc_registry_ref_.block_locs(); - const auto& pl_macros = g_vpr_ctx.placement().pl_macros; + const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); int max_x = g_vpr_ctx.device().grid.width(); int max_y = g_vpr_ctx.device().grid.height(); // clear the location of all blocks in place_ctx for (auto blk : clb_nlist.blocks()) { - if (!block_locs[blk].is_fixed && (ap->row_num[blk] != DONT_SOLVE || (imacro(blk) != NO_MACRO && ap->row_num[macro_head(blk)] != DONT_SOLVE))) { + if (!block_locs[blk].is_fixed && (ap->row_num[blk] != DONT_SOLVE || (place_macros.get_imacro_from_iblk(blk) != NO_MACRO && ap->row_num[place_macros.macro_head(blk)] != DONT_SOLVE))) { unbind_tile(block_locs[blk].loc); } } @@ -824,10 +825,11 @@ void CutSpreader::strict_legalize() { // This prioritizes the placement of longest macros over single blocks std::priority_queue> remaining; for (ClusterBlockId blk : ap->solve_blks) { - if (imacro(blk) != NO_MACRO) // blk is head block of a macro (only head blks are solved) - remaining.emplace(pl_macros[imacro(blk)].members.size(), blk); - else + if (place_macros.get_imacro_from_iblk(blk) != NO_MACRO) { // blk is head block of a macro (only head blks are solved) + remaining.emplace(place_macros[place_macros.get_imacro_from_iblk(blk)].members.size(), blk); + } else { remaining.emplace(1, blk); + } } /* @@ -939,7 +941,7 @@ void CutSpreader::strict_legalize() { int explore_limit = 2 * radius; // if blk is not a macro member - if (imacro(blk) == NO_MACRO) { + if (place_macros.get_imacro_from_iblk(blk) == NO_MACRO) { placed = try_place_blk(blk, nx, ny, @@ -1033,6 +1035,7 @@ bool CutSpreader::try_place_blk(ClusterBlockId blk, std::priority_queue>& remaining) { const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); // iteration at current radius has exceeded exploration limit, and a candidate sub_tile (best_subtile) is found // then blk is placed in best_subtile @@ -1060,7 +1063,7 @@ bool CutSpreader::try_place_blk(ClusterBlockId blk, * OR * 2) a 0.05% chance of acceptance. */ - if (bound_blk && imacro(bound_blk) != NO_MACRO) + if (bound_blk && place_macros.get_imacro_from_iblk(bound_blk) != NO_MACRO) // do not sub_tiles when the block placed on it is part of a macro, as they have higher priority continue; if (!exceeds_explore_limit) { // if still in exploration phase, find best_subtile with smallest best_inp_len @@ -1109,7 +1112,7 @@ bool CutSpreader::try_place_macro(ClusterBlockId blk, int nx, int ny, std::priority_queue>& remaining) { - const auto& pl_macros = g_vpr_ctx.placement().pl_macros; + const auto& place_macros = ap->blk_loc_registry_ref_.place_macros(); const auto& grid_blocks = ap->blk_loc_registry_ref_.grid_blocks(); const ClusteredNetlist& clb_nlist = g_vpr_ctx.clustering().clb_nlist; @@ -1135,15 +1138,15 @@ bool CutSpreader::try_place_macro(ClusterBlockId blk, // if the target location has a logic block, ensure it's not part of a macro // because a macro placed before the current one has higher priority (longer chain) ClusterBlockId bound = grid_blocks.block_at_location(target); - if (bound && imacro(bound) != NO_MACRO) { + if (bound && place_macros.get_imacro_from_iblk(bound) != NO_MACRO) { placement_impossible = true; break; } // place macro block into target vector along with its target location targets.emplace_back(visit_blk, target); - if (macro_head(visit_blk) == visit_blk) { // if visit_blk is the head block of the macro + if (place_macros.macro_head(visit_blk) == visit_blk) { // if visit_blk is the head block of the macro // push all macro members to visit queue along with their calculated positions - const std::vector& members = pl_macros[imacro(blk)].members; + const std::vector& members = place_macros[place_macros.get_imacro_from_iblk(blk)].members; for (auto member = members.begin() + 1; member != members.end(); ++member) { t_pl_loc mloc = target + member->offset; // calculate member_loc using (head blk location + offset) visit.emplace(member->blk_index, mloc); diff --git a/vpr/src/place/directed_moves_util.cpp b/vpr/src/place/directed_moves_util.cpp deleted file mode 100644 index b8a950d832a..00000000000 --- a/vpr/src/place/directed_moves_util.cpp +++ /dev/null @@ -1,146 +0,0 @@ - -#include "directed_moves_util.h" -#include "centroid_move_generator.h" - -t_physical_tile_loc get_coordinate_of_pin(ClusterPinId pin, - const BlkLocRegistry& blk_loc_registry) { - const auto& device_ctx = g_vpr_ctx.device(); - const auto& grid = device_ctx.grid; - const auto& cluster_ctx = g_vpr_ctx.clustering(); - - int pnum = blk_loc_registry.tile_pin_index(pin); - ClusterBlockId block = cluster_ctx.clb_nlist.pin_block(pin); - - t_physical_tile_loc tile_loc; - t_pl_loc block_loc = blk_loc_registry.block_locs()[block].loc; - tile_loc.x = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; - tile_loc.y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; - tile_loc.layer_num = block_loc.layer; - - tile_loc.x = std::max(std::min(tile_loc.x, (int)grid.width() - 2), 1); //-2 for no perim channels - tile_loc.y = std::max(std::min(tile_loc.y, (int)grid.height() - 2), 1); //-2 for no perim channels - - return tile_loc; -} - -void calculate_centroid_loc(ClusterBlockId b_from, - bool timing_weights, - t_pl_loc& centroid, - const PlacerCriticalities* criticalities, - bool noc_attraction_enabled, - float noc_attraction_weight, - const BlkLocRegistry& blk_loc_registry) { - const auto& cluster_ctx = g_vpr_ctx.clustering(); - const auto& block_locs = blk_loc_registry.block_locs(); - - float acc_weight = 0; - float acc_x = 0; - float acc_y = 0; - float acc_layer = 0; - float weight = 1; - - int from_block_layer_num = block_locs[b_from].loc.layer; - VTR_ASSERT(from_block_layer_num != OPEN); - - //iterate over the from block pins - for (ClusterPinId pin_id : cluster_ctx.clb_nlist.block_pins(b_from)) { - ClusterNetId net_id = cluster_ctx.clb_nlist.pin_net(pin_id); - - if (cluster_ctx.clb_nlist.net_is_ignored(net_id)) { - continue; - } - - /* Ignore the special case nets which only connects a block to itself * - * Experimentally, it was found that this case greatly degrade QoR */ - if (cluster_ctx.clb_nlist.net_sinks(net_id).size() == 1) { - ClusterBlockId source = cluster_ctx.clb_nlist.net_driver_block(net_id); - ClusterPinId sink_pin = *cluster_ctx.clb_nlist.net_sinks(net_id).begin(); - ClusterBlockId sink = cluster_ctx.clb_nlist.pin_block(sink_pin); - if (sink == source) { - continue; - } - } - - //if the pin is driver iterate over all the sinks - if (cluster_ctx.clb_nlist.pin_type(pin_id) == PinType::DRIVER) { - if (cluster_ctx.clb_nlist.net_is_ignored(net_id)) - continue; - - for (auto sink_pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { - /* Ignore if one of the sinks is the block itself * - * This case rarely happens but causes QoR degradation */ - if (pin_id == sink_pin_id) - continue; - int ipin = cluster_ctx.clb_nlist.pin_net_index(sink_pin_id); - if (timing_weights) { - weight = criticalities->criticality(net_id, ipin); - } else { - weight = 1; - } - - t_physical_tile_loc tile_loc = get_coordinate_of_pin(sink_pin_id, blk_loc_registry); - - acc_x += tile_loc.x * weight; - acc_y += tile_loc.y * weight; - acc_layer += tile_loc.layer_num * weight; - acc_weight += weight; - } - } - - //else the pin is sink --> only care about its driver - else { - int ipin = cluster_ctx.clb_nlist.pin_net_index(pin_id); - if (timing_weights) { - weight = criticalities->criticality(net_id, ipin); - } else { - weight = 1; - } - - ClusterPinId source_pin = cluster_ctx.clb_nlist.net_driver(net_id); - - t_physical_tile_loc tile_loc = get_coordinate_of_pin(source_pin, blk_loc_registry); - - acc_x += tile_loc.x * weight; - acc_y += tile_loc.y * weight; - acc_layer += tile_loc.layer_num * weight; - acc_weight += weight; - } - } - - if (noc_attraction_enabled) { - NocGroupId noc_grp_id = CentroidMoveGenerator::get_cluster_noc_group(b_from); - - // check if the block belongs to a NoC group - if (noc_grp_id != NocGroupId::INVALID()) { - // get the routers in the associated NoC group - const auto& noc_routers = CentroidMoveGenerator::get_noc_group_routers(noc_grp_id); - float single_noc_weight = (acc_weight * noc_attraction_weight) / (float)noc_routers.size(); - - acc_x *= (1.0f - noc_attraction_weight); - acc_y *= (1.0f - noc_attraction_weight); - acc_weight *= (1.0f - noc_attraction_weight); - - for (ClusterBlockId router_blk_id : noc_routers) { - t_block_loc router_loc = block_locs[router_blk_id]; - acc_x += router_loc.loc.x * single_noc_weight; - acc_y += router_loc.loc.y * single_noc_weight; - acc_weight += single_noc_weight; - } - } - } - - //Calculate the centroid location - centroid.x = (int)std::round(acc_x / acc_weight); - centroid.y = (int)std::round(acc_y / acc_weight); - centroid.layer = (int)std::round(acc_layer / acc_weight); -} - -static std::map available_reward_function = { - {"basic", e_reward_function::BASIC}, - {"nonPenalizing_basic", e_reward_function::NON_PENALIZING_BASIC}, - {"runtime_aware", e_reward_function::RUNTIME_AWARE}, - {"WLbiased_runtime_aware", e_reward_function::WL_BIASED_RUNTIME_AWARE}}; - -e_reward_function string_to_reward(const std::string& st) { - return available_reward_function[st]; -} diff --git a/vpr/src/place/directed_moves_util.h b/vpr/src/place/directed_moves_util.h deleted file mode 100644 index 4b78e424d92..00000000000 --- a/vpr/src/place/directed_moves_util.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef VPR_DIRECTED_MOVES_UTIL_H -#define VPR_DIRECTED_MOVES_UTIL_H - -#include "globals.h" -#include "timing_place.h" - -/** - * @brief enum represents the different reward functions - */ -enum class e_reward_function { - BASIC, ///@ directly uses the change of the annealing cost function - NON_PENALIZING_BASIC, ///@ same as basic reward function but with 0 reward if it's a hill-climbing one - RUNTIME_AWARE, ///@ same as NON_PENALIZING_BASIC but with normalizing with the runtime factor of each move type - WL_BIASED_RUNTIME_AWARE, ///@ same as RUNTIME_AWARE but more biased to WL cost (the factor of the bias is REWARD_BB_TIMING_RELATIVE_WEIGHT) - UNDEFINED_REWARD ///@ Used for manual moves -}; - -e_reward_function string_to_reward(const std::string& st); - -///@brief Helper function that returns the x, y coordinates of a pin -t_physical_tile_loc get_coordinate_of_pin(ClusterPinId pin, - const BlkLocRegistry& blk_loc_registry); - -/** - * @brief Calculates the exact centroid location - * - * This function is very useful in centroid and weightedCentroid moves as it calculates - * the centroid location. It returns the calculated location in centroid. - * - * When NoC attraction is enabled, the computed centroid is slightly adjusted towards the location - * of NoC routers that are in the same NoC group b_from. - * - * @param b_from The block Id of the moving block - * @param timing_weights Determines whether to calculate centroid or - * weighted centroid location. If true, use the timing weights (weighted centroid). - * @param criticalities A pointer to the placer criticalities which is used when - * calculating weighted centroid (send a NULL pointer in case of centroid) - * @param noc_attraction_enabled Indicates whether the computed centroid location - * should be adjusted towards NoC routers in the NoC group of the given block. - * @param noc_attraction_weight When NoC attraction is enabled, this weight - * specifies to which extent the computed centroid should be adjusted. A value - * in range [0, 1] is expected. - * - * @return The calculated location is returned in centroid parameter that is sent by reference - */ -void calculate_centroid_loc(ClusterBlockId b_from, - bool timing_weights, - t_pl_loc& centroid, - const PlacerCriticalities* criticalities, - bool noc_attraction_enabled, - float noc_attraction_weight, - const BlkLocRegistry& blk_loc_registry); - -inline void calculate_centroid_loc(ClusterBlockId b_from, - bool timing_weights, - t_pl_loc& centroid, - const PlacerCriticalities* criticalities, - const BlkLocRegistry& blk_loc_registry) { - calculate_centroid_loc(b_from, timing_weights, centroid, criticalities, false, 0.0f, blk_loc_registry); -} - -#endif diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 592c8ed0e20..8b8a198d451 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -12,13 +12,12 @@ #include "place_constraints.h" #include "move_utils.h" #include "region.h" -#include "directed_moves_util.h" #include "noc_place_utils.h" -#include "echo_files.h" #include #include + #ifdef VERBOSE void print_clb_placement(const char* fname); #endif @@ -66,7 +65,7 @@ static bool place_macro(int macros_max_num_tries, * Used for relative placement, so that the blocks that are more difficult to place can be placed first during initial placement. * A higher score indicates that the block is more difficult to place. */ -static vtr::vector assign_block_scores(); +static vtr::vector assign_block_scores(const PlaceMacros& place_macros); /** * @brief Tries to find y coordinate for macro head location based on macro direction @@ -259,7 +258,7 @@ static void check_initial_placement_legality(const vtr::vector_mapname, + cluster_ctx.clb_nlist.block_type(blk_id)->name.c_str(), MAX_INIT_PLACE_ATTEMPTS - 1); unplaced_blocks++; } @@ -283,13 +282,13 @@ static void check_initial_placement_legality(const vtr::vector_mapindex != logical_block_type.index) { VPR_FATAL_ERROR(VPR_ERROR_PLACE, "Clustered block %d of logical type %s was mistakenly marked as logical type %s.\n", (size_t)movable_blk_id, - cluster_ctx.clb_nlist.block_type(movable_blk_id)->name, - logical_block_type.name); + cluster_ctx.clb_nlist.block_type(movable_blk_id)->name.c_str(), + logical_block_type.name.c_str()); } } } @@ -437,7 +436,7 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, continue; } - t_physical_tile_loc tile_loc = get_coordinate_of_pin(sink_pin_id, blk_loc_registry); + t_physical_tile_loc tile_loc = blk_loc_registry.get_coordinate_of_pin(sink_pin_id); if (find_layer) { VTR_ASSERT(tile_loc.layer_num != OPEN); layer_count[tile_loc.layer_num]++; @@ -457,7 +456,7 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, continue; } - t_physical_tile_loc tile_loc = get_coordinate_of_pin(source_pin, blk_loc_registry); + t_physical_tile_loc tile_loc = blk_loc_registry.get_coordinate_of_pin(source_pin); if (find_layer) { VTR_ASSERT(tile_loc.layer_num != OPEN); layer_count[tile_loc.layer_num]++; @@ -952,12 +951,9 @@ static bool place_macro(int macros_max_num_tries, return macro_placed; } -static vtr::vector assign_block_scores() { - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_ctx = g_vpr_ctx.placement(); - auto& floorplan_ctx = g_vpr_ctx.floorplanning(); - - auto& pl_macros = place_ctx.pl_macros; +static vtr::vector assign_block_scores(const PlaceMacros& place_macros) { + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& floorplan_ctx = g_vpr_ctx.floorplanning();; t_block_score score; @@ -987,7 +983,7 @@ static vtr::vector assign_block_scores() { } //go through placement macros and store size of macro for each block - for (const auto& pl_macro : pl_macros) { + for (const auto& pl_macro : place_macros.macros()) { int size = pl_macro.members.size(); for (const auto& pl_macro_member : pl_macro.members) { block_scores[pl_macro_member.blk_index].macro_size = size; @@ -1004,10 +1000,11 @@ static void place_all_blocks(const t_placer_opts& placer_opts, const char* constraints_file, BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& place_ctx = g_vpr_ctx.placement(); - auto& device_ctx = g_vpr_ctx.device(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& device_ctx = g_vpr_ctx.device(); + const auto& place_macros = blk_loc_registry.place_macros(); auto blocks = cluster_ctx.clb_nlist.blocks(); + int number_of_unplaced_blks_in_curr_itr; //keep tracks of which block types can not be placed in each iteration @@ -1076,8 +1073,7 @@ static void place_all_blocks(const t_placer_opts& placer_opts, //add current block to list to ensure it will be placed sooner in the next iteration in initial placement number_of_unplaced_blks_in_curr_itr++; block_scores[blk_id].failed_to_place_in_prev_attempts++; - int imacro; - get_imacro_from_iblk(&imacro, blk_id, place_ctx.pl_macros); + int imacro = place_macros.get_imacro_from_iblk(blk_id); if (imacro != -1) { //the block belongs to macro that contain a chain, we need to turn on dense placement in next iteration for that type of block unplaced_blk_type_in_curr_itr.insert(blk_id_type->index); } @@ -1106,8 +1102,8 @@ bool place_one_block(const ClusterBlockId blk_id, vtr::vector* block_scores, BlkLocRegistry& blk_loc_registry, vtr::RngContainer& rng) { - const std::vector& pl_macros = g_vpr_ctx.placement().pl_macros; const auto& block_locs = blk_loc_registry.block_locs(); + const auto& place_macros = blk_loc_registry.place_macros(); //Check if block has already been placed if (is_block_placed(blk_id, block_locs)) { @@ -1117,12 +1113,11 @@ bool place_one_block(const ClusterBlockId blk_id, bool placed_macro = false; //Lookup to see if the block is part of a macro - int imacro; - get_imacro_from_iblk(&imacro, blk_id, pl_macros); + int imacro = place_macros.get_imacro_from_iblk(blk_id); if (imacro != -1) { //If the block belongs to a macro, pass that macro to the placement routines VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\tBelongs to a macro %d\n", imacro); - const t_pl_macro& pl_macro = pl_macros[imacro]; + const t_pl_macro& pl_macro = place_macros[imacro]; placed_macro = place_macro(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, pl_macro, pad_loc_type, blk_types_empty_locs_in_grid, *block_scores, blk_loc_registry, rng); } else { //If it does not belong to a macro, create a macro with the one block and then pass to the placement routines @@ -1149,7 +1144,6 @@ static void alloc_and_load_movable_blocks(const vtr::vector_map block_scores = assign_block_scores(); + vtr::vector block_scores = assign_block_scores(place_macros); //Place all blocks place_all_blocks(placer_opts, block_scores, placer_opts.pad_loc_type, constraints_file, blk_loc_registry, rng); @@ -1214,11 +1209,4 @@ void initial_placement(const t_placer_opts& placer_opts, // ensure all blocks are placed and that NoC routing has no cycles check_initial_placement_legality(block_locs); - - //#ifdef VERBOSE - // VTR_LOG("At end of initial_placement.\n"); - // if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_INITIAL_CLB_PLACEMENT)) { - // print_clb_placement(getEchoFileName(E_ECHO_INITIAL_CLB_PLACEMENT)); - // } - //#endif } diff --git a/vpr/src/place/median_move_generator.cpp b/vpr/src/place/median_move_generator.cpp index 64c89df7806..2e982ac6425 100644 --- a/vpr/src/place/median_move_generator.cpp +++ b/vpr/src/place/median_move_generator.cpp @@ -90,53 +90,39 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ } const auto& net_bb_coords = cube_bb ? place_move_ctx.bb_coords[net_id] : union_bb; - //use the incremental update of the bb - ClusterBlockId bnum = cluster_ctx.clb_nlist.pin_block(pin_id); - int pnum = blk_loc_registry.tile_pin_index(pin_id); - VTR_ASSERT(pnum >= 0); - t_pl_loc block_loc = block_locs[bnum].loc; - t_physical_tile_type_ptr block_physical_type = physical_tile_type(block_loc); - int xold = block_loc.x + block_physical_type->pin_width_offset[pnum]; - int yold = block_loc.y + block_physical_type->pin_height_offset[pnum]; - int layer_old = block_loc.layer; - - xold = std::max(std::min(xold, (int)device_ctx.grid.width() - 2), 1); //-2 for no perim channels - yold = std::max(std::min(yold, (int)device_ctx.grid.height() - 2), 1); //-2 for no perim channels - layer_old = std::max(std::min(layer_old, (int)device_ctx.grid.get_num_layers() - 1), 0); + t_physical_tile_loc old_pin_loc = blk_loc_registry.get_coordinate_of_pin(pin_id); + t_physical_tile_loc new_pin_loc; //To calculate the bb incrementally while excluding the moving block //assume that the moving block is moved to a non-critical coord of the bb - int xnew; - if (net_bb_coords.xmin == xold) { - xnew = net_bb_coords.xmax; + if (net_bb_coords.xmin == old_pin_loc.x) { + new_pin_loc.x = net_bb_coords.xmax; } else { - xnew = net_bb_coords.xmin; + new_pin_loc.x = net_bb_coords.xmin; } - int ynew; - if (net_bb_coords.ymin == yold) { - ynew = net_bb_coords.ymax; + if (net_bb_coords.ymin == old_pin_loc.y) { + new_pin_loc.y = net_bb_coords.ymax; } else { - ynew = net_bb_coords.ymin; + new_pin_loc.y = net_bb_coords.ymin; } - int layer_new; - if (net_bb_coords.layer_min == layer_old) { - layer_new = net_bb_coords.layer_max; + if (net_bb_coords.layer_min == old_pin_loc.layer_num) { + new_pin_loc.layer_num = net_bb_coords.layer_max; } else { - layer_new = net_bb_coords.layer_min; + new_pin_loc.layer_num = net_bb_coords.layer_min; } // If the moving block is on the border of the bounding box, we cannot get // the bounding box incrementally. In that case, bounding box should be calculated // from scratch. - if (!get_bb_incrementally(net_id, coords, xold, yold, layer_old, xnew, ynew, layer_new)) { + if (!get_bb_incrementally(net_id, coords, old_pin_loc, new_pin_loc)) { get_bb_from_scratch_excluding_block(net_id, coords, b_from, skip_net); if (skip_net) continue; } } - //push the calculated coorinates into X,Y coord vectors + //push the calculated coordinates into X,Y coord vectors place_move_ctx.X_coord.push_back(coords.xmin); place_move_ctx.X_coord.push_back(coords.xmax); place_move_ctx.Y_coord.push_back(coords.ymin); @@ -191,131 +177,108 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ void MedianMoveGenerator::get_bb_from_scratch_excluding_block(ClusterNetId net_id, t_bb& bb_coord_new, - ClusterBlockId block_id, + ClusterBlockId moving_block_id, bool& skip_net) { //TODO: account for multiple physical pin instances per logical pin - const auto& placer_state = placer_state_.get(); - const auto& block_locs = placer_state.block_locs(); + const auto& blk_loc_registry = placer_state_.get().blk_loc_registry(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + /* If the net is only connected to the moving block, it should be skipped. + * Let's initially assume that the net is only connected to the moving block. + * When going through the driver and sink blocks, we check if they are the same + * as the moving block. If not, we set this flag to false. */ skip_net = true; int xmin = OPEN; int xmax = OPEN; int ymin = OPEN; int ymax = OPEN; - int layer_min = OPEN; int layer_max = OPEN; - int pnum; - - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& device_ctx = g_vpr_ctx.device(); - - ClusterBlockId bnum = cluster_ctx.clb_nlist.net_driver_block(net_id); + ClusterBlockId driver_block_id = cluster_ctx.clb_nlist.net_driver_block(net_id); bool first_block = false; - if (bnum != block_id) { + if (driver_block_id != moving_block_id) { skip_net = false; - pnum = placer_state.blk_loc_registry().net_pin_to_tile_pin_index(net_id, 0); - const t_pl_loc& block_loc = block_locs[bnum].loc; - int src_x = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; - int src_y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; - int src_layer = block_loc.layer; - - xmin = src_x; - ymin = src_y; - xmax = src_x; - ymax = src_y; - layer_min = src_layer; - layer_max = src_layer; + + // get the source pin's location + ClusterPinId source_pin_id = cluster_ctx.clb_nlist.net_pin(net_id, 0); + t_physical_tile_loc source_pin_loc = blk_loc_registry.get_coordinate_of_pin(source_pin_id); + + xmin = source_pin_loc.x; + ymin = source_pin_loc.y; + xmax = source_pin_loc.x; + ymax = source_pin_loc.y; + layer_min = source_pin_loc.layer_num; + layer_max = source_pin_loc.layer_num; first_block = true; } for (ClusterPinId pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { - bnum = cluster_ctx.clb_nlist.pin_block(pin_id); - pnum = placer_state.blk_loc_registry().tile_pin_index(pin_id); - if (bnum == block_id) + ClusterBlockId sink_block_id = cluster_ctx.clb_nlist.pin_block(pin_id); + + if (sink_block_id == moving_block_id) { continue; + } + skip_net = false; - const auto& block_loc = block_locs[bnum].loc; - int x = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; - int y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; - int layer = block_loc.layer; + + t_physical_tile_loc pin_loc = blk_loc_registry.get_coordinate_of_pin(pin_id); if (!first_block) { - xmin = x; - ymin = y; - xmax = x; - ymax = y; - layer_max = layer; - layer_min = layer; + xmin = pin_loc.x; + ymin = pin_loc.y; + xmax = pin_loc.x; + ymax = pin_loc.y; + layer_max = pin_loc.layer_num; + layer_min = pin_loc.layer_num; first_block = true; continue; } - if (x < xmin) { - xmin = x; - } else if (x > xmax) { - xmax = x; + + if (pin_loc.x < xmin) { + xmin = pin_loc.x; + } else if (pin_loc.x > xmax) { + xmax = pin_loc.x; } - if (y < ymin) { - ymin = y; - } else if (y > ymax) { - ymax = y; + if (pin_loc.y < ymin) { + ymin = pin_loc.y; + } else if (pin_loc.y > ymax) { + ymax = pin_loc.y; } - if (layer < layer_min) { - layer_min = layer; - } else if (layer > layer_max) { - layer_max = layer; + if (pin_loc.layer_num < layer_min) { + layer_min = pin_loc.layer_num; + } else if (pin_loc.layer_num > layer_max) { + layer_max = pin_loc.layer_num; } } - /* Now I've found the coordinates of the bounding box. There are no * - * channels beyond device_ctx.grid.width()-2 and * - * device_ctx.grid.height() - 2, so I want to clip to that. As well,* - * since I'll always include the channel immediately below and the * - * channel immediately to the left of the bounding box, I want to * - * clip to 1 in both directions as well (since minimum channel index * - * is 0). See route_common.cpp for a channel diagram. */ - bb_coord_new.xmin = std::max(std::min(xmin, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - bb_coord_new.ymin = std::max(std::min(ymin, device_ctx.grid.height() - 2), 1); //-2 for no perim channels - bb_coord_new.layer_min = std::max(std::min(layer_min, device_ctx.grid.get_num_layers() - 1), 0); - bb_coord_new.xmax = std::max(std::min(xmax, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - bb_coord_new.ymax = std::max(std::min(ymax, device_ctx.grid.height() - 2), 1); //-2 for no perim channels - bb_coord_new.layer_max = std::max(std::min(layer_max, device_ctx.grid.get_num_layers() - 1), 0); + bb_coord_new.xmin = xmin; + bb_coord_new.ymin = ymin; + bb_coord_new.layer_min = layer_min; + bb_coord_new.xmax = xmax; + bb_coord_new.ymax = ymax; + bb_coord_new.layer_max = layer_max; } bool MedianMoveGenerator::get_bb_incrementally(ClusterNetId net_id, t_bb& bb_coord_new, - int xold, - int yold, - int layer_old, - int xnew, - int ynew, - int layer_new) { + t_physical_tile_loc old_pin_loc, + t_physical_tile_loc new_pin_loc) { //TODO: account for multiple physical pin instances per logical pin - - auto& device_ctx = g_vpr_ctx.device(); - auto& place_move_ctx = placer_state_.get().move(); - - xnew = std::max(std::min(xnew, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - ynew = std::max(std::min(ynew, device_ctx.grid.height() - 2), 1); //-2 for no perim channels - layer_new = std::max(std::min(layer_new, device_ctx.grid.get_num_layers() - 1), 0); - - xold = std::max(std::min(xold, device_ctx.grid.width() - 2), 1); //-2 for no perim channels - yold = std::max(std::min(yold, device_ctx.grid.height() - 2), 1); //-2 for no perim channels - layer_old = std::max(std::min(layer_old, device_ctx.grid.get_num_layers() - 1), 0); + const auto& place_move_ctx = placer_state_.get().move(); t_bb union_bb_edge; t_bb union_bb; const bool cube_bb = g_vpr_ctx.placement().cube_bb; - /* Calculating per-layer bounding box is more time consuming compared to cube bounding box. To speed up + /* Calculating per-layer bounding box is more time-consuming compared to cube bounding box. To speed up * this move, the bounding box used for this move is of the type cube bounding box even if the per-layer * bounding box is used by placement SA engine. - * If per-layer bounding box is used, we take a union of boundinx boxes on each layer to make a cube bounding box. - * For example, the xmax of this cube boundix box is determined by the maximim x coordinate across all blocks on all layers. + * If per-layer bounding box is used, we take a union of bounding boxes on each layer to make a cube bounding box. + * For example, the xmax of this cube bounding box is determined by the maximum x coordinate across all blocks on all layers. */ if (!cube_bb) { std::tie(union_bb_edge, union_bb) = union_2d_bb_incr(place_move_ctx.layer_bb_num_on_edges[net_id], @@ -330,11 +293,11 @@ bool MedianMoveGenerator::get_bb_incrementally(ClusterNetId net_id, /* Check if I can update the bounding box incrementally. */ - if (xnew < xold) { /* Move to left. */ + if (new_pin_loc.x < old_pin_loc.x) { /* Move to left. */ /* Update the xmax fields for coordinates and number of edges first. */ - if (xold == curr_bb_coord.xmax) { /* Old position at xmax. */ + if (old_pin_loc.x == curr_bb_coord.xmax) { /* Old position at xmax. */ if (curr_bb_edge.xmax == 1) { return false; } else { @@ -346,20 +309,20 @@ bool MedianMoveGenerator::get_bb_incrementally(ClusterNetId net_id, /* Now do the xmin fields for coordinates and number of edges. */ - if (xnew < curr_bb_coord.xmin) { /* Moved past xmin */ - bb_coord_new.xmin = xnew; - } else if (xnew == curr_bb_coord.xmin) { /* Moved to xmin */ - bb_coord_new.xmin = xnew; + if (new_pin_loc.x < curr_bb_coord.xmin) { /* Moved past xmin */ + bb_coord_new.xmin = new_pin_loc.x; + } else if (new_pin_loc.x == curr_bb_coord.xmin) { /* Moved to xmin */ + bb_coord_new.xmin = new_pin_loc.x; } else { /* Xmin unchanged. */ bb_coord_new.xmin = curr_bb_coord.xmin; } /* End of move to left case. */ - } else if (xnew > xold) { /* Move to right. */ + } else if (new_pin_loc.x > old_pin_loc.x) { /* Move to right. */ /* Update the xmin fields for coordinates and number of edges first. */ - if (xold == curr_bb_coord.xmin) { /* Old position at xmin. */ + if (old_pin_loc.x == curr_bb_coord.xmin) { /* Old position at xmin. */ if (curr_bb_edge.xmin == 1) { return false; } else { @@ -370,27 +333,27 @@ bool MedianMoveGenerator::get_bb_incrementally(ClusterNetId net_id, } /* Now do the xmax fields for coordinates and number of edges. */ - if (xnew > curr_bb_coord.xmax) { /* Moved past xmax. */ - bb_coord_new.xmax = xnew; - } else if (xnew == curr_bb_coord.xmax) { /* Moved to xmax */ - bb_coord_new.xmax = xnew; + if (new_pin_loc.x > curr_bb_coord.xmax) { /* Moved past xmax. */ + bb_coord_new.xmax = new_pin_loc.x; + } else if (new_pin_loc.x == curr_bb_coord.xmax) { /* Moved to xmax */ + bb_coord_new.xmax = new_pin_loc.x; } else { /* Xmax unchanged. */ bb_coord_new.xmax = curr_bb_coord.xmax; } /* End of move to right case. */ - } else { /* xnew == xold -- no x motion. */ + } else { /* new_pin_loc.x == old_pin_loc.x -- no x motion. */ bb_coord_new.xmin = curr_bb_coord.xmin; bb_coord_new.xmax = curr_bb_coord.xmax; } /* Now account for the y-direction motion. */ - if (ynew < yold) { /* Move down. */ + if (new_pin_loc.y < old_pin_loc.y) { /* Move down. */ /* Update the ymax fields for coordinates and number of edges first. */ - if (yold == curr_bb_coord.ymax) { /* Old position at ymax. */ + if (old_pin_loc.y == curr_bb_coord.ymax) { /* Old position at ymax. */ if (curr_bb_edge.ymax == 1) { return false; } else { @@ -402,20 +365,20 @@ bool MedianMoveGenerator::get_bb_incrementally(ClusterNetId net_id, /* Now do the ymin fields for coordinates and number of edges. */ - if (ynew < curr_bb_coord.ymin) { /* Moved past ymin */ - bb_coord_new.ymin = ynew; - } else if (ynew == curr_bb_coord.ymin) { /* Moved to ymin */ - bb_coord_new.ymin = ynew; + if (new_pin_loc.y < curr_bb_coord.ymin) { /* Moved past ymin */ + bb_coord_new.ymin = new_pin_loc.y; + } else if (new_pin_loc.y == curr_bb_coord.ymin) { /* Moved to ymin */ + bb_coord_new.ymin = new_pin_loc.y; } else { /* ymin unchanged. */ bb_coord_new.ymin = curr_bb_coord.ymin; } /* End of move down case. */ - } else if (ynew > yold) { /* Moved up. */ + } else if (new_pin_loc.y > old_pin_loc.y) { /* Moved up. */ /* Update the ymin fields for coordinates and number of edges first. */ - if (yold == curr_bb_coord.ymin) { /* Old position at ymin. */ + if (old_pin_loc.y == curr_bb_coord.ymin) { /* Old position at ymin. */ if (curr_bb_edge.ymin == 1) { return false; } else { @@ -427,22 +390,22 @@ bool MedianMoveGenerator::get_bb_incrementally(ClusterNetId net_id, /* Now do the ymax fields for coordinates and number of edges. */ - if (ynew > curr_bb_coord.ymax) { /* Moved past ymax. */ - bb_coord_new.ymax = ynew; - } else if (ynew == curr_bb_coord.ymax) { /* Moved to ymax */ - bb_coord_new.ymax = ynew; + if (new_pin_loc.y > curr_bb_coord.ymax) { /* Moved past ymax. */ + bb_coord_new.ymax = new_pin_loc.y; + } else if (new_pin_loc.y == curr_bb_coord.ymax) { /* Moved to ymax */ + bb_coord_new.ymax = new_pin_loc.y; } else { /* ymax unchanged. */ bb_coord_new.ymax = curr_bb_coord.ymax; } /* End of move up case. */ - } else { /* ynew == yold -- no y motion. */ + } else { /* new_pin_loc.y == old_pin_loc.y -- no y motion. */ bb_coord_new.ymin = curr_bb_coord.ymin; bb_coord_new.ymax = curr_bb_coord.ymax; } - if (layer_new < layer_old) { - if (layer_old == curr_bb_coord.layer_max) { + if (new_pin_loc.layer_num < old_pin_loc.layer_num) { + if (old_pin_loc.layer_num == curr_bb_coord.layer_max) { if (curr_bb_edge.layer_max == 1) { return false; } else { @@ -452,16 +415,16 @@ bool MedianMoveGenerator::get_bb_incrementally(ClusterNetId net_id, bb_coord_new.layer_max = curr_bb_coord.layer_max; } - if (layer_new < curr_bb_coord.layer_min) { - bb_coord_new.layer_min = layer_new; - } else if (layer_new == curr_bb_coord.layer_min) { - bb_coord_new.layer_min = layer_new; + if (new_pin_loc.layer_num < curr_bb_coord.layer_min) { + bb_coord_new.layer_min = new_pin_loc.layer_num; + } else if (new_pin_loc.layer_num == curr_bb_coord.layer_min) { + bb_coord_new.layer_min = new_pin_loc.layer_num; } else { bb_coord_new.layer_min = curr_bb_coord.layer_min; } - } else if (layer_new > layer_old) { - if (layer_old == curr_bb_coord.layer_min) { + } else if (new_pin_loc.layer_num > old_pin_loc.layer_num) { + if (old_pin_loc.layer_num == curr_bb_coord.layer_min) { if (curr_bb_edge.layer_min == 1) { return false; } else { @@ -471,10 +434,10 @@ bool MedianMoveGenerator::get_bb_incrementally(ClusterNetId net_id, bb_coord_new.layer_min = curr_bb_coord.layer_min; } - if (layer_new > curr_bb_coord.layer_max) { - bb_coord_new.layer_max = layer_new; - } else if (layer_new == curr_bb_coord.layer_max) { - bb_coord_new.layer_max = layer_new; + if (new_pin_loc.layer_num > curr_bb_coord.layer_max) { + bb_coord_new.layer_max = new_pin_loc.layer_num; + } else if (new_pin_loc.layer_num == curr_bb_coord.layer_max) { + bb_coord_new.layer_max = new_pin_loc.layer_num; } else { bb_coord_new.layer_max = curr_bb_coord.layer_max; } diff --git a/vpr/src/place/median_move_generator.h b/vpr/src/place/median_move_generator.h index 12c5baa2255..516fcfb573d 100644 --- a/vpr/src/place/median_move_generator.h +++ b/vpr/src/place/median_move_generator.h @@ -42,14 +42,14 @@ class MedianMoveGenerator : public MoveGenerator { * The x and y coordinates are the pin's x and y coordinates. IO blocks are considered to be * one cell in for simplicity. */ bool get_bb_incrementally(ClusterNetId net_id, t_bb& bb_coord_new, - int xold, int yold, int layer_old, - int xnew, int ynew, int layer_new); + t_physical_tile_loc old_pin_loc, + t_physical_tile_loc new_pin_loc); /** * @brief Finds the bounding box of a net and stores its coordinates in the bb_coord_new data structure. * - * @details It excludes the moving block sent in function arguments in block_id. + * @details It excludes the moving block sent in function arguments in moving_block_id. * It also returns whether this net should be excluded from median calculation or not. * This routine should only be called for small nets, since it does not determine * enough information for the bounding box to be updated incrementally later. @@ -58,7 +58,7 @@ class MedianMoveGenerator : public MoveGenerator { */ void get_bb_from_scratch_excluding_block(ClusterNetId net_id, t_bb& bb_coord_new, - ClusterBlockId block_id, + ClusterBlockId moving_block_id, bool& skip_net); }; diff --git a/vpr/src/place/move_generator.cpp b/vpr/src/place/move_generator.cpp index 7c7e252a050..0b68e3dafcc 100644 --- a/vpr/src/place/move_generator.cpp +++ b/vpr/src/place/move_generator.cpp @@ -6,8 +6,7 @@ void MoveGenerator::calculate_reward_and_process_outcome(const MoveOutcomeStats& move_outcome_stats, double delta_c, float timing_bb_factor) { - /* - * To learn about different reward functions refer to the following paper: + /* To learn about different reward functions refer to the following paper: * Elgammal MA, Murray KE, Betz V. RLPlace: Using reinforcement learning and * smart perturbations to optimize FPGA placement. * IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. @@ -87,7 +86,7 @@ void MoveTypeStat::print_placement_move_types_stats() { int rejected = rejected_moves[itype.index][imove]; int aborted = moves - (accepted + rejected); if (count == 0) { - VTR_LOG("%-18.20s", itype.name); + VTR_LOG("%-18.20s", itype.name.c_str()); } else { VTR_LOG(" "); } @@ -103,3 +102,13 @@ void MoveTypeStat::print_placement_move_types_stats() { } VTR_LOG("\n"); } + +static std::map available_reward_function = { + {"basic", e_reward_function::BASIC}, + {"nonPenalizing_basic", e_reward_function::NON_PENALIZING_BASIC}, + {"runtime_aware", e_reward_function::RUNTIME_AWARE}, + {"WLbiased_runtime_aware", e_reward_function::WL_BIASED_RUNTIME_AWARE}}; + +e_reward_function string_to_reward(const std::string& st) { + return available_reward_function[st]; +} diff --git a/vpr/src/place/move_generator.h b/vpr/src/place/move_generator.h index 885df010864..7b05a32651b 100644 --- a/vpr/src/place/move_generator.h +++ b/vpr/src/place/move_generator.h @@ -4,7 +4,6 @@ #include "vpr_types.h" #include "move_utils.h" #include "timing_place.h" -#include "directed_moves_util.h" #include @@ -41,6 +40,19 @@ struct MoveTypeStat { void print_placement_move_types_stats(); }; +/** + * @brief enum represents the different reward functions + */ +enum class e_reward_function { + BASIC, ///@ directly uses the change of the annealing cost function + NON_PENALIZING_BASIC, ///@ same as basic reward function but with 0 reward if it's a hill-climbing one + RUNTIME_AWARE, ///@ same as NON_PENALIZING_BASIC but with normalizing with the runtime factor of each move type + WL_BIASED_RUNTIME_AWARE, ///@ same as RUNTIME_AWARE but more biased to WL cost (the factor of the bias is REWARD_BB_TIMING_RELATIVE_WEIGHT) + UNDEFINED_REWARD ///@ Used for manual moves +}; + +e_reward_function string_to_reward(const std::string& st); + /** * @brief a base class for move generators * diff --git a/vpr/src/place/move_transactions.cpp b/vpr/src/place/move_transactions.cpp index a116be0d326..d51e0236cbf 100644 --- a/vpr/src/place/move_transactions.cpp +++ b/vpr/src/place/move_transactions.cpp @@ -21,7 +21,7 @@ e_block_move_result t_pl_blocks_to_be_moved::record_block_move(ClusterBlockId bl const BlkLocRegistry& blk_loc_registry) { auto [to_it, to_success] = moved_to.emplace(to); if (!to_success) { - log_move_abort("duplicate block move to location"); + move_abortion_logger.log_move_abort("duplicate block move to location"); return e_block_move_result::ABORT; } @@ -30,7 +30,7 @@ e_block_move_result t_pl_blocks_to_be_moved::record_block_move(ClusterBlockId bl auto [_, from_success] = moved_from.emplace(from); if (!from_success) { moved_to.erase(to_it); - log_move_abort("duplicate block move from location"); + move_abortion_logger.log_move_abort("duplicate block move from location"); return e_block_move_result::ABORT; } @@ -95,3 +95,23 @@ bool t_pl_blocks_to_be_moved::driven_by_moved_block(const ClusterNetId net) cons return is_driven_by_move_blk; } + +void MoveAbortionLogger::log_move_abort(std::string_view reason) { + auto it = move_abort_reasons_.find(reason); + if (it != move_abort_reasons_.end()) { + it->second++; + } else { + move_abort_reasons_.emplace(reason, 1); + } +} + +void MoveAbortionLogger::report_aborted_moves() const { + VTR_LOG("\n"); + VTR_LOG("Aborted Move Reasons:\n"); + if (move_abort_reasons_.empty()) { + VTR_LOG(" No moves aborted\n"); + } + for (const auto& kv : move_abort_reasons_) { + VTR_LOG(" %s: %zu\n", kv.first.c_str(), kv.second); + } +} diff --git a/vpr/src/place/move_transactions.h b/vpr/src/place/move_transactions.h index 68686be262e..6670a012bb0 100644 --- a/vpr/src/place/move_transactions.h +++ b/vpr/src/place/move_transactions.h @@ -30,6 +30,19 @@ struct t_pl_moved_block { t_pl_loc new_loc; }; +class MoveAbortionLogger { + public: + /// Records reasons for an aborted move. + void log_move_abort(std::string_view reason); + + /// Prints a brief report about aborted move reasons and counts. + void report_aborted_moves() const; + + private: + /// Records counts of reasons for aborted moves + std::map> move_abort_reasons_; +}; + /* Stores the list of cluster blocks to be moved in a swap during * * placement. * * Store the information on the blocks to be moved in a swap during * @@ -80,6 +93,8 @@ struct t_pl_blocks_to_be_moved { std::unordered_set moved_to; std::vector affected_pins; + + MoveAbortionLogger move_abortion_logger; }; #endif diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 050b1c0bf6d..6414f602fed 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -16,29 +16,6 @@ //Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING bool f_placer_breakpoint_reached = false; -//Records counts of reasons for aborted moves -static std::map> f_move_abort_reasons; - -void log_move_abort(std::string_view reason) { - auto it = f_move_abort_reasons.find(reason); - if (it != f_move_abort_reasons.end()) { - it->second++; - } else { - f_move_abort_reasons.emplace(reason, 1); - } -} - -void report_aborted_moves() { - VTR_LOG("\n"); - VTR_LOG("Aborted Move Reasons:\n"); - if (f_move_abort_reasons.empty()) { - VTR_LOG(" No moves aborted\n"); - } - for (const auto& kv : f_move_abort_reasons) { - VTR_LOG(" %s: %zu\n", kv.first.c_str(), kv.second); - } -} - e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, @@ -53,7 +30,7 @@ e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_to = grid_blocks.block_at_location(to); if (!b_to) { - log_move_abort("inverted move no to block"); + blocks_affected.move_abortion_logger.log_move_abort("inverted move no to block"); outcome = e_block_move_result::ABORT; } else { t_pl_loc from = block_locs[b_from].loc; @@ -61,7 +38,7 @@ e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, outcome = find_affected_blocks(blocks_affected, b_to, from, blk_loc_registry); if (outcome == e_block_move_result::INVERT) { - log_move_abort("inverted move recursion"); + blocks_affected.move_abortion_logger.log_move_abort("inverted move recursion"); outcome = e_block_move_result::ABORT; } } @@ -85,14 +62,13 @@ e_block_move_result find_affected_blocks(t_pl_blocks_to_be_moved& blocks_affecte const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); - const auto& pl_macros = g_vpr_ctx.placement().pl_macros; + const auto& place_macros = blk_loc_registry.place_macros(); - int imacro_from; e_block_move_result outcome = e_block_move_result::VALID; t_pl_loc from = block_locs[b_from].loc; - get_imacro_from_iblk(&imacro_from, b_from, pl_macros); + int imacro_from = place_macros.get_imacro_from_iblk(b_from); if (imacro_from != -1) { // b_from is part of a macro, I need to swap the whole macro @@ -102,12 +78,11 @@ e_block_move_result find_affected_blocks(t_pl_blocks_to_be_moved& blocks_affecte int imember_from = 0; outcome = record_macro_swaps(blocks_affected, imacro_from, imember_from, swap_offset, blk_loc_registry); - VTR_ASSERT_SAFE(outcome != e_block_move_result::VALID || imember_from == int(pl_macros[imacro_from].members.size())); + VTR_ASSERT_SAFE(outcome != e_block_move_result::VALID || imember_from == int(place_macros[imacro_from].members.size())); } else { ClusterBlockId b_to = grid_blocks.block_at_location(to); - int imacro_to = -1; - get_imacro_from_iblk(&imacro_to, b_to, pl_macros); + int imacro_to = place_macros.get_imacro_from_iblk(b_to); if (imacro_to != -1) { //To block is a macro but from is a single block. @@ -182,16 +157,16 @@ e_block_move_result record_macro_swaps(t_pl_blocks_to_be_moved& blocks_affected, int& imember_from, t_pl_offset swap_offset, const BlkLocRegistry& blk_loc_registry) { - const auto& pl_macros = g_vpr_ctx.placement().pl_macros; + const auto& place_macros = blk_loc_registry.place_macros(); const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); e_block_move_result outcome = e_block_move_result::VALID; - for (; imember_from < int(pl_macros[imacro_from].members.size()) && outcome == e_block_move_result::VALID; imember_from++) { + for (; imember_from < int(place_macros[imacro_from].members.size()) && outcome == e_block_move_result::VALID; imember_from++) { // Gets the new from and to info for every block in the macro // cannot use the old from and to info - ClusterBlockId curr_b_from = pl_macros[imacro_from].members[imember_from].blk_index; + ClusterBlockId curr_b_from = place_macros[imacro_from].members[imember_from].blk_index; t_pl_loc curr_from = block_locs[curr_b_from].loc; @@ -205,19 +180,18 @@ e_block_move_result record_macro_swaps(t_pl_blocks_to_be_moved& blocks_affected, //Note that we need to explicitly check that the types match, since the device floorplan is not //(necessarily) translationally invariant for an arbitrary macro if (!is_legal_swap_to_location(curr_b_from, curr_to, blk_loc_registry)) { - log_move_abort("macro_from swap to location illegal"); + blocks_affected.move_abortion_logger.log_move_abort("macro_from swap to location illegal"); outcome = e_block_move_result::ABORT; } else { ClusterBlockId b_to = grid_blocks.block_at_location(curr_to); - int imacro_to = -1; - get_imacro_from_iblk(&imacro_to, b_to, pl_macros); + int imacro_to = place_macros.get_imacro_from_iblk(b_to); if (imacro_to != -1) { //To block is a macro if (imacro_from == imacro_to) { outcome = record_macro_self_swaps(blocks_affected, imacro_from, swap_offset, blk_loc_registry); - imember_from = pl_macros[imacro_from].members.size(); + imember_from = place_macros[imacro_from].members.size(); break; //record_macro_self_swaps() handles this case completely, so we don't need to continue the loop } else { outcome = record_macro_macro_swaps(blocks_affected, imacro_from, imember_from, imacro_to, b_to, swap_offset, blk_loc_registry); @@ -252,7 +226,7 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff //The position in the from macro ('imacro_from') is specified by 'imember_from', and the relevant //macro fro the to block is 'imacro_to'. - const auto& pl_macros = g_vpr_ctx.placement().pl_macros; + const auto& pl_macros = blk_loc_registry.place_macros().macros(); const auto& block_locs = blk_loc_registry.block_locs(); //At the moment, we only support blk_to being the first element of the 'to' macro. @@ -264,7 +238,7 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff int imember_to = 0; auto outcome = record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset, blk_loc_registry); if (outcome == e_block_move_result::INVERT) { - log_move_abort("invert recursion2"); + blocks_affected.move_abortion_logger.log_move_abort("invert recursion2"); outcome = e_block_move_result::ABORT; } else if (outcome == e_block_move_result::VALID) { outcome = e_block_move_result::INVERT_VALID; @@ -296,7 +270,7 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff ++imember_from, ++imember_to) { //Check that both macros have the same shape while they overlap if (pl_macros[imacro_from].members[imember_from].offset != pl_macros[imacro_to].members[imember_to].offset + from_to_macro_offset) { - log_move_abort("macro shapes disagree"); + blocks_affected.move_abortion_logger.log_move_abort("macro shapes disagree"); return e_block_move_result::ABORT; } @@ -316,7 +290,7 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff } if (!is_legal_swap_to_location(b_from, curr_to, blk_loc_registry)) { - log_move_abort("macro_from swap to location illegal"); + blocks_affected.move_abortion_logger.log_move_abort("macro_from swap to location illegal"); return e_block_move_result::ABORT; } @@ -348,17 +322,17 @@ e_block_move_result record_macro_move(t_pl_blocks_to_be_moved& blocks_affected, const int imacro, t_pl_offset swap_offset, const BlkLocRegistry& blk_loc_registry) { - const auto& pl_macros = g_vpr_ctx.placement().pl_macros; + const auto& place_macros = blk_loc_registry.place_macros(); const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); - for (const t_pl_macro_member& member : pl_macros[imacro].members) { + for (const t_pl_macro_member& member : place_macros[imacro].members) { t_pl_loc from = block_locs[member.blk_index].loc; t_pl_loc to = from + swap_offset; if (!is_legal_swap_to_location(member.blk_index, to, blk_loc_registry)) { - log_move_abort("macro move to location illegal"); + blocks_affected.move_abortion_logger.log_move_abort("macro move to location illegal"); return e_block_move_result::ABORT; } @@ -366,8 +340,7 @@ e_block_move_result record_macro_move(t_pl_blocks_to_be_moved& blocks_affected, blocks_affected.record_block_move(member.blk_index, to, blk_loc_registry); - int imacro_to = -1; - get_imacro_from_iblk(&imacro_to, blk_to, pl_macros); + int imacro_to = place_macros.get_imacro_from_iblk(blk_to); if (blk_to && imacro_to != imacro) { //Block displaced only if exists and not part of current macro displaced_blocks.push_back(blk_to); } @@ -381,34 +354,34 @@ e_block_move_result record_macro_move(t_pl_blocks_to_be_moved& blocks_affected, e_block_move_result identify_macro_self_swap_affected_macros(std::vector& macros, const int imacro, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry) { - const auto& pl_macros = g_vpr_ctx.placement().pl_macros; + const BlkLocRegistry& blk_loc_registry, + MoveAbortionLogger& move_abortion_logger) { + const auto& place_macros = blk_loc_registry.place_macros(); const auto& block_locs = blk_loc_registry.block_locs(); const GridBlock& grid_blocks = blk_loc_registry.grid_blocks(); e_block_move_result outcome = e_block_move_result::VALID; - for (size_t imember = 0; imember < pl_macros[imacro].members.size() && outcome == e_block_move_result::VALID; ++imember) { - ClusterBlockId blk = pl_macros[imacro].members[imember].blk_index; + for (size_t imember = 0; imember < place_macros[imacro].members.size() && outcome == e_block_move_result::VALID; ++imember) { + ClusterBlockId blk = place_macros[imacro].members[imember].blk_index; t_pl_loc from = block_locs[blk].loc; t_pl_loc to = from + swap_offset; if (!is_legal_swap_to_location(blk, to, blk_loc_registry)) { - log_move_abort("macro move to location illegal"); + move_abortion_logger.log_move_abort("macro move to location illegal"); return e_block_move_result::ABORT; } ClusterBlockId blk_to = grid_blocks.block_at_location(to); - int imacro_to = -1; - get_imacro_from_iblk(&imacro_to, blk_to, pl_macros); + int imacro_to = place_macros.get_imacro_from_iblk(blk_to); if (imacro_to != -1) { auto itr = std::find(macros.begin(), macros.end(), imacro_to); if (itr == macros.end()) { macros.push_back(imacro_to); - outcome = identify_macro_self_swap_affected_macros(macros, imacro_to, swap_offset, blk_loc_registry); + outcome = identify_macro_self_swap_affected_macros(macros, imacro_to, swap_offset, blk_loc_registry, move_abortion_logger); } } } @@ -419,14 +392,14 @@ e_block_move_result record_macro_self_swaps(t_pl_blocks_to_be_moved& blocks_affe const int imacro, t_pl_offset swap_offset, const BlkLocRegistry& blk_loc_registry) { - const auto& pl_macros = g_vpr_ctx.placement().pl_macros; + const auto& place_macros = blk_loc_registry.place_macros(); //Reset any partial move blocks_affected.clear_move_blocks(); //Collect the macros affected std::vector affected_macros; - auto outcome = identify_macro_self_swap_affected_macros(affected_macros, imacro, swap_offset, blk_loc_registry); + auto outcome = identify_macro_self_swap_affected_macros(affected_macros, imacro, swap_offset, blk_loc_registry, blocks_affected.move_abortion_logger); if (outcome != e_block_move_result::VALID) { return outcome; @@ -447,8 +420,7 @@ e_block_move_result record_macro_self_swaps(t_pl_blocks_to_be_moved& blocks_affe } auto is_non_macro_block = [&](ClusterBlockId blk) { - int imacro_blk = -1; - get_imacro_from_iblk(&imacro_blk, blk, pl_macros); + int imacro_blk = place_macros.get_imacro_from_iblk(blk); if (std::find(affected_macros.begin(), affected_macros.end(), imacro_blk) != affected_macros.end()) { return false; diff --git a/vpr/src/place/move_utils.h b/vpr/src/place/move_utils.h index 1033f8ffe1f..3c12a9e36d6 100644 --- a/vpr/src/place/move_utils.h +++ b/vpr/src/place/move_utils.h @@ -106,12 +106,6 @@ struct t_swap_stats { int num_ts_called = 0; }; -//Records a reasons for an aborted move -void log_move_abort(std::string_view reason); - -//Prints a breif report about aborted move reasons and counts -void report_aborted_moves(); - e_create_move create_move(t_pl_blocks_to_be_moved& blocks_affected, ClusterBlockId b_from, t_pl_loc to, @@ -158,7 +152,8 @@ e_block_move_result record_macro_move(t_pl_blocks_to_be_moved& blocks_affected, e_block_move_result identify_macro_self_swap_affected_macros(std::vector& macros, const int imacro, t_pl_offset swap_offset, - const BlkLocRegistry& blk_loc_registry); + const BlkLocRegistry& blk_loc_registry, + MoveAbortionLogger& move_abortion_logger); e_block_move_result record_macro_self_swaps(t_pl_blocks_to_be_moved& blocks_affected, const int imacro, diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index 63fd0bf07fd..7cbfed53c53 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -85,8 +85,6 @@ static void add_block_to_bb(const t_physical_tile_loc& new_pin_loc, t_2D_bb& bb_edge_new, t_2D_bb& bb_coord_new); - - /** * @brief Given the 3D BB, calculate the wire-length estimate of the net * @param net_id ID of the net which wirelength estimate is requested @@ -102,8 +100,6 @@ static double get_net_wirelength_estimate(ClusterNetId net_id, const t_bb& bb); */ static double wirelength_crossing_count(size_t fanout); - - /******************************* End of Function definitions ************************************/ @@ -298,7 +294,7 @@ double NetCostHandler::comp_bb_cost(e_cost_methods method) { } double NetCostHandler::comp_cube_bb_cost_(e_cost_methods method) { - auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); auto& place_move_ctx = placer_state_.mutable_move(); double cost = 0; @@ -335,7 +331,7 @@ double NetCostHandler::comp_cube_bb_cost_(e_cost_methods method) { } double NetCostHandler::comp_per_layer_bb_cost_(e_cost_methods method) { - auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); auto& place_move_ctx = placer_state_.mutable_move(); double cost = 0; @@ -438,8 +434,8 @@ void NetCostHandler::update_td_delta_costs_(const PlaceDelayModel* delay_model, * This is also done to minimize the number of timing node/edge invalidations * for incremental static timing analysis (incremental STA). */ - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& block_locs = placer_state_.block_locs(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& block_locs = placer_state_.block_locs(); const auto& connection_delay = placer_state_.timing().connection_delay; auto& connection_timing_cost = placer_state_.mutable_timing().connection_timing_cost; @@ -449,8 +445,7 @@ void NetCostHandler::update_td_delta_costs_(const PlaceDelayModel* delay_model, if (cluster_ctx.clb_nlist.pin_type(pin) == PinType::DRIVER) { /* This pin is a net driver on a moved block. */ /* Recompute all point to point connection delays for the net sinks. */ - for (size_t ipin = 1; ipin < cluster_ctx.clb_nlist.net_pins(net).size(); - ipin++) { + for (size_t ipin = 1; ipin < cluster_ctx.clb_nlist.net_pins(net).size(); ipin++) { float temp_delay = comp_td_single_connection_delay(delay_model, block_locs, net, ipin); /* If the delay hasn't changed, do not mark this pin as affected */ if (temp_delay == connection_delay[net][ipin]) { @@ -461,8 +456,7 @@ void NetCostHandler::update_td_delta_costs_(const PlaceDelayModel* delay_model, proposed_connection_delay[net][ipin] = temp_delay; proposed_connection_timing_cost[net][ipin] = criticalities.criticality(net, ipin) * temp_delay; - delta_timing_cost += proposed_connection_timing_cost[net][ipin] - - connection_timing_cost[net][ipin]; + delta_timing_cost += proposed_connection_timing_cost[net][ipin] - connection_timing_cost[net][ipin]; /* Record this connection in blocks_affected.affected_pins */ ClusterPinId sink_pin = cluster_ctx.clb_nlist.net_pin(net, ipin); @@ -550,7 +544,7 @@ void NetCostHandler::get_non_updatable_cube_bb_(ClusterNetId net_id, bool use_ts //TODO: account for multiple physical pin instances per logical pin const auto& cluster_ctx = g_vpr_ctx.clustering(); const auto& device_ctx = g_vpr_ctx.device(); - const auto& block_locs = placer_state_.block_locs(); + const auto& blk_loc_registry = placer_state_.blk_loc_registry(); auto& move_ctx = placer_state_.mutable_move(); // the bounding box coordinates that is going to be updated by this function @@ -558,60 +552,52 @@ void NetCostHandler::get_non_updatable_cube_bb_(ClusterNetId net_id, bool use_ts // the number of sink pins of "net_id" on each layer vtr::NdMatrixProxy num_sink_pin_layer = use_ts ? ts_layer_sink_pin_count_[size_t(net_id)] : move_ctx.num_sink_pin_layer[size_t(net_id)]; - ClusterBlockId bnum = cluster_ctx.clb_nlist.net_driver_block(net_id); - int pnum = placer_state_.blk_loc_registry().net_pin_to_tile_pin_index(net_id, 0); + // get the source pin's location + ClusterPinId source_pin_id = cluster_ctx.clb_nlist.net_pin(net_id, 0); + t_physical_tile_loc source_pin_loc = blk_loc_registry.get_coordinate_of_pin(source_pin_id); - t_pl_loc block_loc = block_locs[bnum].loc; - int x = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; - int y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; - int layer = block_loc.layer; - - bb_coord_new.xmin = x; - bb_coord_new.ymin = y; - bb_coord_new.layer_min = layer; - bb_coord_new.xmax = x; - bb_coord_new.ymax = y; - bb_coord_new.layer_max = layer; + // initialize the bounding box coordinates with the source pin's coordinates + bb_coord_new.xmin = source_pin_loc.x; + bb_coord_new.ymin = source_pin_loc.y; + bb_coord_new.layer_min = source_pin_loc.layer_num; + bb_coord_new.xmax = source_pin_loc.x; + bb_coord_new.ymax = source_pin_loc.y; + bb_coord_new.layer_max = source_pin_loc.layer_num; for (int layer_num = 0; layer_num < device_ctx.grid.get_num_layers(); layer_num++) { num_sink_pin_layer[layer_num] = 0; } for (ClusterPinId pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { - bnum = cluster_ctx.clb_nlist.pin_block(pin_id); - block_loc = block_locs[bnum].loc; - pnum = placer_state_.blk_loc_registry().tile_pin_index(pin_id); - x = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; - y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; - layer = block_loc.layer; - - if (x < bb_coord_new.xmin) { - bb_coord_new.xmin = x; - } else if (x > bb_coord_new.xmax) { - bb_coord_new.xmax = x; + t_physical_tile_loc pin_loc = blk_loc_registry.get_coordinate_of_pin(pin_id); + + if (pin_loc.x < bb_coord_new.xmin) { + bb_coord_new.xmin = pin_loc.x; + } else if (pin_loc.x > bb_coord_new.xmax) { + bb_coord_new.xmax = pin_loc.x; } - if (y < bb_coord_new.ymin) { - bb_coord_new.ymin = y; - } else if (y > bb_coord_new.ymax) { - bb_coord_new.ymax = y; + if (pin_loc.y < bb_coord_new.ymin) { + bb_coord_new.ymin = pin_loc.y; + } else if (pin_loc.y > bb_coord_new.ymax) { + bb_coord_new.ymax = pin_loc.y; } - if (layer < bb_coord_new.layer_min) { - bb_coord_new.layer_min = layer; - } else if (layer > bb_coord_new.layer_max) { - bb_coord_new.layer_max = layer; + if (pin_loc.layer_num < bb_coord_new.layer_min) { + bb_coord_new.layer_min = pin_loc.layer_num; + } else if (pin_loc.layer_num > bb_coord_new.layer_max) { + bb_coord_new.layer_max = pin_loc.layer_num; } - num_sink_pin_layer[layer]++; + num_sink_pin_layer[pin_loc.layer_num]++; } } void NetCostHandler::get_non_updatable_per_layer_bb_(ClusterNetId net_id, bool use_ts) { //TODO: account for multiple physical pin instances per logical pin - auto& device_ctx = g_vpr_ctx.device(); - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& block_locs = placer_state_.block_locs(); + const auto& device_ctx = g_vpr_ctx.device(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& blk_loc_registry = placer_state_.blk_loc_registry(); auto& move_ctx = placer_state_.mutable_move(); std::vector& bb_coord_new = use_ts ? layer_ts_bb_coord_new_[net_id] : move_ctx.layer_bb_coords[net_id]; @@ -620,38 +606,29 @@ void NetCostHandler::get_non_updatable_per_layer_bb_(ClusterNetId net_id, bool u const int num_layers = device_ctx.grid.get_num_layers(); VTR_ASSERT_DEBUG(bb_coord_new.size() == (size_t)num_layers); - ClusterBlockId bnum = cluster_ctx.clb_nlist.net_driver_block(net_id); - t_pl_loc block_loc = block_locs[bnum].loc; - int pnum = placer_state_.blk_loc_registry().net_pin_to_tile_pin_index(net_id, 0); - - int src_x = block_locs[bnum].loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; - int src_y = block_locs[bnum].loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; + // get the source pin's location + ClusterPinId source_pin_id = cluster_ctx.clb_nlist.net_pin(net_id, 0); + t_physical_tile_loc source_pin_loc = blk_loc_registry.get_coordinate_of_pin(source_pin_id); for (int layer_num = 0; layer_num < num_layers; layer_num++) { - bb_coord_new[layer_num] = t_2D_bb{src_x, src_x, src_y, src_y, layer_num}; + bb_coord_new[layer_num] = t_2D_bb{source_pin_loc.x, source_pin_loc.x, source_pin_loc.y, source_pin_loc.y, source_pin_loc.layer_num}; num_sink_layer[layer_num] = 0; } for (ClusterPinId pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { - bnum = cluster_ctx.clb_nlist.pin_block(pin_id); - block_loc = block_locs[bnum].loc; - pnum = placer_state_.blk_loc_registry().tile_pin_index(pin_id); - int x = block_locs[bnum].loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; - int y = block_locs[bnum].loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; - - int layer_num = block_locs[bnum].loc.layer; - num_sink_layer[layer_num]++; - - if (x < bb_coord_new[layer_num].xmin) { - bb_coord_new[layer_num].xmin = x; - } else if (x > bb_coord_new[layer_num].xmax) { - bb_coord_new[layer_num].xmax = x; + t_physical_tile_loc pin_loc = blk_loc_registry.get_coordinate_of_pin(pin_id); + num_sink_layer[pin_loc.layer_num]++; + + if (pin_loc.x < bb_coord_new[pin_loc.layer_num].xmin) { + bb_coord_new[pin_loc.layer_num].xmin = pin_loc.x; + } else if (pin_loc.x > bb_coord_new[pin_loc.layer_num].xmax) { + bb_coord_new[pin_loc.layer_num].xmax = pin_loc.x; } - if (y < bb_coord_new[layer_num].ymin) { - bb_coord_new[layer_num].ymin = y; - } else if (y > bb_coord_new[layer_num].ymax) { - bb_coord_new[layer_num].ymax = y; + if (pin_loc.y < bb_coord_new[pin_loc.layer_num].ymin) { + bb_coord_new[pin_loc.layer_num].ymin = pin_loc.y; + } else if (pin_loc.y > bb_coord_new[pin_loc.layer_num].ymax) { + bb_coord_new[pin_loc.layer_num].ymax = pin_loc.y; } } } @@ -972,22 +949,22 @@ void NetCostHandler::update_layer_bb_(ClusterNetId net_id, if (layer_changed) { update_bb_layer_changed_(net_id, - pin_old_loc, - pin_new_loc, - *curr_bb_edge, - *curr_bb_coord, - bb_pin_sink_count_new, - bb_edge_new, - bb_coord_new); + pin_old_loc, + pin_new_loc, + *curr_bb_edge, + *curr_bb_coord, + bb_pin_sink_count_new, + bb_edge_new, + bb_coord_new); } else { update_bb_same_layer_(net_id, - pin_old_loc, - pin_new_loc, - *curr_bb_edge, - *curr_bb_coord, - bb_pin_sink_count_new, - bb_edge_new, - bb_coord_new); + pin_old_loc, + pin_new_loc, + *curr_bb_edge, + *curr_bb_coord, + bb_pin_sink_count_new, + bb_edge_new, + bb_coord_new); } if (bb_update_status_[net_id] == NetUpdateState::NOT_UPDATED_YET) { @@ -1270,26 +1247,21 @@ void NetCostHandler::get_bb_from_scratch_(ClusterNetId net_id, t_bb& coords, t_bb& num_on_edges, vtr::NdMatrixProxy num_sink_pin_layer) { - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& device_ctx = g_vpr_ctx.device(); - auto& grid = device_ctx.grid; - auto& block_locs = placer_state_.block_locs(); - - ClusterBlockId bnum = cluster_ctx.clb_nlist.net_driver_block(net_id); - t_pl_loc block_loc = block_locs[bnum].loc; - int pnum = placer_state_.blk_loc_registry().net_pin_to_tile_pin_index(net_id, 0); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& device_ctx = g_vpr_ctx.device(); + const auto& grid = device_ctx.grid; + const auto& blk_loc_registry = placer_state_.blk_loc_registry(); - VTR_ASSERT_SAFE(pnum >= 0); - int x = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; - int y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; - int pin_layer = block_loc.layer; + // get the source pin's location + ClusterPinId source_pin_id = cluster_ctx.clb_nlist.net_pin(net_id, 0); + t_physical_tile_loc source_pin_loc = blk_loc_registry.get_coordinate_of_pin(source_pin_id); - int xmin = x; - int ymin = y; - int layer_min = pin_layer; - int xmax = x; - int ymax = y; - int layer_max = pin_layer; + int xmin = source_pin_loc.x; + int ymin = source_pin_loc.y; + int layer_min = source_pin_loc.layer_num; + int xmax = source_pin_loc.x; + int ymax = source_pin_loc.y; + int layer_max = source_pin_loc.layer_num; int xmin_edge = 1; int ymin_edge = 1; @@ -1303,60 +1275,48 @@ void NetCostHandler::get_bb_from_scratch_(ClusterNetId net_id, } for (ClusterPinId pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { - bnum = cluster_ctx.clb_nlist.pin_block(pin_id); - block_loc = block_locs[bnum].loc; - pnum = placer_state_.blk_loc_registry().tile_pin_index(pin_id); - x = block_locs[bnum].loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; - y = block_locs[bnum].loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; - pin_layer = block_locs[bnum].loc.layer; - - /* Code below counts IO blocks as being within the 1..grid.width()-2, 1..grid.height()-2 clb array. * - * This is because channels do not go out of the 0..grid.width()-2, 0..grid.height()-2 range, and * - * I always take all channels impinging on the bounding box to be within * - * that bounding box. Hence, this "movement" of IO blocks does not affect * - * the which channels are included within the bounding box, and it * - * simplifies the code a lot. */ - - if (x == xmin) { + t_physical_tile_loc pin_loc = blk_loc_registry.get_coordinate_of_pin(pin_id); + + if (pin_loc.x == xmin) { xmin_edge++; } - if (x == xmax) { /* Recall that xmin could equal xmax -- don't use else */ + if (pin_loc.x == xmax) { /* Recall that xmin could equal xmax -- don't use else */ xmax_edge++; - } else if (x < xmin) { - xmin = x; + } else if (pin_loc.x < xmin) { + xmin = pin_loc.x; xmin_edge = 1; - } else if (x > xmax) { - xmax = x; + } else if (pin_loc.x > xmax) { + xmax = pin_loc.x; xmax_edge = 1; } - if (y == ymin) { + if (pin_loc.y == ymin) { ymin_edge++; } - if (y == ymax) { + if (pin_loc.y == ymax) { ymax_edge++; - } else if (y < ymin) { - ymin = y; + } else if (pin_loc.y < ymin) { + ymin = pin_loc.y; ymin_edge = 1; - } else if (y > ymax) { - ymax = y; + } else if (pin_loc.y > ymax) { + ymax = pin_loc.y; ymax_edge = 1; } - if (pin_layer == layer_min) { + if (pin_loc.layer_num == layer_min) { layer_min_edge++; } - if (pin_layer == layer_max) { + if (pin_loc.layer_num == layer_max) { layer_max_edge++; - } else if (pin_layer < layer_min) { - layer_min = pin_layer; + } else if (pin_loc.layer_num < layer_min) { + layer_min = pin_loc.layer_num; layer_min_edge = 1; - } else if (pin_layer > layer_max) { - layer_max = pin_layer; + } else if (pin_loc.layer_num > layer_max) { + layer_max = pin_loc.layer_num; layer_max_edge = 1; } - num_sink_pin_layer[pin_layer]++; + num_sink_pin_layer[pin_loc.layer_num]++; } // Copy the coordinates and number on edges information into the proper structures. @@ -1381,71 +1341,56 @@ void NetCostHandler::get_layer_bb_from_scratch_(ClusterNetId net_id, std::vector& num_on_edges, std::vector& coords, vtr::NdMatrixProxy layer_pin_sink_count) { - auto& device_ctx = g_vpr_ctx.device(); - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& block_locs = placer_state_.block_locs(); + const auto& device_ctx = g_vpr_ctx.device(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& blk_loc_registry = placer_state_.blk_loc_registry(); const int num_layers = device_ctx.grid.get_num_layers(); VTR_ASSERT_DEBUG(coords.size() == (size_t)num_layers); VTR_ASSERT_DEBUG(num_on_edges.size() == (size_t)num_layers); - ClusterBlockId bnum = cluster_ctx.clb_nlist.net_driver_block(net_id); - t_pl_loc block_loc = block_locs[bnum].loc; - int pnum_src = placer_state_.blk_loc_registry().net_pin_to_tile_pin_index(net_id, 0); - VTR_ASSERT_SAFE(pnum_src >= 0); - int x_src = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum_src]; - int y_src = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum_src]; + // get the source pin's location + ClusterPinId source_pin_id = cluster_ctx.clb_nlist.net_pin(net_id, 0); + t_physical_tile_loc source_pin_loc = blk_loc_registry.get_coordinate_of_pin(source_pin_id); // TODO: Currently we are assuming that crossing can only happen from OPIN. Because of that, // when per-layer bounding box is used, we want the bounding box on each layer to also include // the location of source since the connection on each layer starts from that location. for (int layer_num = 0; layer_num < num_layers; layer_num++) { - coords[layer_num] = t_2D_bb{x_src, x_src, y_src, y_src, layer_num}; + coords[layer_num] = t_2D_bb{source_pin_loc.x, source_pin_loc.x, source_pin_loc.y, source_pin_loc.y, source_pin_loc.layer_num}; num_on_edges[layer_num] = t_2D_bb{1, 1, 1, 1, layer_num}; layer_pin_sink_count[layer_num] = 0; } for (ClusterPinId pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { - bnum = cluster_ctx.clb_nlist.pin_block(pin_id); - block_loc = block_locs[bnum].loc; - int pnum = placer_state_.blk_loc_registry().tile_pin_index(pin_id); - int layer = block_locs[bnum].loc.layer; - VTR_ASSERT_SAFE(layer >= 0 && layer < num_layers); - layer_pin_sink_count[layer]++; - int x = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; - int y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; - - /* Code below counts IO blocks as being within the 1..grid.width()-2, 1..grid.height()-2 clb array. * - * This is because channels do not go out of the 0..grid.width()-2, 0..grid.height()-2 range, and * - * I always take all channels impinging on the bounding box to be within * - * that bounding box. Hence, this "movement" of IO blocks does not affect * - * the which channels are included within the bounding box, and it * - * simplifies the code a lot. */ - - if (x == coords[layer].xmin) { - num_on_edges[layer].xmin++; + t_physical_tile_loc pin_loc = blk_loc_registry.get_coordinate_of_pin(pin_id); + VTR_ASSERT_SAFE(pin_loc.layer_num >= 0 && pin_loc.layer_num < num_layers); + layer_pin_sink_count[pin_loc.layer_num]++; + + if (pin_loc.x == coords[pin_loc.layer_num].xmin) { + num_on_edges[pin_loc.layer_num].xmin++; } - if (x == coords[layer].xmax) { /* Recall that xmin could equal xmax -- don't use else */ - num_on_edges[layer].xmax++; - } else if (x < coords[layer].xmin) { - coords[layer].xmin = x; - num_on_edges[layer].xmin = 1; - } else if (x > coords[layer].xmax) { - coords[layer].xmax = x; - num_on_edges[layer].xmax = 1; + if (pin_loc.x == coords[pin_loc.layer_num].xmax) { /* Recall that xmin could equal xmax -- don't use else */ + num_on_edges[pin_loc.layer_num].xmax++; + } else if (pin_loc.x < coords[pin_loc.layer_num].xmin) { + coords[pin_loc.layer_num].xmin = pin_loc.x; + num_on_edges[pin_loc.layer_num].xmin = 1; + } else if (pin_loc.x > coords[pin_loc.layer_num].xmax) { + coords[pin_loc.layer_num].xmax = pin_loc.x; + num_on_edges[pin_loc.layer_num].xmax = 1; } - if (y == coords[layer].ymin) { - num_on_edges[layer].ymin++; + if (pin_loc.y == coords[pin_loc.layer_num].ymin) { + num_on_edges[pin_loc.layer_num].ymin++; } - if (y == coords[layer].ymax) { - num_on_edges[layer].ymax++; - } else if (y < coords[layer].ymin) { - coords[layer].ymin = y; - num_on_edges[layer].ymin = 1; - } else if (y > coords[layer].ymax) { - coords[layer].ymax = y; - num_on_edges[layer].ymax = 1; + if (pin_loc.y == coords[pin_loc.layer_num].ymax) { + num_on_edges[pin_loc.layer_num].ymax++; + } else if (pin_loc.y < coords[pin_loc.layer_num].ymin) { + coords[pin_loc.layer_num].ymin = pin_loc.y; + num_on_edges[pin_loc.layer_num].ymin = 1; + } else if (pin_loc.y > coords[pin_loc.layer_num].ymax) { + coords[pin_loc.layer_num].ymax = pin_loc.y; + num_on_edges[pin_loc.layer_num].ymax = 1; } } } diff --git a/vpr/src/place/place.cpp b/vpr/src/place/place.cpp index b61df5c603f..e41fbcbd2ba 100644 --- a/vpr/src/place/place.cpp +++ b/vpr/src/place/place.cpp @@ -183,8 +183,7 @@ static bool is_cube_bb(const e_place_bounding_box_mode place_bb_mode, static NetCostHandler alloc_and_load_placement_structs(const t_placer_opts& placer_opts, const t_noc_opts& noc_opts, - t_direct_inf* directs, - int num_directs, + const std::vector& directs, PlacerState& placer_state, std::optional& noc_cost_handler); @@ -356,16 +355,14 @@ void try_place(const Netlist<>& net_list, t_chan_width_dist chan_width_dist, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, - t_direct_inf* directs, - int num_directs, + const std::vector& directs, bool is_flat) { /* Does almost all the work of placing a circuit. Width_fac gives the * * width of the widest channel. Place_cost_exp says what exponent the * * width should be taken to when calculating costs. This allows a * * greater bias for anisotropic architectures. */ - /* - * Currently, the functions that require is_flat as their parameter and are called during placement should + /* Currently, the functions that require is_flat as their parameter and are called during placement should * receive is_flat as false. For example, if the RR graph of router lookahead is built here, it should be as * if is_flat is false, even if is_flat is set to true from the command line. */ @@ -412,7 +409,6 @@ void try_place(const Netlist<>& net_list, det_routing_arch, segment_inf, directs, - num_directs, is_flat); if (isEchoFileEnabled(E_ECHO_PLACEMENT_DELTA_DELAY_MODEL)) { @@ -441,7 +437,7 @@ void try_place(const Netlist<>& net_list, std::optional noc_cost_handler; // create cost handler objects NetCostHandler net_cost_handler = alloc_and_load_placement_structs(placer_opts, noc_opts, directs, - num_directs, placer_state, noc_cost_handler); + placer_state, noc_cost_handler); #ifndef NO_GRAPHICS if (noc_cost_handler.has_value()) { @@ -635,13 +631,13 @@ void try_place(const Netlist<>& net_list, } size_t num_macro_members = 0; - for (auto& macro : g_vpr_ctx.placement().pl_macros) { + for (auto& macro : blk_loc_registry.place_macros().macros()) { num_macro_members += macro.members.size(); } VTR_LOG( "Placement contains %zu placement macros involving %zu blocks (average macro size %f)\n", - g_vpr_ctx.placement().pl_macros.size(), num_macro_members, - float(num_macro_members) / g_vpr_ctx.placement().pl_macros.size()); + blk_loc_registry.place_macros().macros().size(), num_macro_members, + float(num_macro_members) / blk_loc_registry.place_macros().macros().size()); VTR_LOG("\n"); sprintf(msg, @@ -923,7 +919,7 @@ void try_place(const Netlist<>& net_list, //Some stats VTR_LOG("\n"); VTR_LOG("Swaps called: %d\n", swap_stats.num_ts_called); - report_aborted_moves(); + blocks_affected.move_abortion_logger.report_aborted_moves(); if (placer_opts.place_algorithm.is_timing_driven()) { //Final timing estimate @@ -1851,8 +1847,7 @@ static void invalidate_affected_connections(const t_pl_blocks_to_be_moved& block * computing costs quickly and such. */ static NetCostHandler alloc_and_load_placement_structs(const t_placer_opts& placer_opts, const t_noc_opts& noc_opts, - t_direct_inf* directs, - int num_directs, + const std::vector& directs, PlacerState& placer_state, std::optional& noc_cost_handler) { const auto& device_ctx = g_vpr_ctx.device(); @@ -1865,9 +1860,7 @@ static NetCostHandler alloc_and_load_placement_structs(const t_placer_opts& plac const int num_layers = device_ctx.grid.get_num_layers(); - auto& block_locs = placer_state.mutable_block_locs(); - auto& grid_blocks = placer_state.mutable_grid_blocks(); - init_placement_context(block_locs, grid_blocks); + init_placement_context(placer_state.mutable_blk_loc_registry(), directs); int max_pins_per_clb = 0; for (const t_physical_tile_type& type : device_ctx.physical_tile_types) { @@ -1921,8 +1914,6 @@ static NetCostHandler alloc_and_load_placement_structs(const t_placer_opts& plac elem = OPEN; } - place_ctx.pl_macros = alloc_and_load_placement_macros(directs, num_directs); - place_ctx.compressed_block_grids = create_compressed_block_grids(); if (noc_opts.noc) { @@ -1935,8 +1926,6 @@ static NetCostHandler alloc_and_load_placement_structs(const t_placer_opts& plac /* Frees the major structures needed by the placer (and not needed * * elsewhere). */ static void free_placement_structs() { - free_placement_macros_structs(); - auto& place_ctx = g_vpr_ctx.mutable_placement(); vtr::release_memory(place_ctx.compressed_block_grids); } @@ -2051,7 +2040,7 @@ static int check_block_placement_consistency(const BlkLocRegistry& blk_loc_regis if (physical_tile_type(block_loc) != physical_tile) { VTR_LOG_ERROR( "Block %zu type (%s) does not match grid location (%zu,%zu, %d) type (%s).\n", - size_t(bnum), logical_block->name, i, j, layer_num, physical_tile->name); + size_t(bnum), logical_block->name.c_str(), i, j, layer_num, physical_tile->name.c_str()); error++; } @@ -2101,7 +2090,7 @@ static int check_block_placement_consistency(const BlkLocRegistry& blk_loc_regis } int check_macro_placement_consistency(const BlkLocRegistry& blk_loc_registry) { - const auto& pl_macros = g_vpr_ctx.placement().pl_macros; + const auto& pl_macros = blk_loc_registry.place_macros().macros(); const auto& block_locs = blk_loc_registry.block_locs(); const auto& grid_blocks = blk_loc_registry.grid_blocks(); @@ -2251,8 +2240,8 @@ static void print_resources_utilization(const BlkLocRegistry& blk_loc_registry) const auto& device_ctx = g_vpr_ctx.device(); const auto& block_locs = blk_loc_registry.block_locs(); - int max_block_name = 0; - int max_tile_name = 0; + size_t max_block_name = 0; + size_t max_tile_name = 0; //Record the resource requirement std::map num_type_instances; @@ -2261,14 +2250,14 @@ static void print_resources_utilization(const BlkLocRegistry& blk_loc_registry) for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) { const t_pl_loc& loc = block_locs[blk_id].loc; - auto physical_tile = device_ctx.grid.get_physical_type({loc.x, loc.y, loc.layer}); - auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); + t_physical_tile_type_ptr physical_tile = device_ctx.grid.get_physical_type({loc.x, loc.y, loc.layer}); + t_logical_block_type_ptr logical_block = cluster_ctx.clb_nlist.block_type(blk_id); num_type_instances[logical_block]++; num_placed_instances[logical_block][physical_tile]++; - max_block_name = std::max(max_block_name, strlen(logical_block->name)); - max_tile_name = std::max(max_tile_name, strlen(physical_tile->name)); + max_block_name = std::max(max_block_name, logical_block->name.length()); + max_tile_name = std::max(max_tile_name, physical_tile->name.length()); } VTR_LOG("\n"); @@ -2276,8 +2265,8 @@ static void print_resources_utilization(const BlkLocRegistry& blk_loc_registry) for (const auto [logical_block_type_ptr, _] : num_type_instances) { for (const auto [physical_tile_type_ptr, num_instances] : num_placed_instances[logical_block_type_ptr]) { VTR_LOG(" %-*s implemented as %-*s: %d\n", max_block_name, - logical_block_type_ptr->name, max_tile_name, - physical_tile_type_ptr->name, num_instances); + logical_block_type_ptr->name.c_str(), max_tile_name, + physical_tile_type_ptr->name.c_str(), num_instances); } } VTR_LOG("\n"); diff --git a/vpr/src/place/place.h b/vpr/src/place/place.h index dba2f79ab23..138c6cdd05d 100644 --- a/vpr/src/place/place.h +++ b/vpr/src/place/place.h @@ -12,8 +12,7 @@ void try_place(const Netlist<>& net_list, t_chan_width_dist chan_width_dist, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, - t_direct_inf* directs, - int num_directs, + const std::vector& directs, bool is_flat); #endif diff --git a/vpr/src/place/place_constraints.cpp b/vpr/src/place/place_constraints.cpp index 94af4721026..f53efc0f4ef 100644 --- a/vpr/src/place/place_constraints.cpp +++ b/vpr/src/place/place_constraints.cpp @@ -157,11 +157,10 @@ void print_macro_constraint_error(const t_pl_macro& pl_macro) { VPR_ERROR(VPR_ERROR_PLACE, " \n Check that the above-mentioned placement macro blocks have compatible floorplan constraints.\n"); } -void propagate_place_constraints() { - auto& place_ctx = g_vpr_ctx.placement(); +void propagate_place_constraints(const PlaceMacros& place_macros) { auto& floorplanning_ctx = g_vpr_ctx.mutable_floorplanning(); - for (const t_pl_macro& pl_macro : place_ctx.pl_macros) { + for (const t_pl_macro& pl_macro : place_macros.macros()) { if (is_macro_constrained(pl_macro)) { /* Get the PartitionRegion for the head of the macro * based on the constraints of all blocks contained in the macro diff --git a/vpr/src/place/place_constraints.h b/vpr/src/place/place_constraints.h index 02157e907a1..78497dd20f8 100644 --- a/vpr/src/place/place_constraints.h +++ b/vpr/src/place/place_constraints.h @@ -93,7 +93,7 @@ PartitionRegion update_macro_member_pr(const PartitionRegion& head_pr, * initial placement to ease floorplan legality checking while placing macros during * initial placement. */ -void propagate_place_constraints(); +void propagate_place_constraints(const PlaceMacros& place_macros); void print_macro_constraint_error(const t_pl_macro& pl_macro); diff --git a/vpr/src/place/place_delay_model.cpp b/vpr/src/place/place_delay_model.cpp index aa6896a62fe..4f626a5817f 100644 --- a/vpr/src/place/place_delay_model.cpp +++ b/vpr/src/place/place_delay_model.cpp @@ -120,8 +120,8 @@ void OverrideDelayModel::dump_echo(std::string filepath) const { auto override_key = kv.first; float delay_val = kv.second; fprintf(f, "from_type: %s to_type: %s from_pin_class: %d to_pin_class: %d delta_x: %d delta_y: %d -> delay: %g\n", - device_ctx.physical_tile_types[override_key.from_type].name, - device_ctx.physical_tile_types[override_key.to_type].name, + device_ctx.physical_tile_types[override_key.from_type].name.c_str(), + device_ctx.physical_tile_types[override_key.to_type].name.c_str(), override_key.from_class, override_key.to_class, override_key.delta_x, @@ -324,8 +324,7 @@ std::unique_ptr alloc_lookups_and_delay_model(const Netlist<>& const t_router_opts& router_opts, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, bool is_flat) { return compute_place_delay_model(placer_opts, router_opts, @@ -334,7 +333,6 @@ std::unique_ptr alloc_lookups_and_delay_model(const Netlist<>& segment_inf, chan_width_dist, directs, - num_directs, is_flat); } diff --git a/vpr/src/place/place_delay_model.h b/vpr/src/place/place_delay_model.h index 05fba845f0a..0aa01385e6e 100644 --- a/vpr/src/place/place_delay_model.h +++ b/vpr/src/place/place_delay_model.h @@ -35,8 +35,7 @@ std::unique_ptr alloc_lookups_and_delay_model(const Netlist<>& const t_router_opts& router_opts, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, bool is_flat); ///@brief Returns the delay of one point to point connection. diff --git a/vpr/src/place/place_macro.cpp b/vpr/src/place/place_macro.cpp index 78c1a186d20..3568405290c 100644 --- a/vpr/src/place/place_macro.cpp +++ b/vpr/src/place/place_macro.cpp @@ -1,89 +1,186 @@ + +#include "place_macro.h" + #include #include #include #include +#include #include "vtr_assert.h" -#include "vtr_memory.h" #include "vtr_util.h" - +#include "vpr_utils.h" #include "vpr_types.h" #include "vpr_error.h" #include "physical_types.h" #include "globals.h" -#include "place_macro.h" -#include "vpr_utils.h" #include "echo_files.h" -/******************** File-scope variables declarations **********************/ +/** + * @brief Determines whether a cluster net is constant. + * @param clb_net The unique id of a cluster net. + * @return True if the net is constant; otherwise false. + */ +static bool is_constant_clb_net(ClusterNetId clb_net); -/* f_idirect_from_blk_pin array allow us to quickly find pins that could be in a * - * direct connection. Values stored is the index of the possible direct connection * - * as specified in the arch file, OPEN (-1) is stored for pins that could not be * - * part of a direct chain conneciton. * - * [0...device_ctx.num_block_types-1][0...num_pins-1] */ -static int** f_idirect_from_blk_pin = nullptr; +/** + * @brief Performs a sanity check on macros by making sure that + * each block appears in at most one macro. + * @param macros All placement macros in the netlist. + */ +static void validate_macros(const std::vector& macros); -/* f_direct_type_from_blk_pin array stores the value SOURCE if the pin is the * - * from_pin, SINK if the pin is the to_pin in the direct connection as specified in * - * the arch file, OPEN (-1) is stored for pins that could not be part of a direct * - * chain conneciton. * - * [0...device_ctx.num_block_types-1][0...num_pins-1] */ -static int** f_direct_type_from_blk_pin = nullptr; +/** + * @brief Tries to combine two placement macros. + * @details This function takes two placement macro ids which have a common cluster block + * or more in between. The function then tries to find if the two macros could be combined + * to form a larger macro. If it's impossible to combine the two macros together then + * this design will never place and route. + * + * @param pl_macro_member_blk_num [0..num_macros-1][0..num_cluster_blocks-1] + * 2D array of macros created so far. + * @param matching_macro first macro id, which is a previous macro that is found to have the same block + * @param latest_macro second macro id, which is the macro being created at this iteration + * @return True if combining two macros was successful; otherwise false. + */ +static bool try_combine_macros(std::vector>& pl_macro_member_blk_num, + int matching_macro, + int latest_macro); + +/* Go through all the ports in all the blocks to find the port that has the same * + * name as port_name and belongs to the block type that has the name pb_type_name. * + * Then, check that whether start_pin_index and end_pin_index are specified. If * + * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * + * Otherwise, mark down all the pins in that port. */ +static void mark_direct_of_ports(int idirect, + int direct_type, + std::string_view pb_type_name, + std::string_view port_name, + int end_pin_index, + int start_pin_index, + std::string_view src_string, + int line, + std::vector>& idirect_from_blk_pin, + std::vector>& direct_type_from_blk_pin, + const PortPinToBlockPinConverter& port_pin_to_block_pin); + +/** + * @brief Mark the pin entry in idirect_from_blk_pin with idirect and the pin entry in + * direct_type_from_blk_pin with direct_type from start_pin_index to end_pin_index. + */ +static void mark_direct_of_pins(int start_pin_index, + int end_pin_index, + int itype, + int isub_tile, + int iport, + std::vector>& idirect_from_blk_pin, + int idirect, + std::vector>& direct_type_from_blk_pin, + int direct_type, + int line, + std::string_view src_string, + const PortPinToBlockPinConverter& port_pin_to_block_pin); + +const std::vector& PlaceMacros::macros() const { + return pl_macros_; +} -/* f_imacro_from_blk_pin maps a blk_num to the corresponding macro index. * - * If the block is not part of a macro, the value OPEN (-1) is stored. * - * [0...cluster_ctx.clb_nlist.blocks().size()-1] */ -static vtr::vector_map f_imacro_from_iblk; +void PlaceMacros::alloc_and_load_placement_macros(const std::vector& directs) { + /* Allocates allocates and loads placement macros and returns + * the total number of macros in 2 steps. + * 1) Allocate temporary data structure for maximum possible + * size and loops through all the blocks storing the data + * relevant to the carry chains. At the same time, also count + * the amount of memory required for the actual variables. + * 2) Allocate the actual variables with the exact amount of + * memory. Then loads the data from the temporary data + * structures before freeing them. + */ + const auto& cluster_ctx = g_vpr_ctx.clustering(); + + // Allocate maximum memory for temporary variables. + std::vector pl_macro_idirect(cluster_ctx.clb_nlist.blocks().size()); + std::vector pl_macro_num_members(cluster_ctx.clb_nlist.blocks().size()); + /* For pl_macro_member_blk_num, Allocate for the first dimension only at first. Allocate for the second dimension + * when I know the size. Otherwise, the array is going to be of size cluster_ctx.clb_nlist.blocks().size()^2 */ + std::vector> pl_macro_member_blk_num(cluster_ctx.clb_nlist.blocks().size()); -/******************** Subroutine declarations ********************************/ + alloc_and_load_idirect_from_blk_pin_(directs); -static void find_all_the_macro(int* num_of_macro, std::vector& pl_macro_member_blk_num_of_this_blk, std::vector& pl_macro_idirect, std::vector& pl_macro_num_members, std::vector>& pl_macro_member_blk_num); + /* Compute required size: + * Go through all the pins with possible direct connections in + * idirect_from_blk_pin_. Count the number of heads (which is the same + * as the number macros) and also the length of each macro + * Head - blocks with to_pin OPEN and from_pin connected + * Tail - blocks with to_pin connected and from_pin OPEN + */ + const int num_macro = find_all_the_macro_(pl_macro_idirect, pl_macro_num_members, pl_macro_member_blk_num); -static void alloc_and_load_imacro_from_iblk(const std::vector& macros); + // Allocate the memories for the macro. + pl_macros_.resize(num_macro); -static void write_place_macros(std::string filename, const std::vector& macros); + /* Allocate the memories for the chain members. + * Load the values from the temporary data structures. + */ + for (int imacro = 0; imacro < num_macro; imacro++) { + pl_macros_[imacro].members = std::vector(pl_macro_num_members[imacro]); + + // Load the values for each member of the macro + for (size_t imember = 0; imember < pl_macros_[imacro].members.size(); imember++) { + pl_macros_[imacro].members[imember].offset.x = imember * directs[pl_macro_idirect[imacro]].x_offset; + pl_macros_[imacro].members[imember].offset.y = imember * directs[pl_macro_idirect[imacro]].y_offset; + pl_macros_[imacro].members[imember].offset.sub_tile = directs[pl_macro_idirect[imacro]].sub_tile_offset; + pl_macros_[imacro].members[imember].blk_index = pl_macro_member_blk_num[imacro][imember]; + } + } -static bool is_constant_clb_net(ClusterNetId clb_net); + if (isEchoFileEnabled(E_ECHO_PLACE_MACROS)) { + write_place_macros_(getEchoFileName(E_ECHO_PLACE_MACROS), pl_macros_); + } -static bool net_is_driven_by_direct(ClusterNetId clb_net); + validate_macros(pl_macros_); -static void validate_macros(const std::vector& macros); + alloc_and_load_imacro_from_iblk_(pl_macros_); +} -static bool try_combine_macros(std::vector>& pl_macro_member_blk_num, int matching_macro, int latest_macro); -/******************** Subroutine definitions *********************************/ +ClusterBlockId PlaceMacros::macro_head(ClusterBlockId blk) const { + int macro_index = get_imacro_from_iblk(blk); + if (macro_index == OPEN) { + return ClusterBlockId::INVALID(); + } else { + return pl_macros_[macro_index].members[0].blk_index; + } +} -static void find_all_the_macro(int* num_of_macro, std::vector& pl_macro_member_blk_num_of_this_blk, std::vector& pl_macro_idirect, std::vector& pl_macro_num_members, std::vector>& pl_macro_member_blk_num) { +int PlaceMacros::find_all_the_macro_(std::vector& pl_macro_idirect, + std::vector& pl_macro_num_members, + std::vector>& pl_macro_member_blk_num) { /* Compute required size: * * Go through all the pins with possible direct connections in * - * f_idirect_from_blk_pin. Count the number of heads (which is the same * + * idirect_from_blk_pin_. Count the number of heads (which is the same * * as the number macros) and also the length of each macro * * Head - blocks with to_pin OPEN and from_pin connected * * Tail - blocks with to_pin connected and from_pin OPEN */ - - int from_iblk_pin, to_iblk_pin, from_idirect, to_idirect, - from_src_or_sink, to_src_or_sink; - ClusterNetId to_net_id, from_net_id, next_net_id, curr_net_id; - ClusterBlockId next_blk_id; - int num_blk_pins, num_macro; - int imember; - auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); + std::vector pl_macro_member_blk_num_of_this_blk(cluster_ctx.clb_nlist.blocks().size()); // Hash table holding the unique cluster ids and the macro id it belongs to std::unordered_map clusters_macro; - num_macro = 0; - for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { - auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); - auto physical_tile = pick_physical_type(logical_block); + // counts the total number of macros + int num_macro = 0; + + for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) { + t_logical_block_type_ptr logical_block = cluster_ctx.clb_nlist.block_type(blk_id); + t_physical_tile_type_ptr physical_tile = pick_physical_type(logical_block); - num_blk_pins = cluster_ctx.clb_nlist.block_type(blk_id)->pb_type->num_pins; - for (to_iblk_pin = 0; to_iblk_pin < num_blk_pins; to_iblk_pin++) { + int num_blk_pins = cluster_ctx.clb_nlist.block_type(blk_id)->pb_type->num_pins; + for (int to_iblk_pin = 0; to_iblk_pin < num_blk_pins; to_iblk_pin++) { int to_physical_pin = get_physical_pin(physical_tile, logical_block, to_iblk_pin); - to_net_id = cluster_ctx.clb_nlist.block_net(blk_id, to_iblk_pin); - to_idirect = f_idirect_from_blk_pin[physical_tile->index][to_physical_pin]; - to_src_or_sink = f_direct_type_from_blk_pin[physical_tile->index][to_physical_pin]; + ClusterNetId to_net_id = cluster_ctx.clb_nlist.block_net(blk_id, to_iblk_pin); + int to_idirect = idirect_from_blk_pin_[physical_tile->index][to_physical_pin]; + int to_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][to_physical_pin]; // Identify potential macro head blocks (i.e. start of a macro) // @@ -94,16 +191,14 @@ static void find_all_the_macro(int* num_of_macro, std::vector& p // Note that the restriction that constant nets are not driven from another direct ensures that // blocks in the middle of a chain with internal constant signals are not detected as potential // head blocks. - if (to_src_or_sink == SINK && to_idirect != OPEN - && (to_net_id == ClusterNetId::INVALID() - || (is_constant_clb_net(to_net_id) - && !net_is_driven_by_direct(to_net_id)))) { - for (from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { + if (to_src_or_sink == SINK && to_idirect != OPEN && + (to_net_id == ClusterNetId::INVALID() || (is_constant_clb_net(to_net_id) && !net_is_driven_by_direct_(to_net_id)))) { + for (int from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { int from_physical_pin = get_physical_pin(physical_tile, logical_block, from_iblk_pin); - from_net_id = cluster_ctx.clb_nlist.block_net(blk_id, from_iblk_pin); - from_idirect = f_idirect_from_blk_pin[physical_tile->index][from_physical_pin]; - from_src_or_sink = f_direct_type_from_blk_pin[physical_tile->index][from_physical_pin]; + ClusterNetId from_net_id = cluster_ctx.clb_nlist.block_net(blk_id, from_iblk_pin); + int from_idirect = idirect_from_blk_pin_[physical_tile->index][from_physical_pin]; + int from_src_or_sink = direct_type_from_blk_pin_[physical_tile->index][from_physical_pin]; // Confirm whether this is a head macro // @@ -121,24 +216,24 @@ static void find_all_the_macro(int* num_of_macro, std::vector& p // there are at least 2 members - 1 head and 1 tail. // Initialize the variables - next_net_id = from_net_id; - next_blk_id = blk_id; + ClusterNetId next_net_id = from_net_id; + ClusterBlockId next_blk_id = blk_id; // Start finding the other members while (next_net_id != ClusterNetId::INVALID()) { - curr_net_id = next_net_id; + ClusterNetId curr_net_id = next_net_id; // Assume that carry chains only has 1 sink - direct connection VTR_ASSERT(cluster_ctx.clb_nlist.net_sinks(curr_net_id).size() == 1); next_blk_id = cluster_ctx.clb_nlist.net_pin_block(curr_net_id, 1); // Assume that the from_iblk_pin index is the same for the next block - VTR_ASSERT(f_idirect_from_blk_pin[physical_tile->index][from_physical_pin] == from_idirect - && f_direct_type_from_blk_pin[physical_tile->index][from_physical_pin] == SOURCE); + VTR_ASSERT(idirect_from_blk_pin_[physical_tile->index][from_physical_pin] == from_idirect + && direct_type_from_blk_pin_[physical_tile->index][from_physical_pin] == SOURCE); next_net_id = cluster_ctx.clb_nlist.block_net(next_blk_id, from_iblk_pin); // Mark down this block as a member of the macro - imember = pl_macro_num_members[num_macro]; + int imember = pl_macro_num_members[num_macro]; pl_macro_member_blk_num_of_this_blk[imember] = next_blk_id; // Increment the num_member count. @@ -150,7 +245,7 @@ static void find_all_the_macro(int* num_of_macro, std::vector& p pl_macro_member_blk_num[num_macro].resize(pl_macro_num_members[num_macro]); int matching_macro = -1; // Copy the data from the temporary array to the newly allocated array. - for (imember = 0; imember < pl_macro_num_members[num_macro]; imember++) { + for (int imember = 0; imember < pl_macro_num_members[num_macro]; imember++) { auto cluster_id = pl_macro_member_blk_num_of_this_blk[imember]; pl_macro_member_blk_num[num_macro][imember] = cluster_id; // check if this cluster block was in a previous macro @@ -185,20 +280,12 @@ static void find_all_the_macro(int* num_of_macro, std::vector& p } // Finish going through all blocks. // Now, all the data is readily stored in the temporary data structures. - *num_of_macro = num_macro; + return num_macro; } -static bool try_combine_macros(std::vector>& pl_macro_member_blk_num, int matching_macro, int latest_macro) { - /* This function takes two placement macro ids which have a common cluster block - * or more in between. The function then tries to find if the two macros could - * be combined together to form a larger macro. If it's impossible to combine - * the two macros together then this design will never place and route. - * Arguments: - * pl_macro_member_blk_num : [0..num_macros-1][0..num_cluster_blocks-1] 2D array - * of macros created so far. - * matching_macro : first macro id, which is a previous macro that is found to have the same block - * latest_macro : second macro id, which is the macro being created at this iteration */ - +static bool try_combine_macros(std::vector>& pl_macro_member_blk_num, + int matching_macro, + int latest_macro) { auto& old_macro_blocks = pl_macro_member_blk_num[matching_macro]; auto& new_macro_blocks = pl_macro_member_blk_num[latest_macro]; @@ -296,147 +383,197 @@ static bool try_combine_macros(std::vector>& pl_macr return true; } -std::vector alloc_and_load_placement_macros(t_direct_inf* directs, int num_directs) { - /* This function allocates and loads the macros placement macros * - * and returns the total number of macros in 2 steps. * - * 1) Allocate temporary data structure for maximum possible * - * size and loops through all the blocks storing the data * - * relevant to the carry chains. At the same time, also count * - * the amount of memory required for the actual variables. * - * 2) Allocate the actual variables with the exact amount of * - * memory. Then loads the data from the temporary data * - * structures before freeing them. * - * * - * For pl_macro_member_blk_num, allocate for the first dimension * - * only at first. Allocate for the second dimension when I know * - * the size. Otherwise, the array is going to be of size * - * cluster_ctx.clb_nlist.blocks().size()^2 (There are big * - * benckmarks VPR that have cluster_ctx.clb_nlist.blocks().size() * - * in the 100k's range). * - * * - * The placement macro array is freed by the caller(s). */ - - /* Declaration of local variables */ - int num_macro; - auto& cluster_ctx = g_vpr_ctx.clustering(); - - /* Allocate maximum memory for temporary variables. */ - std::vector pl_macro_idirect(cluster_ctx.clb_nlist.blocks().size()); - std::vector pl_macro_num_members(cluster_ctx.clb_nlist.blocks().size()); - std::vector> pl_macro_member_blk_num(cluster_ctx.clb_nlist.blocks().size()); - std::vector pl_macro_member_blk_num_of_this_blk(cluster_ctx.clb_nlist.blocks().size()); - - /* Sets up the required variables. */ - alloc_and_load_idirect_from_blk_pin(directs, num_directs, - &f_idirect_from_blk_pin, &f_direct_type_from_blk_pin); - - /* Compute required size: * - * Go through all the pins with possible direct connections in * - * f_idirect_from_blk_pin. Count the number of heads (which is the same * - * as the number macros) and also the length of each macro * - * Head - blocks with to_pin OPEN and from_pin connected * - * Tail - blocks with to_pin connected and from_pin OPEN */ - num_macro = 0; - find_all_the_macro(&num_macro, pl_macro_member_blk_num_of_this_blk, - pl_macro_idirect, pl_macro_num_members, pl_macro_member_blk_num); +int PlaceMacros::get_imacro_from_iblk(ClusterBlockId iblk) const { + int imacro; + if (iblk != ClusterBlockId::INVALID()) { + // Return the imacro for the block. + imacro = imacro_from_iblk_[iblk]; + } else { + imacro = OPEN; //No valid block, so no valid macro + } - /* Allocate the memories for the macro. */ - std::vector macros(num_macro); + return imacro; +} - /* Allocate the memories for the chain members. * - * Load the values from the temporary data structures. */ - for (int imacro = 0; imacro < num_macro; imacro++) { - macros[imacro].members = std::vector(pl_macro_num_members[imacro]); +void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector& directs) { + const auto& device_ctx = g_vpr_ctx.device(); - /* Load the values for each member of the macro */ - for (size_t imember = 0; imember < macros[imacro].members.size(); imember++) { - macros[imacro].members[imember].offset.x = imember * directs[pl_macro_idirect[imacro]].x_offset; - macros[imacro].members[imember].offset.y = imember * directs[pl_macro_idirect[imacro]].y_offset; - macros[imacro].members[imember].offset.sub_tile = directs[pl_macro_idirect[imacro]].sub_tile_offset; - macros[imacro].members[imember].blk_index = pl_macro_member_blk_num[imacro][imember]; + // Allocate and initialize the values to OPEN (-1). + idirect_from_blk_pin_.resize(device_ctx.physical_tile_types.size()); + direct_type_from_blk_pin_.resize(device_ctx.physical_tile_types.size()); + for (const t_physical_tile_type& type : device_ctx.physical_tile_types) { + if (is_empty_type(&type)) { + continue; } - } - if (isEchoFileEnabled(E_ECHO_PLACE_MACROS)) { - write_place_macros(getEchoFileName(E_ECHO_PLACE_MACROS), macros); + idirect_from_blk_pin_[type.index].resize(type.num_pins, OPEN); + direct_type_from_blk_pin_[type.index].resize(type.num_pins, OPEN); } - validate_macros(macros); + const PortPinToBlockPinConverter port_pin_to_block_pin; - return macros; + /* Load the values */ + // Go through directs and find pins with possible direct connections + for (size_t idirect = 0; idirect < directs.size(); idirect++) { + // Parse out the pb_type and port name, possibly pin_indices from from_pin + auto [from_end_pin_index, from_start_pin_index, from_pb_type_name, from_port_name] = parse_direct_pin_name(directs[idirect].from_pin, + directs[idirect].line); + + // Parse out the pb_type and port name, possibly pin_indices from to_pin + auto [to_end_pin_index, to_start_pin_index, to_pb_type_name, to_port_name] = parse_direct_pin_name(directs[idirect].to_pin, + directs[idirect].line); + + /* Now I have all the data that I need, I could go through all the block pins + * in all the blocks to find all the pins that could have possible direct + * connections. Mark all down all those pins with the idirect the pins belong + * to and whether it is a source or a sink of the direct connection. */ + + // Find blocks with the same name as from_pb_type_name and from_port_name + mark_direct_of_ports(idirect, SOURCE, from_pb_type_name, from_port_name, + from_end_pin_index, from_start_pin_index, directs[idirect].from_pin, + directs[idirect].line, + idirect_from_blk_pin_, direct_type_from_blk_pin_, + port_pin_to_block_pin); + + // Then, find blocks with the same name as to_pb_type_name and from_port_name + mark_direct_of_ports(idirect, SINK, to_pb_type_name, to_port_name, + to_end_pin_index, to_start_pin_index, directs[idirect].to_pin, + directs[idirect].line, + idirect_from_blk_pin_, direct_type_from_blk_pin_, + port_pin_to_block_pin); + + } // Finish going through all the directs } -void get_imacro_from_iblk(int* imacro, ClusterBlockId iblk, const std::vector& macros) { - /* This mapping is needed for fast lookup's whether the block with index * - * iblk belongs to a placement macro or not. * - * * - * The array f_imacro_from_iblk is used for the mapping for speed reason * - * [0...cluster_ctx.clb_nlist.blocks().size()-1] */ +static void mark_direct_of_ports(int idirect, + int direct_type, + std::string_view pb_type_name, + std::string_view port_name, + int end_pin_index, + int start_pin_index, + std::string_view src_string, + int line, + std::vector>& idirect_from_blk_pin, + std::vector>& direct_type_from_blk_pin, + const PortPinToBlockPinConverter& port_pin_to_block_pin) { + /* Go through all the ports in all the blocks to find the port that has the same * + * name as port_name and belongs to the block type that has the name pb_type_name. * + * Then, check that whether start_pin_index and end_pin_index are specified. If * + * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * + * Otherwise, mark down all the pins in that port. */ - /* If the array is not allocated and loaded, allocate it. */ - if (f_imacro_from_iblk.size() == 0) { - alloc_and_load_imacro_from_iblk(macros); - } + auto& device_ctx = g_vpr_ctx.device(); - if (iblk) { - /* Return the imacro for the block. */ - *imacro = f_imacro_from_iblk[iblk]; - } else { - *imacro = OPEN; //No valid block, so no valid macro - } + // Go through all the block types + for (int itype = 1; itype < (int)device_ctx.physical_tile_types.size(); itype++) { + auto& physical_tile = device_ctx.physical_tile_types[itype]; + // Find blocks with the same pb_type_name + if (pb_type_name == physical_tile.name) { + int num_sub_tiles = physical_tile.sub_tiles.size(); + for (int isub_tile = 0; isub_tile < num_sub_tiles; isub_tile++) { + auto& ports = physical_tile.sub_tiles[isub_tile].ports; + int num_ports = ports.size(); + for (int iport = 0; iport < num_ports; iport++) { + // Find ports with the same port_name + if (port_name == ports[iport].name) { + int num_port_pins = ports[iport].num_pins; + + // Check whether the end_pin_index is valid + if (end_pin_index > num_port_pins) { + VTR_LOG_ERROR( + "[LINE %d] Invalid pin - %s, the end_pin_index in " + "[end_pin_index:start_pin_index] should " + "be less than the num_port_pins %d.\n", + line, src_string, num_port_pins); + exit(1); + } + + // Check whether the pin indices are specified + if (start_pin_index >= 0 || end_pin_index >= 0) { + mark_direct_of_pins(start_pin_index, end_pin_index, itype, + isub_tile, iport, idirect_from_blk_pin, idirect, + direct_type_from_blk_pin, direct_type, line, src_string, + port_pin_to_block_pin); + } else { + mark_direct_of_pins(0, num_port_pins - 1, itype, + isub_tile, iport, idirect_from_blk_pin, idirect, + direct_type_from_blk_pin, direct_type, line, src_string, + port_pin_to_block_pin); + } + } // Do nothing if port_name does not match + } // Finish going through all the ports + } // Finish going through all the subtiles + } // Do nothing if pb_type_name does not match + } // Finish going through all the blocks } -void set_imacro_for_iblk(int* imacro, ClusterBlockId blk_id) { - auto& cluster_ctx = g_vpr_ctx.clustering(); +static void mark_direct_of_pins(int start_pin_index, + int end_pin_index, + int itype, + int isub_tile, + int iport, + std::vector>& idirect_from_blk_pin, + int idirect, + std::vector>& direct_type_from_blk_pin, + int direct_type, + int line, + std::string_view src_string, + const PortPinToBlockPinConverter& port_pin_to_block_pin) { + const auto& device_ctx = g_vpr_ctx.device(); + + // Mark pins with indices from start_pin_index to end_pin_index, inclusive + for (int iport_pin = start_pin_index; iport_pin <= end_pin_index; iport_pin++) { + int iblk_pin = port_pin_to_block_pin.get_blk_pin_from_port_pin(itype, isub_tile, iport, iport_pin); + + // iterate through all segment connections and check if all Fc's are 0 + bool all_fcs_0 = true; + for (const auto& fc_spec : device_ctx.physical_tile_types[itype].fc_specs) { + for (int ipin : fc_spec.pins) { + if (iblk_pin == ipin && fc_spec.fc_value > 0) { + all_fcs_0 = false; + break; + } + } + if (!all_fcs_0) break; + } + + // Check the fc for the pin, direct chain link only if fc == 0 + if (all_fcs_0) { + idirect_from_blk_pin[itype][iblk_pin] = idirect; - f_imacro_from_iblk.resize(cluster_ctx.clb_nlist.blocks().size()); - f_imacro_from_iblk.insert(blk_id, *imacro); + // Check whether the pins are marked, errors out if so + if (direct_type_from_blk_pin[itype][iblk_pin] != OPEN) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "[LINE %d] Invalid pin - %s, this pin is in more than one direct connection.\n", + line, src_string); + } else { + direct_type_from_blk_pin[itype][iblk_pin] = direct_type; + } + } + } // Finish marking all the pins } /* Allocates and loads imacro_from_iblk array. */ -static void alloc_and_load_imacro_from_iblk(const std::vector& macros) { +void PlaceMacros::alloc_and_load_imacro_from_iblk_(const std::vector& macros) { auto& cluster_ctx = g_vpr_ctx.clustering(); - f_imacro_from_iblk.resize(cluster_ctx.clb_nlist.blocks().size()); + imacro_from_iblk_.resize(cluster_ctx.clb_nlist.blocks().size()); /* Allocate and initialize the values to OPEN (-1). */ for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { - f_imacro_from_iblk.insert(blk_id, OPEN); + imacro_from_iblk_.insert(blk_id, OPEN); } /* Load the values */ for (size_t imacro = 0; imacro < macros.size(); imacro++) { for (size_t imember = 0; imember < macros[imacro].members.size(); imember++) { ClusterBlockId blk_id = macros[imacro].members[imember].blk_index; - f_imacro_from_iblk.insert(blk_id, imacro); + imacro_from_iblk_.insert(blk_id, imacro); } } } -void free_placement_macros_structs() { - /* This function frees up all the static data structures used. */ - - // This frees up the two arrays and set the pointers to NULL - auto& device_ctx = g_vpr_ctx.device(); - unsigned int itype; - if (f_idirect_from_blk_pin != nullptr) { - for (itype = 1; itype < device_ctx.physical_tile_types.size(); itype++) { - delete[] f_idirect_from_blk_pin[itype]; - } - delete[] f_idirect_from_blk_pin; - f_idirect_from_blk_pin = nullptr; - } - - if (f_direct_type_from_blk_pin != nullptr) { - for (itype = 1; itype < device_ctx.physical_tile_types.size(); itype++) { - delete[] f_direct_type_from_blk_pin[itype]; - } - delete[] f_direct_type_from_blk_pin; - f_direct_type_from_blk_pin = nullptr; - } -} - -static void write_place_macros(std::string filename, const std::vector& macros) { +void PlaceMacros::write_place_macros_(std::string filename, const std::vector& macros) { FILE* f = vtr::fopen(filename.c_str(), "w"); auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -472,15 +609,15 @@ static void write_place_macros(std::string filename, const std::vectorindex][physical_pin]; + auto direct = idirect_from_blk_pin_[physical_tile->index][physical_pin]; return direct != OPEN; } +const t_pl_macro& PlaceMacros::operator[](int idx) const { + return pl_macros_[idx]; +} + + + static void validate_macros(const std::vector& macros) { //Perform sanity checks on macros - auto& cluster_ctx = g_vpr_ctx.clustering(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); //Verify that blocks only appear in a single macro std::multimap block_to_macro; @@ -524,7 +667,7 @@ static void validate_macros(const std::vector& macros) { } } - for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { + for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) { auto range = block_to_macro.equal_range(blk_id); int blk_macro_cnt = std::distance(range.first, range.second); @@ -542,3 +685,4 @@ static void validate_macros(const std::vector& macros) { } } } + diff --git a/vpr/src/place/place_macro.h b/vpr/src/place/place_macro.h index 71c6a720773..ed6a2fc82c5 100644 --- a/vpr/src/place/place_macro.h +++ b/vpr/src/place/place_macro.h @@ -14,21 +14,6 @@ * treated as a unit and regular routing would not be used to connect the carry_in's and * carry_out's. Floorplanning constraints may also be an example of placement macros. * - * The function alloc_and_load_placement_macros allocates and loads the placement - * macros in the following steps: - * (1) First, go through all the block types and mark down the pins that could possibly - * be part of a placement macros. - * (2) Then, go through the netlist of all the pins marked in (1) to find out all the - * heads of the placement macros using criteria depending on the type of placement - * macros. For carry chains, the heads of the placement macros are blocks with - * carry_in's not connected to any nets (OPEN) while the carry_out's connected to the - * netlist with only 1 SINK. - * (3) Traverse from the heads to the tails of the placement macros and load the - * information in the t_pl_macro data structure. Similar to (2), tails are identified - * with criteria depending on the type of placement macros. For carry chains, the - * tails are blocks with carry_out's not connected to any nets (OPEN) while the - * carry_in's is connected to the netlist which has only 1 SINK. - * * The only placement macros supported at the moment are the carry chains with limited * functionality. * @@ -133,38 +118,136 @@ #ifndef PLACE_MACRO_H #define PLACE_MACRO_H + #include #include "clustered_netlist_fwd.h" #include "physical_types.h" #include "vpr_types.h" -/* These are the placement macro structure. - * It is in the form of array of structs instead of - * structs of arrays for cache efficiency. - * Could have more data members for other macro type. - * blk_index: The cluster_ctx.blocks index of this block. - * x_offset: The x_offset from the first macro member to this member - * y_offset: The y_offset from the first macro member to this member - * z_offset: The z_offset from the first macro member to this member +/** + * @struct t_pl_macro_member + * @brief The placement macro structure. */ struct t_pl_macro_member { + ///@brief The cluster_ctx.blocks index of this block. ClusterBlockId blk_index; + ///@brief The location offset from the first macro member to this member t_pl_offset offset; }; -/* num_blocks: The number of blocks this macro contains. - * members: An array of blocks in this macro [0:num_macro-1]. - * idirect: The direct index as specified in the arch file - */ struct t_pl_macro { + ///@brief A vector of blocks in this macro [0:num_macro-1]. std::vector members; }; -/* These are the function declarations. */ -std::vector alloc_and_load_placement_macros(t_direct_inf* directs, int num_directs); -void get_imacro_from_iblk(int* imacro, ClusterBlockId iblk, const std::vector& macros); -void set_imacro_for_iblk(int* imacro, ClusterBlockId iblk); -void free_placement_macros_structs(); +class PlaceMacros { + public: + PlaceMacros() = default; + + /** + * @brief Allocates and loads the placement macros. + * @details The following steps are taken in this methodL + * (1) First, go through all the block types and mark down the pins that could possibly + * be part of a placement macros. + * (2) Then, go through the netlist of all the pins marked in (1) to find out all the + * heads of the placement macros using criteria depending on the type of placement + * macros. For carry chains, the heads of the placement macros are blocks with + * carry_in's not connected to any nets (OPEN) while the carry_out's connected to the + * netlist with only 1 SINK. + * (3) Traverse from the heads to the tails of the placement macros and load the + * information in the t_pl_macro data structure. Similar to (2), tails are identified + * with criteria depending on the type of placement macros. For carry chains, the + * tails are blocks with carry_out's not connected to any nets (OPEN) while the + * carry_in's is connected to the netlist which has only 1 SINK. + * @param directs + */ + void alloc_and_load_placement_macros(const std::vector& directs); + + /** + * @brief Returns the placement macro index to which the given block belongs. + * @param iblk The unique ID of a clustered block whose placement macro is of interest. + * @return The placement macro index that the given block is part of. A negative integer + * in returned if the block is not part of a macro. + */ + int get_imacro_from_iblk(ClusterBlockId iblk) const; + + /** + * @brief Finds the head block of the macro that contains a given clustered block + * @details Placement macro head is the base of the macro, where the locations of the other macro members can be + * calculated using base.loc + member.offset. + * + * @return The Id of a clustered block that is the head of a macro that the given clustered block is part of. + */ + ClusterBlockId macro_head(ClusterBlockId blk) const; + + /// @brief Returns a constant reference to all placement macros. + const std::vector& macros() const; + + /** + * @brief Returns the placement macro associated with a macro index. + * @param idx An index specifying a macro. get_imacro_from_iblk() can + * be called to find out a the macro index of the placement macro a + * clustered block is part of. + * @return A placement macro associated with the given index. + */ + const t_pl_macro& operator[](int idx) const; + + private: + + /** + * @brief This array allow us to quickly find pins that could be in a direct connection. + * @details Values stored is the index of the possible direct connection as specified in the arch file, + * OPEN (-1) is stored for pins that could not be part of a direct chain connection. + * [0...device_ctx.num_block_types-1][0...num_pins-1] + */ + std::vector> idirect_from_blk_pin_; + + /** + * @brief This array stores the value SOURCE if the pin is the from_pin, + * SINK if the pin is the to_pin in the direct connection as specified in the arch file, + * OPEN (-1) is stored for pins that could not be part of a direct chain connection. + * [0...device_ctx.num_block_types-1][0...num_pins-1] + */ + std::vector> direct_type_from_blk_pin_; + + /** + * @brief Maps a blk_num to the corresponding macro index. + * @details If the block is not part of a macro, the value OPEN (-1) is stored. + * [0...cluster_ctx.clb_nlist.blocks().size()-1] + */ + vtr::vector_map imacro_from_iblk_; + + ///@brief Stores all the placement macros (usually carry chains). + std::vector pl_macros_; + + private: + int find_all_the_macro_(std::vector& pl_macro_idirect, + std::vector& pl_macro_num_members, + std::vector>& pl_macro_member_blk_num); + + void alloc_and_load_imacro_from_iblk_(const std::vector& macros); + + void write_place_macros_(std::string filename, const std::vector& macros); + + bool net_is_driven_by_direct_(ClusterNetId clb_net); + + /** + * @brief Allocates and loads idirect_from_blk_pin and direct_type_from_blk_pin arrays. + * + * @details For a bus (multiple bits) direct connection, all the pins in the bus are marked. + * idirect_from_blk_pin vector allow us to quickly find pins that could be in a + * direct connection. Values stored is the index of the possible direct connection + * as specified in the arch file, OPEN (-1) is stored for pins that could not be + * part of a direct chain connection. + * + * direct_type_from_blk_pin vector stores the value SOURCE if the pin is the + * from_pin, SINK if the pin is the to_pin in the direct connection as specified in + * the arch file, OPEN (-1) is stored for pins that could not be part of a direct + * chain connection. + * @param directs Contains information about all direct connections in the architecture. + */ + void alloc_and_load_idirect_from_blk_pin_(const std::vector& directs); +}; #endif diff --git a/vpr/src/place/place_util.cpp b/vpr/src/place/place_util.cpp index df96e911d37..ce24914b7f2 100644 --- a/vpr/src/place/place_util.cpp +++ b/vpr/src/place/place_util.cpp @@ -17,16 +17,22 @@ */ static GridBlock init_grid_blocks(); -void init_placement_context(vtr::vector_map& block_locs, - GridBlock& grid_blocks) { +void init_placement_context(BlkLocRegistry& blk_loc_registry, + const std::vector& directs) { auto& cluster_ctx = g_vpr_ctx.clustering(); + auto& block_locs = blk_loc_registry.mutable_block_locs(); + auto& grid_blocks = blk_loc_registry.mutable_grid_blocks(); + auto& place_macros = blk_loc_registry.mutable_place_macros(); + /* Initialize the lookup of CLB block positions */ block_locs.clear(); block_locs.resize(cluster_ctx.clb_nlist.blocks().size()); /* Initialize the reverse lookup of CLB block positions */ grid_blocks = init_grid_blocks(); + + place_macros.alloc_and_load_placement_macros(directs); } static GridBlock init_grid_blocks() { diff --git a/vpr/src/place/place_util.h b/vpr/src/place/place_util.h index 9c3714b0488..60d4a86b1c5 100644 --- a/vpr/src/place/place_util.h +++ b/vpr/src/place/place_util.h @@ -309,11 +309,12 @@ class t_placer_statistics { * * Forward direction - block to grid: place_ctx.block_locs. * Reverse direction - grid to block: place_ctx.grid_blocks. + * Allocates and load placement macros. * * Initialize both of them to empty states. */ -void init_placement_context(vtr::vector_map& block_locs, - GridBlock& grid_blocks); +void init_placement_context(BlkLocRegistry& blk_loc_registry, + const std::vector& directs); /** * @brief Get the initial limit for inner loop block move attempt limit. diff --git a/vpr/src/place/simpleRL_move_generator.h b/vpr/src/place/simpleRL_move_generator.h index 9bdddc6c800..eacf736e79b 100644 --- a/vpr/src/place/simpleRL_move_generator.h +++ b/vpr/src/place/simpleRL_move_generator.h @@ -29,7 +29,7 @@ class KArmedBanditAgent { * @brief Update the agent Q-table based on the reward received by the SA algorithm * * @param reward A double value calculated in "place.cpp" file showing how placement cost was affected by the prior action taken - * @param reward_func The reward function used by the agent, detail explanation can be found on "directed_moves_util.h" file + * @param reward_func The reward function used by the agent. */ void process_outcome(double, e_reward_function); diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp index 06fb05911a8..86dc396e2b8 100644 --- a/vpr/src/place/timing_place_lookup.cpp +++ b/vpr/src/place/timing_place_lookup.cpp @@ -176,15 +176,13 @@ std::unique_ptr compute_place_delay_model(const t_placer_opts& t_det_routing_arch* det_routing_arch, std::vector& segment_inf, t_chan_width_dist chan_width_dist, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, bool is_flat) { vtr::ScopedStartFinishTimer timer("Computing placement delta delay look-up"); t_chan_width chan_width = setup_chan_width(router_opts, chan_width_dist); - alloc_routing_structs(chan_width, router_opts, det_routing_arch, segment_inf, - directs, num_directs, is_flat); + alloc_routing_structs(chan_width, router_opts, det_routing_arch, segment_inf, directs, is_flat); const RouterLookahead* router_lookahead = get_cached_router_lookahead(*det_routing_arch, router_opts.lookahead_type, @@ -737,7 +735,7 @@ static vtr::NdMatrix compute_delta_delays( auto type = grid.get_physical_type({x, y, from_layer_num}); if (type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { - if (!allowed_types.empty() && allowed_types.find(std::string(type->name)) == allowed_types.end()) { + if (!allowed_types.empty() && allowed_types.find(type->name) == allowed_types.end()) { continue; } src_type = type; @@ -781,7 +779,7 @@ static vtr::NdMatrix compute_delta_delays( auto type = grid.get_physical_type({x, y, from_layer_num}); if (type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { - if (!allowed_types.empty() && allowed_types.find(std::string(type->name)) == allowed_types.end()) { + if (!allowed_types.empty() && allowed_types.find(type->name) == allowed_types.end()) { continue; } src_type = type; @@ -1221,8 +1219,8 @@ void OverrideDelayModel::compute_override_delay_model( //Look at all the direct connections that exist, and add overrides to delay model auto& device_ctx = g_vpr_ctx.device(); - for (int idirect = 0; idirect < device_ctx.arch->num_directs; ++idirect) { - const t_direct_inf* direct = &device_ctx.arch->Directs[idirect]; + for (int idirect = 0; idirect < (int)device_ctx.arch->directs.size(); ++idirect) { + const t_direct_inf* direct = &device_ctx.arch->directs[idirect]; InstPort from_port = parse_inst_port(direct->from_pin); InstPort to_port = parse_inst_port(direct->to_pin); @@ -1285,8 +1283,8 @@ void OverrideDelayModel::compute_override_delay_model( sampled_rr_pairs.insert({src_rr, sink_rr}); } - VTR_LOGV_WARN(missing_instances > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no instances of this direct found)\n", missing_instances, direct->name); - VTR_LOGV_WARN(missing_paths > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no routing path found)\n", missing_paths, direct->name); + VTR_LOGV_WARN(missing_instances > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no instances of this direct found)\n", missing_instances, direct->name.c_str()); + VTR_LOGV_WARN(missing_paths > 0, "Found no delta delay for %d bits of inter-block direct connect '%s' (no routing path found)\n", missing_paths, direct->name.c_str()); } } diff --git a/vpr/src/place/timing_place_lookup.h b/vpr/src/place/timing_place_lookup.h index 30e1a8ae01a..fba3f470483 100644 --- a/vpr/src/place/timing_place_lookup.h +++ b/vpr/src/place/timing_place_lookup.h @@ -8,11 +8,11 @@ std::unique_ptr compute_place_delay_model(const t_placer_opts& t_det_routing_arch* det_routing_arch, std::vector& segment_inf, t_chan_width_dist chan_width_dist, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, bool is_flat); std::vector get_best_classes(enum e_pin_type pintype, t_physical_tile_type_ptr type); + bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node); #endif diff --git a/vpr/src/place/weighted_centroid_move_generator.cpp b/vpr/src/place/weighted_centroid_move_generator.cpp index 972bbfca4ec..a2b99cb1d86 100644 --- a/vpr/src/place/weighted_centroid_move_generator.cpp +++ b/vpr/src/place/weighted_centroid_move_generator.cpp @@ -1,71 +1,8 @@ #include "weighted_centroid_move_generator.h" -#include "globals.h" -#include "directed_moves_util.h" -#include "place_constraints.h" -#include "placer_state.h" -#include "move_utils.h" - WeightedCentroidMoveGenerator::WeightedCentroidMoveGenerator(PlacerState& placer_state, e_reward_function reward_function, vtr::RngContainer& rng) - : MoveGenerator(placer_state, reward_function, rng) {} - -e_create_move WeightedCentroidMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_affected, - t_propose_action& proposed_action, - float rlim, - const t_placer_opts& placer_opts, - const PlacerCriticalities* criticalities) { - const auto& cluster_ctx = g_vpr_ctx.clustering(); - const auto& device_ctx = g_vpr_ctx.device(); - auto& placer_state = placer_state_.get(); - const auto& block_locs = placer_state.block_locs(); - auto& place_move_ctx = placer_state.mutable_move(); - const auto& blk_loc_registry = placer_state.blk_loc_registry(); - - //Find a movable block based on blk_type - ClusterBlockId b_from = propose_block_to_move(placer_opts, - proposed_action.logical_blk_type_index, - /*highly_crit_block=*/false, - /*net_from=*/nullptr, - /*pin_from=*/nullptr, - placer_state, - rng_); - - VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "Weighted Centroid Move Choose Block %d - rlim %f\n", size_t(b_from), rlim); - - if (!b_from) { //No movable block found - VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\tNo movable block found\n"); - return e_create_move::ABORT; - } - - t_pl_loc from = block_locs[b_from].loc; - auto cluster_from_type = cluster_ctx.clb_nlist.block_type(b_from); - auto grid_from_type = device_ctx.grid.get_physical_type({from.x, from.y, from.layer}); - VTR_ASSERT(is_tile_compatible(grid_from_type, cluster_from_type)); - - t_range_limiters range_limiters{rlim, - place_move_ctx.first_rlim, - placer_opts.place_dm_rlim}; - - t_pl_loc to, centroid; - - /* Calculate the weighted centroid */ - calculate_centroid_loc(b_from, true, centroid, criticalities, blk_loc_registry); - - // Centroid location is not necessarily a valid location, and the downstream location expect a valid - // layer for "to" location. So if the layer is not valid, we set it to the same layer as from loc. - centroid.layer = (centroid.layer < 0) ? from.layer : centroid.layer; - if (!find_to_loc_centroid(cluster_from_type, from, centroid, range_limiters, to, b_from, blk_loc_registry, rng_)) { - return e_create_move::ABORT; - } - - e_create_move create_move = ::create_move(blocks_affected, b_from, to, blk_loc_registry); - - //Check that all the blocks affected by the move would still be in a legal floorplan region after the swap - if (!floorplan_legal(blocks_affected)) { - return e_create_move::ABORT; - } - - return create_move; + : CentroidMoveGenerator(placer_state, reward_function, rng) { + weighted_ = true; } diff --git a/vpr/src/place/weighted_centroid_move_generator.h b/vpr/src/place/weighted_centroid_move_generator.h index b7c6a6560ce..9a13ebabf08 100644 --- a/vpr/src/place/weighted_centroid_move_generator.h +++ b/vpr/src/place/weighted_centroid_move_generator.h @@ -1,30 +1,25 @@ #ifndef VPR_WEIGHTED_CENTROID_MOVE_GEN_H #define VPR_WEIGHTED_CENTROID_MOVE_GEN_H -#include "move_generator.h" -#include "timing_place.h" + +#include "centroid_move_generator.h" /** * @brief Weighted Centroid move generator * * This move generator is inspired by analytical placers: model net connections as springs and - * calculate the force equilibrium location. + * calculate the force equilibrium location. + * + * @details This class inherits from CentroidMoveGenerator to avoid code duplication. * * For more details, please refer to: * "Learn to Place: FPGA Placement using Reinforcement Learning and Directed Moves", ICFPT2020 */ -class WeightedCentroidMoveGenerator : public MoveGenerator { +class WeightedCentroidMoveGenerator : public CentroidMoveGenerator { public: WeightedCentroidMoveGenerator() = delete; WeightedCentroidMoveGenerator(PlacerState& placer_state, e_reward_function reward_function, vtr::RngContainer& rng); - - private: - e_create_move propose_move(t_pl_blocks_to_be_moved& blocks_affected, - t_propose_action& proposed_action, - float rlim, - const t_placer_opts& placer_opts, - const PlacerCriticalities* criticalities) override; }; #endif diff --git a/vpr/src/place/weighted_median_move_generator.cpp b/vpr/src/place/weighted_median_move_generator.cpp index 586de977130..b391509f5c3 100644 --- a/vpr/src/place/weighted_median_move_generator.cpp +++ b/vpr/src/place/weighted_median_move_generator.cpp @@ -42,11 +42,8 @@ e_create_move WeightedMedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& return e_create_move::ABORT; } - - int num_layers = g_vpr_ctx.device().grid.get_num_layers(); - t_pl_loc from = block_locs[b_from].loc; auto cluster_from_type = cluster_ctx.clb_nlist.block_type(b_from); auto grid_from_type = g_vpr_ctx.device().grid.get_physical_type({from.x, from.y, from.layer}); @@ -160,7 +157,7 @@ bool WeightedMedianMoveGenerator::get_bb_cost_for_net_excluding_block(ClusterNet const PlacerCriticalities* criticalities, t_bb_cost* coords) { const auto& blk_loc_registry = placer_state_.get().blk_loc_registry(); - const auto& block_locs = blk_loc_registry.block_locs(); + const auto& cluster_ctx = g_vpr_ctx.clustering(); bool skip_net = true; @@ -178,17 +175,10 @@ bool WeightedMedianMoveGenerator::get_bb_cost_for_net_excluding_block(ClusterNet float layer_min_cost = 0.f; float layer_max_cost = 0.f; - auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& device_ctx = g_vpr_ctx.device(); - auto& grid = device_ctx.grid; - bool is_first_block = true; for (ClusterPinId pin_id : cluster_ctx.clb_nlist.net_pins(net_id)) { - ClusterBlockId bnum = cluster_ctx.clb_nlist.pin_block(pin_id); - if (pin_id != moving_pin_id) { skip_net = false; - int pnum = blk_loc_registry.tile_pin_index(pin_id); /** * Calculates the pin index of the correct pin to calculate the required connection * @@ -203,56 +193,49 @@ bool WeightedMedianMoveGenerator::get_bb_cost_for_net_excluding_block(ClusterNet } float cost = criticalities->criticality(net_id, ipin); - VTR_ASSERT(pnum >= 0); - const t_pl_loc block_loc = block_locs[bnum].loc; - int x = block_loc.x + physical_tile_type(block_loc)->pin_width_offset[pnum]; - int y = block_loc.y + physical_tile_type(block_loc)->pin_height_offset[pnum]; - int layer = block_loc.layer; - - x = std::max(std::min(x, (int)grid.width() - 2), 1); //-2 for no perim channels - y = std::max(std::min(y, (int)grid.height() - 2), 1); //-2 for no perim channels + t_physical_tile_loc pin_loc = blk_loc_registry.get_coordinate_of_pin(pin_id); if (is_first_block) { - xmin = x; + xmin = pin_loc.x; xmin_cost = cost; - ymin = y; + ymin = pin_loc.y; ymin_cost = cost; - xmax = x; + xmax = pin_loc.x; xmax_cost = cost; - ymax = y; + ymax = pin_loc.y; ymax_cost = cost; - layer_min = layer; + layer_min = pin_loc.layer_num; layer_min_cost = cost; - layer_max = layer; + layer_max = pin_loc.layer_num; layer_max_cost = cost; is_first_block = false; } else { - if (x < xmin) { - xmin = x; + if (pin_loc.x < xmin) { + xmin = pin_loc.x; xmin_cost = cost; - } else if (x > xmax) { - xmax = x; + } else if (pin_loc.x > xmax) { + xmax = pin_loc.x; xmax_cost = cost; } - if (y < ymin) { - ymin = y; + if (pin_loc.y < ymin) { + ymin = pin_loc.y; ymin_cost = cost; - } else if (y > ymax) { - ymax = y; + } else if (pin_loc.y > ymax) { + ymax = pin_loc.y; ymax_cost = cost; } - if (layer < layer_min) { - layer_min = layer; + if (pin_loc.layer_num < layer_min) { + layer_min = pin_loc.layer_num; layer_min_cost = cost; - } else if (layer > layer_max) { - layer_max = layer; + } else if (pin_loc.layer_num > layer_max) { + layer_max = pin_loc.layer_num; layer_max_cost = cost; - } else if (layer == layer_min) { + } else if (pin_loc.layer_num == layer_min) { if (cost > layer_min_cost) layer_min_cost = cost; - } else if (layer == layer_max) { + } else if (pin_loc.layer_num == layer_max) { if (cost > layer_max_cost) layer_max_cost = cost; } diff --git a/vpr/src/route/cb_metrics.cpp b/vpr/src/route/cb_metrics.cpp index b10ddc7409b..a1fa4294179 100644 --- a/vpr/src/route/cb_metrics.cpp +++ b/vpr/src/route/cb_metrics.cpp @@ -218,8 +218,8 @@ void get_conn_block_metrics(const t_physical_tile_type_ptr block_type, int***** /* check based on block type whether we should account for pins on both sides of a channel when computing the relevant CB metrics * (i.e. from a block on the left and from a block on the right for a vertical channel, for instance) */ bool both_sides = false; - if (0 == strcmp("clb", block_type->name) && DRIVER == pin_type) { - /* many CLBs are adjacent to eachother, so connections from one CLB + if (block_type->name == "clb" && DRIVER == pin_type) { + /* many CLBs are adjacent to each other, so connections from one CLB * will share the channel segment with its neighbor. We'd like to take this into * account for the applicable metrics. */ both_sides = true; @@ -705,8 +705,8 @@ static double try_move(const e_metric metric, /* for the CLB block types it is appropriate to account for pins on both sides of a channel segment when * calculating a CB metric (because CLBs are often found side by side) */ bool both_sides = false; - if (0 == strcmp("clb", block_type->name) && DRIVER == pin_type) { - /* many CLBs are adjacent to eachother, so connections from one CLB + if (block_type->name == "clb" && DRIVER == pin_type) { + /* many CLBs are adjacent to each other, so connections from one CLB * will share the channel segment with its neighbor. We'd like to take this into * account for the applicable metrics. */ both_sides = true; @@ -1346,7 +1346,7 @@ static t_xbar_matrix combine_two_xbars(const t_xbar_matrix* xbar1, const t_xbar_ } void analyze_conn_blocks(const int***** opin_cb, const int***** ipin_cb, const t_physical_tile_type_ptr block_type, const int* Fc_array_out, const int* Fc_array_in, const t_chan_width* chan_width_inf) { - if (0 != strcmp(block_type->name, "clb")) { + if (block_type->name != "clb") { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "This code currently works for CLB blocks only"); } if (chan_width_inf->x_min != chan_width_inf->x_max || chan_width_inf->y_min != chan_width_inf->y_max diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index 688388b8689..369da62a7f7 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -418,7 +418,7 @@ static void log_single_overused_node_status(int overuse_index, RRNodeId node_id) VTR_LOG(" %7d", rr_graph.node_ptc_num(node_id)); // Block Name - VTR_LOG(" %7s", physical_blk->name); + VTR_LOG(" %7s", physical_blk->name.c_str()); //X_low VTR_LOG(" %7d", x); diff --git a/vpr/src/route/route.cpp b/vpr/src/route/route.cpp index ffc430f6fce..c2a094b494b 100644 --- a/vpr/src/route/route.cpp +++ b/vpr/src/route/route.cpp @@ -22,8 +22,7 @@ bool route(const Netlist<>& net_list, std::shared_ptr timing_info, std::shared_ptr delay_calc, t_chan_width_dist chan_width_dist, - t_direct_inf* directs, - int num_directs, + const std::vector& directs, ScreenUpdatePriority first_iteration_priority, bool is_flat) { auto& device_ctx = g_vpr_ctx.mutable_device(); @@ -59,7 +58,6 @@ bool route(const Netlist<>& net_list, segment_inf, router_opts, directs, - num_directs, &warning_count, is_flat); diff --git a/vpr/src/route/route.h b/vpr/src/route/route.h index cf6efb26311..082a417008e 100644 --- a/vpr/src/route/route.h +++ b/vpr/src/route/route.h @@ -27,7 +27,6 @@ bool route(const Netlist<>& net_list, std::shared_ptr timing_info, std::shared_ptr delay_calc, t_chan_width_dist chan_width_dist, - t_direct_inf* directs, - int num_directs, + const std::vector& directs, ScreenUpdatePriority first_iteration_priority, bool is_flat); diff --git a/vpr/src/route/route_utils.cpp b/vpr/src/route/route_utils.cpp index b67b544b47a..60dec8d18d4 100644 --- a/vpr/src/route/route_utils.cpp +++ b/vpr/src/route/route_utils.cpp @@ -469,8 +469,7 @@ void try_graph(int width_fac, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, t_chan_width_dist chan_width_dist, - t_direct_inf* directs, - int num_directs, + const std::vector& directs, bool is_flat) { auto& device_ctx = g_vpr_ctx.mutable_device(); @@ -499,7 +498,7 @@ void try_graph(int width_fac, det_routing_arch, segment_inf, router_opts, - directs, num_directs, + directs, &warning_count, is_flat); } diff --git a/vpr/src/route/route_utils.h b/vpr/src/route/route_utils.h index c7d79a61fbf..edf5a3b59f7 100644 --- a/vpr/src/route/route_utils.h +++ b/vpr/src/route/route_utils.h @@ -145,8 +145,7 @@ void try_graph(int width_fac, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, t_chan_width_dist chan_width_dist, - t_direct_inf* directs, - int num_directs, + const std::vector& directs, bool is_flat); /* This routine updates the pres_fac used by the drawing functions */ diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index ae25d5cdf78..5feb0e9b2f6 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -247,8 +247,7 @@ void alloc_routing_structs(const t_chan_width& chan_width, const t_router_opts& router_opts, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, bool is_flat) { int warnings; t_graph_type graph_type; @@ -268,7 +267,7 @@ void alloc_routing_structs(const t_chan_width& chan_width, det_routing_arch, segment_inf, router_opts, - directs, num_directs, + directs, &warnings, is_flat); diff --git a/vpr/src/route/router_delay_profiling.h b/vpr/src/route/router_delay_profiling.h index 1d5ae1b21c1..ca855720d85 100644 --- a/vpr/src/route/router_delay_profiling.h +++ b/vpr/src/route/router_delay_profiling.h @@ -56,8 +56,7 @@ void alloc_routing_structs(const t_chan_width& chan_width, const t_router_opts& router_opts, t_det_routing_arch* det_routing_arch, std::vector& segment_inf, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, bool is_flat); void free_routing_structs(); diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index 798ebcccf37..cc285616146 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -412,7 +412,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat) { VTR_LOG_WARN("Found no %ssample locations for %s in %s\n", (num_sampled_locs == 0) ? "" : "more ", rr_node_typename[rr_type], - device_ctx.physical_tile_types[itile].name); + device_ctx.physical_tile_types[itile].name.c_str()); break; } @@ -491,7 +491,7 @@ t_chan_ipins_delays compute_router_chan_ipin_lookahead() { if (sample_loc.x == OPEN && sample_loc.y == OPEN && sample_loc.layer_num == OPEN) { //No untried instances of the current tile type left VTR_LOG_WARN("Found no sample locations for %s\n", - tile_type.name); + tile_type.name.c_str()); continue; } diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 855707bd58a..0b2073555de 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -174,8 +174,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, const DeviceGrid& grid, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, const t_clb_to_clb_directs* clb_to_clb_directs, const int num_seg_types); @@ -195,8 +194,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, t_rr_edge_info_set& created_rr_edges, bool* Fc_clipped, const t_unified_to_parallel_seg_index& seg_index_map, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, const t_clb_to_clb_directs* clb_to_clb_directs, const int num_seg_types, int& edge_count); @@ -210,8 +208,7 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder, int opin, RRNodeId from_rr_node, t_rr_edge_info_set& rr_edges_to_create, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, const t_clb_to_clb_directs* clb_to_clb_directs); static std::function alloc_and_load_rr_graph(RRGraphBuilder& rr_graph_builder, @@ -240,8 +237,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder const int delayless_switch, const enum e_directionality directionality, bool* Fc_clipped, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, const t_clb_to_clb_directs* clb_to_clb_directs, bool is_global_graph, const enum e_clock_modeling clock_modeling, @@ -620,7 +616,7 @@ static void rr_graph_externals(const std::vector& segment_inf, int wire_to_rr_ipin_switch, enum e_base_cost_type base_cost_type); -static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, const int delayless_switch); +static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, const int delayless_switch); static t_seg_details* alloc_and_load_global_route_seg_details(const int global_route_switch, int* num_seg_details = nullptr); @@ -744,8 +740,7 @@ static void build_rr_graph(const t_graph_type graph_type, const float R_minW_pmos, const enum e_base_cost_type base_cost_type, const enum e_clock_modeling clock_modeling, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, int* wire_to_rr_ipin_switch, bool is_flat, int* Warnings, @@ -780,8 +775,7 @@ void create_rr_graph(const t_graph_type graph_type, t_det_routing_arch* det_routing_arch, const std::vector& segment_inf, const t_router_opts& router_opts, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, int* Warnings, bool is_flat) { const auto& device_ctx = g_vpr_ctx.device(); @@ -849,7 +843,7 @@ void create_rr_graph(const t_graph_type graph_type, det_routing_arch->R_minW_pmos, router_opts.base_cost_type, router_opts.clock_modeling, - directs, num_directs, + directs, &det_routing_arch->wire_to_rr_ipin_switch, is_flat, Warnings, @@ -1075,8 +1069,7 @@ static void build_rr_graph(const t_graph_type graph_type, const float R_minW_pmos, const enum e_base_cost_type base_cost_type, const enum e_clock_modeling clock_modeling, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, int* wire_to_rr_ipin_switch, bool is_flat, int* Warnings, @@ -1106,8 +1099,8 @@ static void build_rr_graph(const t_graph_type graph_type, const auto& rr_graph = device_ctx.rr_graph; t_clb_to_clb_directs* clb_to_clb_directs = nullptr; - if (num_directs > 0) { - clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, num_directs, delayless_switch); + if (!directs.empty()) { + clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch); } /* START SEG_DETAILS */ @@ -1460,7 +1453,6 @@ static void build_rr_graph(const t_graph_type graph_type, auto update_chan_width = alloc_and_load_rr_graph( device_ctx.rr_graph_builder, - device_ctx.rr_graph_builder.rr_nodes(), device_ctx.rr_graph, segment_inf.size(), segment_inf_x.size(), segment_index_map, @@ -1476,7 +1468,8 @@ static void build_rr_graph(const t_graph_type graph_type, delayless_switch, directionality, &Fc_clipped, - directs, num_directs, clb_to_clb_directs, + directs, + clb_to_clb_directs, is_global_graph, clock_modeling, is_flat, @@ -2158,8 +2151,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder const int delayless_switch, const enum e_directionality directionality, bool* Fc_clipped, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, const t_clb_to_clb_directs* clb_to_clb_directs, bool is_global_graph, const enum e_clock_modeling clock_modeling, @@ -2245,14 +2237,14 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder opin_to_track_map, Fc_out, rr_edges_to_create, chan_details_x, chan_details_y, grid, - directs, num_directs, clb_to_clb_directs, num_seg_types); + directs, clb_to_clb_directs, num_seg_types); } else { VTR_ASSERT(UNI_DIRECTIONAL == directionality); bool clipped; build_unidir_rr_opins(rr_graph_builder, rr_graph, layer, i, j, side, grid, Fc_out, chan_width, chan_details_x, chan_details_y, Fc_xofs, Fc_yofs, rr_edges_to_create, &clipped, seg_index_map, - directs, num_directs, clb_to_clb_directs, num_seg_types, + directs, clb_to_clb_directs, num_seg_types, rr_edges_before_directs); if (clipped) { *Fc_clipped = true; @@ -2743,8 +2735,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, const DeviceGrid& grid, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, const t_clb_to_clb_directs* clb_to_clb_directs, const int num_seg_types) { //Don't connect pins which are not adjacent to channels around the perimeter @@ -2793,7 +2784,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder, /* Add in direct connections */ get_opin_direct_connections(rr_graph_builder, rr_graph, layer, i, j, side, pin_index, node_index, rr_edges_to_create, - directs, num_directs, clb_to_clb_directs); + directs, clb_to_clb_directs); } } @@ -4244,8 +4235,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, t_rr_edge_info_set& rr_edges_to_create, bool* Fc_clipped, const t_unified_to_parallel_seg_index& seg_index_map, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, const t_clb_to_clb_directs* clb_to_clb_directs, const int num_seg_types, int& rr_edge_count) { @@ -4346,7 +4336,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, /* Add in direct connections */ get_opin_direct_connections(rr_graph_builder, rr_graph, layer, i, j, side, pin_index, opin_node_index, rr_edges_to_create, - directs, num_directs, clb_to_clb_directs); + directs, clb_to_clb_directs); } } @@ -4355,22 +4345,17 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, * This data structure supplements the the info in the "directs" data structure * TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one */ -static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch) { - int i; +static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, int delayless_switch) { t_clb_to_clb_directs* clb_to_clb_directs; - char *tile_name, *port_name; - int start_pin_index, end_pin_index; t_physical_tile_type_ptr physical_tile = nullptr; t_physical_tile_port tile_port; auto& device_ctx = g_vpr_ctx.device(); + const int num_directs = directs.size(); clb_to_clb_directs = new t_clb_to_clb_directs[num_directs]; - tile_name = nullptr; - port_name = nullptr; - - for (i = 0; i < num_directs; i++) { + for (int i = 0; i < num_directs; i++) { //clb_to_clb_directs[i].from_clb_type; clb_to_clb_directs[i].from_clb_pin_start_index = 0; clb_to_clb_directs[i].from_clb_pin_end_index = 0; @@ -4379,23 +4364,20 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in clb_to_clb_directs[i].to_clb_pin_end_index = 0; clb_to_clb_directs[i].switch_index = 0; - tile_name = new char[strlen(directs[i].from_pin) + strlen(directs[i].to_pin)]; - port_name = new char[strlen(directs[i].from_pin) + strlen(directs[i].to_pin)]; - // Load from pins // Parse out the pb_type name, port name, and pin range - parse_direct_pin_name(directs[i].from_pin, directs[i].line, &start_pin_index, &end_pin_index, tile_name, port_name); + auto [start_pin_index, end_pin_index, tile_name, port_name] = parse_direct_pin_name(directs[i].from_pin, directs[i].line); // Figure out which type, port, and pin is used - for (const auto& type : device_ctx.physical_tile_types) { - if (strcmp(type.name, tile_name) == 0) { + for (const t_physical_tile_type& type : device_ctx.physical_tile_types) { + if (tile_name == type.name) { physical_tile = &type; break; } } if (physical_tile == nullptr) { - VPR_THROW(VPR_ERROR_ARCH, "Unable to find block %s.\n", tile_name); + VPR_THROW(VPR_ERROR_ARCH, "Unable to find block %s.\n", tile_name.c_str()); } clb_to_clb_directs[i].from_clb_type = physical_tile; @@ -4415,18 +4397,18 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in // Load to pins // Parse out the pb_type name, port name, and pin range - parse_direct_pin_name(directs[i].to_pin, directs[i].line, &start_pin_index, &end_pin_index, tile_name, port_name); + std::tie(start_pin_index, end_pin_index, tile_name, port_name) = parse_direct_pin_name(directs[i].to_pin, directs[i].line); // Figure out which type, port, and pin is used - for (const auto& type : device_ctx.physical_tile_types) { - if (strcmp(type.name, tile_name) == 0) { + for (const t_physical_tile_type& type : device_ctx.physical_tile_types) { + if (tile_name == type.name ) { physical_tile = &type; break; } } if (physical_tile == nullptr) { - VPR_THROW(VPR_ERROR_ARCH, "Unable to find block %s.\n", tile_name); + VPR_THROW(VPR_ERROR_ARCH, "Unable to find block %s.\n", tile_name.c_str()); } clb_to_clb_directs[i].to_clb_type = physical_tile; @@ -4446,7 +4428,7 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in if (abs(clb_to_clb_directs[i].from_clb_pin_start_index - clb_to_clb_directs[i].from_clb_pin_end_index) != abs(clb_to_clb_directs[i].to_clb_pin_start_index - clb_to_clb_directs[i].to_clb_pin_end_index)) { vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), directs[i].line, - "Range mismatch from %s to %s.\n", directs[i].from_pin, directs[i].to_pin); + "Range mismatch from %s to %s.\n", directs[i].from_pin.c_str(), directs[i].to_pin.c_str()); } //Set the switch index @@ -4457,8 +4439,6 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in //Use the delayless switch by default clb_to_clb_directs[i].switch_index = delayless_switch; } - delete[] tile_name; - delete[] port_name; } return clb_to_clb_directs; @@ -4477,8 +4457,7 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder, int opin, RRNodeId from_rr_node, t_rr_edge_info_set& rr_edges_to_create, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, const t_clb_to_clb_directs* clb_to_clb_directs) { auto& device_ctx = g_vpr_ctx.device(); @@ -4493,9 +4472,9 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder, } //Capacity location determined by pin number relative to pins per capacity instance - int z, relative_opin; - std::tie(z, relative_opin) = get_capacity_location_from_physical_pin(curr_type, opin); + auto [z, relative_opin] = get_capacity_location_from_physical_pin(curr_type, opin); VTR_ASSERT(z >= 0 && z < curr_type->capacity); + const int num_directs = directs.size(); /* Iterate through all direct connections */ for (int i = 0; i < num_directs; i++) { diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index 7b7423d23f4..b0b3b7d1f00 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -27,8 +27,7 @@ void create_rr_graph(const t_graph_type graph_type, t_det_routing_arch* det_routing_arch, const std::vector& segment_inf, const t_router_opts& router_opts, - const t_direct_inf* directs, - const int num_directs, + const std::vector& directs, int* Warnings, bool is_flat); diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 39c1e0ab697..fc271a8b795 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1165,7 +1165,7 @@ void dump_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map, for (int width = 0; width < types[i].width; ++width) { for (int height = 0; height < types[i].height; ++height) { for (int side = 0; side < 4; ++side) { - fprintf(fp, "\nTYPE:%s width:%d height:%d layer:%d\n", types[i].name, width, height, layer); + fprintf(fp, "\nTYPE:%s width:%d height:%d layer:%d\n", types[i].name.c_str(), width, height, layer); fprintf(fp, "\nSIDE:%d TRACK:%d \n", side, track); for (size_t con = 0; con < track_to_pin_map[i][track][width][height][layer][side].size(); con++) { fprintf(fp, "%d ", track_to_pin_map[i][track][width][height][layer][side][con]); diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 3caf87e43ba..7db2815cf3e 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -2,7 +2,6 @@ #include #include #include -#include #include "pack_types.h" #include "prepack.h" @@ -26,45 +25,13 @@ /* This module contains subroutines that are used in several unrelated parts * * of VPR. They are VPR-specific utility routines. */ -/* This defines the maximum string length that could be parsed by functions * - * in vpr_utils. */ -static constexpr size_t MAX_STRING_LEN = 512; - /******************** File-scope variables declarations **********************/ - -/* These three mappings are needed since there are two different netlist * - * conventions - in the cluster level, ports and port pins are used * - * while in the post-pack level, block pins are used. The reason block * - * type is used instead of blocks is to save memories. */ - -/* f_port_pin_to_block_pin array allows us to quickly find what block * - * pin a port pin corresponds to. * - * [0...device_ctx.physical_tile_types.size()-1][0..num_sub_tiles][0...num_ports-1][0...num_port_pins-1] */ -static std::vector>>> f_blk_pin_from_port_pin; - //Regular expressions used to determine register and logic primitives //TODO: Make this set-able from command-line? const std::regex REGISTER_MODEL_REGEX("(.subckt\\s+)?.*(latch|dff).*", std::regex::icase); const std::regex LOGIC_MODEL_REGEX("(.subckt\\s+)?.*(lut|names|lcell).*", std::regex::icase); /******************** Subroutine declarations ********************************/ - -/* Allocates and loads blk_pin_from_port_pin array. */ -static void alloc_and_load_blk_pin_from_port_pin(); - -/* Go through all the ports in all the blocks to find the port that has the same * - * name as port_name and belongs to the block type that has the name pb_type_name. * - * Then, check that whether start_pin_index and end_pin_index are specified. If * - * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * - * Otherwise, mark down all the pins in that port. */ -static void mark_direct_of_ports(int idirect, int direct_type, char* pb_type_name, char* port_name, int end_pin_index, int start_pin_index, char* src_string, int line, int** idirect_from_blk_pin, int** direct_type_from_blk_pin); - -static void get_blk_pin_from_port_pin(int blk_type_index, int sub_tile, int port, int port_pin, int* blk_pin); -/* Mark the pin entry in idirect_from_blk_pin with idirect and the pin entry in * - * direct_type_from_blk_pin with direct_type from start_pin_index to * - * end_pin_index. */ -static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, int isub_tile, int iport, int** idirect_from_blk_pin, int idirect, int** direct_type_from_blk_pin, int direct_type, int line, char* src_string); - static void load_pb_graph_pin_lookup_from_index_rec(t_pb_graph_pin** pb_graph_pin_lookup_from_index, t_pb_graph_node* pb_graph_node); static void load_pin_id_to_pb_mapping_rec(t_pb* cur_pb, t_pb** pin_id_to_pb_mapping); @@ -116,8 +83,7 @@ const t_model_ports* find_model_port(const t_model* model, const std::string& na * print tabs given number of tabs to file */ void print_tabs(FILE* fpout, int num_tab) { - int i; - for (i = 0; i < num_tab; i++) { + for (int i = 0; i < num_tab; i++) { fprintf(fpout, "\t"); } } @@ -170,8 +136,8 @@ void sync_grid_to_blocks() { if (type != device_ctx.grid.get_physical_type({blk_x, blk_y, blk_layer})) { VPR_FATAL_ERROR(VPR_ERROR_PLACE, "A block is in a grid location (%d x %d) layer (%d) with a conflicting types '%s' and '%s' .\n", blk_x, blk_y, blk_layer, - type->name, - device_ctx.grid.get_physical_type({blk_x, blk_y, blk_layer})->name); + type->name.c_str(), + device_ctx.grid.get_physical_type({blk_x, blk_y, blk_layer})->name.c_str()); } /* Check already in use */ @@ -584,24 +550,20 @@ int get_sub_tile_index(ClusterBlockId blk) { * for the node. */ int get_unique_pb_graph_node_id(const t_pb_graph_node* pb_graph_node) { - t_pb_graph_pin first_input_pin; - t_pb_graph_pin first_output_pin; - int node_id; - if (pb_graph_node->num_input_pins != nullptr) { /* If input port exists on this node, return the index of the first * input pin as node_id. */ - first_input_pin = pb_graph_node->input_pins[0][0]; - node_id = first_input_pin.pin_count_in_cluster; + t_pb_graph_pin first_input_pin = pb_graph_node->input_pins[0][0]; + int node_id = first_input_pin.pin_count_in_cluster; return node_id; } else { /* If no input port exists on node, then return the index of the first * output pin. Every pb_node is guaranteed to have at least an input or * output pin. */ - first_output_pin = pb_graph_node->output_pins[0][0]; - node_id = first_output_pin.pin_count_in_cluster; + t_pb_graph_pin first_output_pin = pb_graph_node->output_pins[0][0]; + int node_id = first_output_pin.pin_count_in_cluster; return node_id; } } @@ -878,15 +840,14 @@ static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::reg } int get_max_primitives_in_pb_type(t_pb_type* pb_type) { - int i, j; - int max_size, temp_size; + int max_size; if (pb_type->modes == nullptr) { max_size = 1; } else { max_size = 0; - temp_size = 0; - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + int temp_size = 0; + for (int i = 0; i < pb_type->num_modes; i++) { + for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { temp_size += pb_type->modes[i].pb_type_children[j].num_pb * get_max_primitives_in_pb_type( &pb_type->modes[i].pb_type_children[j]); @@ -901,15 +862,14 @@ int get_max_primitives_in_pb_type(t_pb_type* pb_type) { /* finds maximum number of nets that can be contained in pb_type, this is bounded by the number of driving pins */ int get_max_nets_in_pb_type(const t_pb_type* pb_type) { - int i, j; - int max_nets, temp_nets; + int max_nets; if (pb_type->modes == nullptr) { max_nets = pb_type->num_output_pins; } else { max_nets = 0; - for (i = 0; i < pb_type->num_modes; i++) { - temp_nets = 0; - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + for (int i = 0; i < pb_type->num_modes; i++) { + int temp_nets = 0; + for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { temp_nets += pb_type->modes[i].pb_type_children[j].num_pb * get_max_nets_in_pb_type( &pb_type->modes[i].pb_type_children[j]); @@ -927,13 +887,10 @@ int get_max_nets_in_pb_type(const t_pb_type* pb_type) { } int get_max_depth_of_pb_type(t_pb_type* pb_type) { - int i, j; - int max_depth, temp_depth; - max_depth = pb_type->depth; - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - temp_depth = get_max_depth_of_pb_type( - &pb_type->modes[i].pb_type_children[j]); + int max_depth = pb_type->depth; + for (int i = 0; i < pb_type->num_modes; i++) { + for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { + int temp_depth = get_max_depth_of_pb_type(&pb_type->modes[i].pb_type_children[j]); if (temp_depth > max_depth) { max_depth = temp_depth; } @@ -1034,11 +991,9 @@ AtomBlockId find_memory_sibling(const t_pb* pb) { * NULL if not found */ t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(const t_model_ports* model_port, const int model_pin, const t_pb_graph_node* pb_graph_node) { - int i; - if (model_port->dir == IN_PORT) { - if (model_port->is_clock == false) { - for (i = 0; i < pb_graph_node->num_input_ports; i++) { + if (!model_port->is_clock) { + for (int i = 0; i < pb_graph_node->num_input_ports; i++) { if (pb_graph_node->input_pins[i][0].port->model_port == model_port) { if (pb_graph_node->num_input_pins[i] > model_pin) { return &pb_graph_node->input_pins[i][model_pin]; @@ -1048,7 +1003,7 @@ t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(const t_model_ports* m } } } else { - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { + for (int i = 0; i < pb_graph_node->num_clock_ports; i++) { if (pb_graph_node->clock_pins[i][0].port->model_port == model_port) { if (pb_graph_node->num_clock_pins[i] > model_pin) { return &pb_graph_node->clock_pins[i][model_pin]; @@ -1060,7 +1015,7 @@ t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(const t_model_ports* m } } else { VTR_ASSERT(model_port->dir == OUT_PORT); - for (i = 0; i < pb_graph_node->num_output_ports; i++) { + for (int i = 0; i < pb_graph_node->num_output_ports; i++) { if (pb_graph_node->output_pins[i][0].port->model_port == model_port) { if (pb_graph_node->num_output_pins[i] > model_pin) { return &pb_graph_node->output_pins[i][model_pin]; @@ -1615,64 +1570,6 @@ void free_pb_stats(t_pb* pb) { } } -/*************************************************************************************** - * Y.G.THIEN - * 29 AUG 2012 - * - * The following functions maps the block pins indices for all block types to the * - * corresponding port indices and port_pin indices. This is necessary since there are * - * different netlist conventions - in the cluster level, ports and port pins are used * - * while in the post-pack level, block pins are used. * - * * - ***************************************************************************************/ - -static void get_blk_pin_from_port_pin(int blk_type_index, int sub_tile, int port, int port_pin, int* blk_pin) { - /* This mapping is needed since there are two different netlist * - * conventions - in the cluster level, ports and port pins are used * - * while in the post-pack level, block pins are used. The reason block * - * type is used instead of blocks is to save memories. * - * * - * f_port_pin_to_block_pin array allows us to quickly find what block * - * pin a port pin corresponds to. * - * [0...device_ctx.logical_block_types.size()-1][0...num_ports-1][0...num_port_pins-1] */ - - /* If the array is not allocated and loaded, allocate it. */ - if (f_blk_pin_from_port_pin.empty()) { - alloc_and_load_blk_pin_from_port_pin(); - } - - /* Return the port and port_pin for the pin. */ - *blk_pin = f_blk_pin_from_port_pin[blk_type_index][sub_tile][port][port_pin]; -} - -static void alloc_and_load_blk_pin_from_port_pin() { - /* Allocates and loads blk_pin_from_port_pin array. */ - - auto& device_ctx = g_vpr_ctx.device(); - auto& types = device_ctx.physical_tile_types; - - /* Resize and initialize the values to OPEN (-1). */ - int num_types = types.size(); - f_blk_pin_from_port_pin.resize(num_types); - for (int itype = 1; itype < num_types; itype++) { - int blk_pin_count = 0; - auto& type = types[itype]; - int num_sub_tiles = type.sub_tiles.size(); - f_blk_pin_from_port_pin[itype].resize(num_sub_tiles); - for (int isub_tile = 0; isub_tile < num_sub_tiles; isub_tile++) { - int num_ports = type.sub_tiles[isub_tile].ports.size(); - f_blk_pin_from_port_pin[itype][isub_tile].resize(num_ports); - for (int iport = 0; iport < num_ports; iport++) { - int num_pins = type.sub_tiles[isub_tile].ports[iport].num_pins; - for (int ipin = 0; ipin < num_pins; ipin++) { - f_blk_pin_from_port_pin[itype][isub_tile][iport].push_back(blk_pin_count); - blk_pin_count++; - } - } - } - } -} - /*************************************************************************************** * Y.G.THIEN * 30 AUG 2012 @@ -1688,15 +1585,7 @@ static void alloc_and_load_blk_pin_from_port_pin() { * load placement macros in place_macro.c * * * ***************************************************************************************/ - -void parse_direct_pin_name(char* src_string, int line, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name) { - /* Parses out the pb_type_name and port_name from the direct passed in. * - * If the start_pin_index and end_pin_index is specified, parse them too. * - * Return the values parsed by reference. */ - - char source_string[MAX_STRING_LEN + 1]; - char* find_format = nullptr; - int ichar, match_count; +std::tuple parse_direct_pin_name(std::string_view src_string, int line) { if (vtr::split(src_string).size() > 1) { VPR_THROW(VPR_ERROR_ARCH, @@ -1704,24 +1593,21 @@ void parse_direct_pin_name(char* src_string, int line, int* start_pin_index, int } // parse out the pb_type and port name, possibly pin_indices - find_format = strstr(src_string, "["); - if (find_format == nullptr) { + if (src_string.find('[') == std::string_view::npos) { /* Format "pb_type_name.port_name" */ - *start_pin_index = *end_pin_index = -1; + const int start_pin_index = -1; + const int end_pin_index = -1; - if (strlen(src_string) + 1 <= MAX_STRING_LEN + 1) { - strcpy(source_string, src_string); - } else { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, - "Pin name exceeded buffer size of %zu characters", MAX_STRING_LEN + 1); - } - for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { - if (source_string[ichar] == '.') - source_string[ichar] = ' '; - } + std::string source_string{src_string}; + // replace '.' characters with space + std::replace(source_string.begin(), source_string.end(), '.', ' '); + + std::istringstream source_iss(source_string); + std::string pb_type_name, port_name; - match_count = sscanf(source_string, "%s %s", pb_type_name, port_name); - if (match_count != 2) { + if (source_iss >> pb_type_name >> port_name) { + return {start_pin_index, end_pin_index, pb_type_name, port_name}; + } else { VTR_LOG_ERROR( "[LINE %d] Invalid pin - %s, name should be in the format " "\"pb_type_name\".\"port_name\" or \"pb_type_name\".\"port_name[end_pin_index:start_pin_index]\". " @@ -1731,214 +1617,45 @@ void parse_direct_pin_name(char* src_string, int line, int* start_pin_index, int } } else { /* Format "pb_type_name.port_name[end_pin_index:start_pin_index]" */ - strcpy(source_string, src_string); - for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { - //Need white space between the components when using %s with - //sscanf - if (source_string[ichar] == '.') - source_string[ichar] = ' '; - if (source_string[ichar] == '[') - source_string[ichar] = ' '; - } - - match_count = sscanf(source_string, "%s %s %d:%d]", - pb_type_name, port_name, - end_pin_index, start_pin_index); - if (match_count != 4) { - VTR_LOG_ERROR( - "[LINE %d] Invalid pin - %s, name should be in the format " - "\"pb_type_name\".\"port_name\" or \"pb_type_name\".\"port_name[end_pin_index:start_pin_index]\". " - "The end_pin_index and start_pin_index can be the same.\n", - line, src_string); - exit(1); - } - if (*end_pin_index < 0 || *start_pin_index < 0) { - VTR_LOG_ERROR( - "[LINE %d] Invalid pin - %s, the pin_index in " - "[end_pin_index:start_pin_index] should not be a negative value.\n", - line, src_string); - exit(1); - } - if (*end_pin_index < *start_pin_index) { - VTR_LOG_ERROR( - "[LINE %d] Invalid from_pin - %s, the end_pin_index in " - "[end_pin_index:start_pin_index] should not be less than start_pin_index.\n", - line, src_string); - exit(1); - } - } -} - -static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, int isub_tile, int iport, int** idirect_from_blk_pin, int idirect, int** direct_type_from_blk_pin, int direct_type, int line, char* src_string) { - /* Mark the pin entry in idirect_from_blk_pin with idirect and the pin entry in * - * direct_type_from_blk_pin with direct_type from start_pin_index to * - * end_pin_index. */ + std::string source_string{src_string}; - int iport_pin, iblk_pin; - auto& device_ctx = g_vpr_ctx.device(); + // Replace '.' and '[' characters with ' ' + std::replace_if(source_string.begin(), source_string.end(), + [](char c) { return c == '.' || c == '[' || c == ':' || c == ']'; }, + ' '); - // Mark pins with indices from start_pin_index to end_pin_index, inclusive - for (iport_pin = start_pin_index; iport_pin <= end_pin_index; iport_pin++) { - get_blk_pin_from_port_pin(itype, isub_tile, iport, iport_pin, &iblk_pin); - - //iterate through all segment connections and check if all Fc's are 0 - bool all_fcs_0 = true; - for (const auto& fc_spec : device_ctx.physical_tile_types[itype].fc_specs) { - for (int ipin : fc_spec.pins) { - if (iblk_pin == ipin && fc_spec.fc_value > 0) { - all_fcs_0 = false; - break; - } - } - if (!all_fcs_0) break; - } + std::istringstream source_iss(source_string); + int start_pin_index, end_pin_index; + std::string pb_type_name, port_name; - // Check the fc for the pin, direct chain link only if fc == 0 - if (all_fcs_0) { - idirect_from_blk_pin[itype][iblk_pin] = idirect; + if (source_iss >> pb_type_name >> port_name >> end_pin_index >> start_pin_index) { - // Check whether the pins are marked, errors out if so - if (direct_type_from_blk_pin[itype][iblk_pin] != OPEN) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, - "[LINE %d] Invalid pin - %s, this pin is in more than one direct connection.\n", - line, src_string); - } else { - direct_type_from_blk_pin[itype][iblk_pin] = direct_type; + if (end_pin_index < 0 || start_pin_index < 0) { + VTR_LOG_ERROR( + "[LINE %d] Invalid pin - %s, the pin_index in " + "[end_pin_index:start_pin_index] should not be a negative value.\n", + line, src_string); + exit(1); } - } - } // Finish marking all the pins -} - -static void mark_direct_of_ports(int idirect, int direct_type, char* pb_type_name, char* port_name, int end_pin_index, int start_pin_index, char* src_string, int line, int** idirect_from_blk_pin, int** direct_type_from_blk_pin) { - /* Go through all the ports in all the blocks to find the port that has the same * - * name as port_name and belongs to the block type that has the name pb_type_name. * - * Then, check that whether start_pin_index and end_pin_index are specified. If * - * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * - * Otherwise, mark down all the pins in that port. */ - auto& device_ctx = g_vpr_ctx.device(); - - // Go through all the block types - for (int itype = 1; itype < (int)device_ctx.physical_tile_types.size(); itype++) { - auto& physical_tile = device_ctx.physical_tile_types[itype]; - // Find blocks with the same pb_type_name - if (strcmp(physical_tile.name, pb_type_name) == 0) { - int num_sub_tiles = physical_tile.sub_tiles.size(); - for (int isub_tile = 0; isub_tile < num_sub_tiles; isub_tile++) { - auto& ports = physical_tile.sub_tiles[isub_tile].ports; - int num_ports = ports.size(); - for (int iport = 0; iport < num_ports; iport++) { - // Find ports with the same port_name - if (strcmp(ports[iport].name, port_name) == 0) { - int num_port_pins = ports[iport].num_pins; - - // Check whether the end_pin_index is valid - if (end_pin_index > num_port_pins) { - VTR_LOG_ERROR( - "[LINE %d] Invalid pin - %s, the end_pin_index in " - "[end_pin_index:start_pin_index] should " - "be less than the num_port_pins %d.\n", - line, src_string, num_port_pins); - exit(1); - } - - // Check whether the pin indices are specified - if (start_pin_index >= 0 || end_pin_index >= 0) { - mark_direct_of_pins(start_pin_index, end_pin_index, itype, - isub_tile, iport, idirect_from_blk_pin, idirect, - direct_type_from_blk_pin, direct_type, line, src_string); - } else { - mark_direct_of_pins(0, num_port_pins - 1, itype, - isub_tile, iport, idirect_from_blk_pin, idirect, - direct_type_from_blk_pin, direct_type, line, src_string); - } - } // Do nothing if port_name does not match - } // Finish going through all the ports - } // Finish going through all the subtiles - } // Do nothing if pb_type_name does not match - } // Finish going through all the blocks -} - -void alloc_and_load_idirect_from_blk_pin(t_direct_inf* directs, int num_directs, int*** idirect_from_blk_pin, int*** direct_type_from_blk_pin) { - /* Allocates and loads idirect_from_blk_pin and direct_type_from_blk_pin arrays. * - * * - * For a bus (multiple bits) direct connection, all the pins in the bus are marked. * - * * - * idirect_from_blk_pin array allow us to quickly find pins that could be in a * - * direct connection. Values stored is the index of the possible direct connection * - * as specified in the arch file, OPEN (-1) is stored for pins that could not be * - * part of a direct chain conneciton. * - * * - * direct_type_from_blk_pin array stores the value SOURCE if the pin is the * - * from_pin, SINK if the pin is the to_pin in the direct connection as specified in * - * the arch file, OPEN (-1) is stored for pins that could not be part of a direct * - * chain conneciton. * - * * - * Stores the pointers to the two 2D arrays in the addresses passed in. * - * * - * The two arrays are freed by the caller(s). */ - - int iblk_pin, idirect, num_type_pins; - int **temp_idirect_from_blk_pin, **temp_direct_type_from_blk_pin; - - char to_pb_type_name[MAX_STRING_LEN + 1], to_port_name[MAX_STRING_LEN + 1], - from_pb_type_name[MAX_STRING_LEN + 1], from_port_name[MAX_STRING_LEN + 1]; - int to_start_pin_index = -1, to_end_pin_index = -1; - int from_start_pin_index = -1, from_end_pin_index = -1; - auto& device_ctx = g_vpr_ctx.device(); - - /* Allocate and initialize the values to OPEN (-1). */ - temp_idirect_from_blk_pin = new int*[device_ctx.physical_tile_types.size()]; - temp_direct_type_from_blk_pin = new int*[device_ctx.physical_tile_types.size()]; - for (const auto& type : device_ctx.physical_tile_types) { - if (is_empty_type(&type)) continue; - - int itype = type.index; - num_type_pins = type.num_pins; - - temp_idirect_from_blk_pin[itype] = new int[num_type_pins]; - temp_direct_type_from_blk_pin[itype] = new int[num_type_pins]; + if (end_pin_index < start_pin_index) { + VTR_LOG_ERROR( + "[LINE %d] Invalid from_pin - %s, the end_pin_index in " + "[end_pin_index:start_pin_index] should not be less than start_pin_index.\n", + line, src_string); + exit(1); + } - /* Initialize values to OPEN */ - for (iblk_pin = 0; iblk_pin < num_type_pins; iblk_pin++) { - temp_idirect_from_blk_pin[itype][iblk_pin] = OPEN; - temp_direct_type_from_blk_pin[itype][iblk_pin] = OPEN; + return {start_pin_index, end_pin_index, pb_type_name, port_name}; + } else { + VTR_LOG_ERROR( + "[LINE %d] Invalid pin - %s, name should be in the format " + "\"pb_type_name\".\"port_name\" or \"pb_type_name\".\"port_name[end_pin_index:start_pin_index]\". " + "The end_pin_index and start_pin_index can be the same.\n", + line, src_string); + exit(1); } } - - /* Load the values */ - // Go through directs and find pins with possible direct connections - for (idirect = 0; idirect < num_directs; idirect++) { - // Parse out the pb_type and port name, possibly pin_indices from from_pin - parse_direct_pin_name(directs[idirect].from_pin, directs[idirect].line, - &from_end_pin_index, &from_start_pin_index, from_pb_type_name, from_port_name); - - // Parse out the pb_type and port name, possibly pin_indices from to_pin - parse_direct_pin_name(directs[idirect].to_pin, directs[idirect].line, - &to_end_pin_index, &to_start_pin_index, to_pb_type_name, to_port_name); - - /* Now I have all the data that I need, I could go through all the block pins * - * in all the blocks to find all the pins that could have possible direct * - * connections. Mark all down all those pins with the idirect the pins belong * - * to and whether it is a source or a sink of the direct connection. */ - - // Find blocks with the same name as from_pb_type_name and from_port_name - mark_direct_of_ports(idirect, SOURCE, from_pb_type_name, from_port_name, - from_end_pin_index, from_start_pin_index, directs[idirect].from_pin, - directs[idirect].line, - temp_idirect_from_blk_pin, temp_direct_type_from_blk_pin); - - // Then, find blocks with the same name as to_pb_type_name and from_port_name - mark_direct_of_ports(idirect, SINK, to_pb_type_name, to_port_name, - to_end_pin_index, to_start_pin_index, directs[idirect].to_pin, - directs[idirect].line, - temp_idirect_from_blk_pin, temp_direct_type_from_blk_pin); - - } // Finish going through all the directs - - /* Returns the pointer to the 2D arrays by reference. */ - *idirect_from_blk_pin = temp_idirect_from_blk_pin; - *direct_type_from_blk_pin = temp_direct_type_from_blk_pin; } /* @@ -2083,17 +1800,17 @@ int get_atom_pin_class_num(const AtomPinId atom_pin_id) { return get_class_num_from_pin_physical_num(physical_type, pin_physical_num); } -t_physical_tile_port find_tile_port_by_name(t_physical_tile_type_ptr type, const char* port_name) { - for (const auto& sub_tile : type->sub_tiles) { - for (const auto& port : sub_tile.ports) { - if (0 == strcmp(port.name, port_name)) { +t_physical_tile_port find_tile_port_by_name(t_physical_tile_type_ptr type, std::string_view port_name) { + for (const t_sub_tile& sub_tile : type->sub_tiles) { + for (const t_physical_tile_port& port : sub_tile.ports) { + if (port_name == port.name) { return port; } } } // Port has not been found, throw an error. - VPR_THROW(VPR_ERROR_ARCH, "Unable to find port %s (on block %s).\n", port_name, type->name); + VPR_THROW(VPR_ERROR_ARCH, "Unable to find port %s (on block %s).\n", port_name, type->name.c_str()); } void pretty_print_uint(const char* prefix, size_t value, int num_digits, int scientific_precision) { @@ -2325,7 +2042,7 @@ std::vector get_cluster_netlist_intra_tile_pins_at_loc(const int layer, const auto& cluster_pin_chains = pin_chains_num[cluster_blk_id]; const auto& cluster_chain_sinks = pin_chains[cluster_blk_id].chain_sink; const auto& cluster_pin_chain_idx = pin_chains[cluster_blk_id].pin_chain_idx; - // remove common elements betweeen cluster_pin_chains. + // remove common elements between cluster_pin_chains. for (auto pin : cluster_internal_pins) { auto it = cluster_pin_chains.find(pin); if (it == cluster_pin_chains.end()) { @@ -2437,3 +2154,36 @@ float get_min_cross_layer_delay() { return min_delay; } + +PortPinToBlockPinConverter::PortPinToBlockPinConverter() { + const auto& device_ctx = g_vpr_ctx.device(); + const auto& types = device_ctx.physical_tile_types; + + // Resize and initialize the values to OPEN (-1). + size_t num_types = types.size(); + blk_pin_from_port_pin_.resize(num_types); + + for (size_t itype = 1; itype < num_types; itype++) { + int blk_pin_count = 0; + auto& type = types[itype]; + size_t num_sub_tiles = type.sub_tiles.size(); + blk_pin_from_port_pin_[itype].resize(num_sub_tiles); + for (size_t isub_tile = 0; isub_tile < num_sub_tiles; isub_tile++) { + size_t num_ports = type.sub_tiles[isub_tile].ports.size(); + blk_pin_from_port_pin_[itype][isub_tile].resize(num_ports); + for (size_t iport = 0; iport < num_ports; iport++) { + int num_pins = type.sub_tiles[isub_tile].ports[iport].num_pins; + for (int ipin = 0; ipin < num_pins; ipin++) { + blk_pin_from_port_pin_[itype][isub_tile][iport].push_back(blk_pin_count); + blk_pin_count++; + } + } + } + } +} + +int PortPinToBlockPinConverter::get_blk_pin_from_port_pin(int blk_type_index, int sub_tile, int port, int port_pin) const { + // Return the port and port_pin for the pin. + int blk_pin = blk_pin_from_port_pin_[blk_type_index][sub_tile][port][port_pin]; + return blk_pin; +} \ No newline at end of file diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index 9f08dcc0d2b..1091d79e000 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -135,7 +135,7 @@ std::string rr_node_arch_name(RRNodeId inode, bool is_flat); * Intra-Logic Block Utility Functions **************************************************************/ -//Class for looking up pb graph pins from block pin indicies +//Class for looking up pb graph pins from block pin indices class IntraLbPbPinLookup { public: IntraLbPbPinLookup(const std::vector& block_types); @@ -216,9 +216,12 @@ t_pin_range get_pb_pins(t_physical_tile_type_ptr physical_type, float compute_primitive_base_cost(const t_pb_graph_node* primitive); int num_ext_inputs_atom_block(AtomBlockId blk_id); -void alloc_and_load_idirect_from_blk_pin(t_direct_inf* directs, int num_directs, int*** idirect_from_blk_pin, int*** direct_type_from_blk_pin); - -void parse_direct_pin_name(char* src_string, int line, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); +/** + * @brief Parses out the pb_type_name and port_name from the direct passed in. + * If the start_pin_index and end_pin_index is specified, parse them too. * + * @return (start_pin_index, end_pin_index, pb_type_name, port_name) + */ +std::tuple parse_direct_pin_name(std::string_view src_string, int line); void free_pb_stats(t_pb* pb); void free_pb(t_pb* pb); @@ -309,11 +312,44 @@ void apply_route_constraints(const UserRouteConstraints& constraint); /** * @brief Iterate over all inter-layer switch types and return the minimum delay of it. * useful four router lookahead to to have some estimate of the cost of crossing a layer - * @param arch_switch_inf - * @param segment_inf - * @param wire_to_ipin_arch_sw_id * @return */ float get_min_cross_layer_delay(); +/** + * @class PortPinToBlockPinConverter + * @brief Maps the block pins indices for all block types to the corresponding port indices and port_pin indices. + * + * @details This is necessary since there are different netlist conventions - in the cluster level, + * ports and port pins are used while in the post-pack level, block pins are used. + */ +class PortPinToBlockPinConverter { + public: + /** + * @brief Allocates and loads blk_pin_from_port_pin_ array. + */ + PortPinToBlockPinConverter(); + + /** + * @brief Converts port and port pin indices of a specific block type to block pin index. + * + * @details The reason block type is used instead of blocks is to save memory. + * + * @param blk_type_index The block type index. + * @param sub_tile The subtile index within the specified block type. + * @param port The port number whose block pin number is desired. + * @param port_pin The port pin number in the specified port whose block pin number is desired. + * @return int The block pin index corresponding to the given port and port pin numbers. + */ + int get_blk_pin_from_port_pin(int blk_type_index, int sub_tile, int port, int port_pin) const; + + private: + /** + * @brief This array allows us to quickly find what block pin a port pin corresponds to. + * @details A 4D array that should be indexed as following: + * [0...device_ctx.physical_tile_types.size()-1][0..num_sub_tiles][0...num_ports-1][0...num_port_pins-1] + */ + std::vector>>> blk_pin_from_port_pin_; +}; + #endif diff --git a/vpr/test/test_connection_router.cpp b/vpr/test/test_connection_router.cpp index 568b2b175f7..a106ad80a80 100644 --- a/vpr/test/test_connection_router.cpp +++ b/vpr/test/test_connection_router.cpp @@ -164,8 +164,7 @@ TEST_CASE("connection_router", "[vpr]") { vpr_setup.RouterOpts, &vpr_setup.RoutingArch, vpr_setup.Segments, - arch.Directs, - arch.num_directs, + arch.directs, router_opts.flat_routing); // Find a source and sink to route diff --git a/vpr/test/test_interchange_device.cpp b/vpr/test/test_interchange_device.cpp index 276decccf13..6ab763ec5d8 100644 --- a/vpr/test/test_interchange_device.cpp +++ b/vpr/test/test_interchange_device.cpp @@ -94,10 +94,10 @@ TEST_CASE("read_interchange_luts", "[vpr]") { REQUIRE(lut_element.lut_bels.size() == 1); for (auto lut_bel : lut_element.lut_bels) { - CHECK(std::find(lut_bels.begin(), lut_bels.end(), lut_bel.name) != lut_bels.end()); + CHECK(lut_bels.find(lut_bel.name) != lut_bels.end()); REQUIRE(lut_bel.output_pin == std::string("O")); - for (auto lut_pin : lut_bel.input_pins) - CHECK(std::find(lut_bel_pins.begin(), lut_bel_pins.end(), lut_pin) != lut_bel_pins.end()); + for (const std::string &lut_pin : lut_bel.input_pins) + CHECK(lut_bel_pins.find(lut_pin) != lut_bel_pins.end()); } } } @@ -113,8 +113,8 @@ TEST_CASE("read_interchange_tiles", "[vpr]") { std::unordered_set ptypes = {"EMPTY", "IOB", "IB", "OB", "CLB", "constant_block"}; // Check that there are exactly the expected models - for (auto ptype : physical_tile_types) { - std::string name = ptype.name; + for (const t_physical_tile_type& ptype : physical_tile_types) { + const std::string& name = ptype.name; REQUIRE(ptypes.find(name) != ptypes.end()); ptypes.erase(name); diff --git a/vpr/test/test_vpr.cpp b/vpr/test/test_vpr.cpp index 0e92311b5c2..d96c0389a5d 100644 --- a/vpr/test/test_vpr.cpp +++ b/vpr/test/test_vpr.cpp @@ -62,8 +62,8 @@ TEST_CASE("read_arch_metadata", "[vpr]") { bool found_mode = false; bool found_direct = false; - for (const auto& type : logical_block_types) { - if (strcmp("io", type.name) == 0) { + for (const t_logical_block_type& type : logical_block_types) { + if (type.name == "io") { found_pb_type = true; REQUIRE(type.pb_type != nullptr); REQUIRE(type.pb_type->meta.has(pb_type_type)); diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt index 9077f9965e9..51984390d53 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 11.99 vpr 255.45 MiB 0.11 36912 -1 -1 1 0.05 -1 -1 34700 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261584 6 1 13 14 2 8 9 4 4 16 clb auto 101.0 MiB 0.11 13 244.4 MiB 0.04 0.00 0.875884 -3.21653 -0.875884 0.545 0.47 0.000264546 0.000241337 0.00754986 0.00454282 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136677 0.00891098 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00722654 0.00593545 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 12.96 vpr 261.56 MiB 0.15 45980 -1 -1 1 0.06 -1 -1 34932 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 267836 3 1 25 26 2 8 6 4 4 16 clb auto 106.4 MiB 0.87 17 249.9 MiB 0.03 0.00 0.571 -8.64803 -0.571 0.557849 0.47 0.000543454 0.000488368 0.00346482 0.00253954 20 19 1 107788 107788 10441.3 652.579 0.67 0.0113116 0.00855232 742 1670 -1 15 1 6 6 63 36 0 0 63 36 6 6 0 0 9 6 0 0 9 9 0 0 6 6 0 0 18 3 0 0 15 6 0 0 6 0 0 0 0 0 6 0 0 0.571 0.557849 -8.82275 -0.571 0 0 13748.8 859.301 0.01 0.04 0.17 -1 -1 0.01 0.00501901 0.00409753 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 11.88 vpr 254.22 MiB 0.15 35980 -1 -1 1 0.00 -1 -1 32420 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260320 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0.00 0.544641 -1.83465 -0.544641 nan 0.47 0.000504445 0.000240584 0.00477542 0.00228264 20 21 1 107788 107788 10441.3 652.579 0.64 0.00804976 0.00416003 742 1670 -1 19 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00215701 0.00121245 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 11.99 vpr 255.45 MiB 0.11 36912 -1 -1 1 0.05 -1 -1 34700 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261584 6 1 13 14 2 8 9 4 4 16 clb auto 101.0 MiB 0.11 13 244.4 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000264546 0.000241337 0.00754986 0.00454282 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136677 0.00891098 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00722654 0.00593545 +k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 12.96 vpr 261.56 MiB 0.15 45980 -1 -1 1 0.06 -1 -1 34932 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 267836 3 1 25 26 2 8 6 4 4 16 clb auto 106.4 MiB 0.87 17 249.9 MiB 0.03 0 0.571 -8.64803 -0.571 0.557849 0.47 0.000543454 0.000488368 0.00346482 0.00253954 20 19 1 107788 107788 10441.3 652.579 0.67 0.0113116 0.00855232 742 1670 -1 27 1 6 6 63 36 0 0 63 36 6 6 0 0 9 6 0 0 9 9 0 0 6 6 0 0 18 3 0 0 15 6 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.82275 -0.865 0 0 13748.8 859.301 0.01 0.04 0.17 -1 -1 0.01 0.00501901 0.00409753 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 11.88 vpr 254.22 MiB 0.15 35980 -1 -1 1 0 -1 -1 32420 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260320 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0 0.544641 -1.83465 -0.544641 nan 0.47 0.000504445 0.000240584 0.00477542 0.00228264 20 21 1 107788 107788 10441.3 652.579 0.64 0.00804976 0.00416003 742 1670 -1 19 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00215701 0.00121245 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt index d044003b867..21dd6c7c148 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.30 vpr 255.23 MiB 0.10 37032 -1 -1 1 0.05 -1 -1 34904 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261360 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.1 MiB 0.04 0.00 0.875884 -3.21653 -0.875884 0.545 0.47 0.000265884 0.000243239 0.00748601 0.00452291 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136031 0.00885329 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00736034 0.00605214 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 13.17 vpr 257.73 MiB 0.11 45924 -1 -1 1 0.05 -1 -1 34916 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 263920 3 1 23 24 2 8 6 4 4 16 clb auto 102.9 MiB 0.41 17 246.4 MiB 0.03 0.00 0.571 -8.10303 -0.571 0.557849 0.47 0.000537036 0.000469297 0.00334227 0.00240417 20 19 1 107788 107788 10441.3 652.579 0.66 0.0107944 0.00802791 742 1670 -1 16 1 6 6 65 37 0 0 65 37 6 6 0 0 8 6 0 0 8 8 0 0 6 6 0 0 16 4 0 0 21 7 0 0 6 0 0 0 0 0 6 0 0 0.571 0.557849 -8.27775 -0.571 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00471694 0.00381784 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.06 vpr 254.61 MiB 0.11 36040 -1 -1 1 0.01 -1 -1 32628 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260720 6 2 10 12 2 8 10 4 4 16 clb auto 100.6 MiB 0.06 13 243.8 MiB 0.02 0.00 0.544641 -1.98049 -0.544641 nan 0.47 0.000492001 0.000225939 0.00246091 0.00127477 20 20 1 107788 107788 10441.3 652.579 0.64 0.00559049 0.00306652 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00247934 0.00153705 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.3 vpr 255.23 MiB 0.1 37032 -1 -1 1 0.05 -1 -1 34904 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261360 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.1 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000265884 0.000243239 0.00748601 0.00452291 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136031 0.00885329 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00736034 0.00605214 +k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 13.17 vpr 257.73 MiB 0.11 45924 -1 -1 1 0.05 -1 -1 34916 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 263920 3 1 23 24 2 8 6 4 4 16 clb auto 102.9 MiB 0.41 17 246.4 MiB 0.03 0 0.571 -8.10303 -0.571 0.557849 0.47 0.000537036 0.000469297 0.00334227 0.00240417 20 19 1 107788 107788 10441.3 652.579 0.66 0.0107944 0.00802791 742 1670 -1 27 1 6 6 65 37 0 0 65 37 6 6 0 0 8 6 0 0 8 8 0 0 6 6 0 0 16 4 0 0 21 7 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.27775 -0.865 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00471694 0.00381784 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.06 vpr 254.61 MiB 0.11 36040 -1 -1 1 0.01 -1 -1 32628 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260720 6 2 10 12 2 8 10 4 4 16 clb auto 100.6 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000492001 0.000225939 0.00246091 0.00127477 20 20 1 107788 107788 10441.3 652.579 0.64 0.00559049 0.00306652 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00247934 0.00153705 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt index ac8b192b56d..f90ef2264d9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/once/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.22 vpr 254.93 MiB 0.10 37000 -1 -1 1 0.05 -1 -1 34808 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261052 6 1 13 14 2 8 9 4 4 16 clb auto 100.7 MiB 0.11 13 244.1 MiB 0.04 0.00 0.875884 -3.21653 -0.875884 0.545 0.47 0.000263443 0.000240838 0.00748415 0.00450484 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136082 0.00886525 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00739705 0.00603502 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 14.79 vpr 261.44 MiB 0.12 46076 -1 -1 1 0.05 -1 -1 34892 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 267712 3 1 25 26 2 8 6 4 4 16 clb auto 106.3 MiB 1.00 17 250.0 MiB 0.04 0.00 0.571 -8.64803 -0.571 0.557849 0.53 0.000560438 0.000505834 0.00360459 0.00262507 20 19 1 107788 107788 10441.3 652.579 0.76 0.0119539 0.00893362 742 1670 -1 15 1 6 6 63 36 0 0 63 36 6 6 0 0 9 6 0 0 9 9 0 0 6 6 0 0 18 3 0 0 15 6 0 0 6 0 0 0 0 0 6 0 0 0.571 0.557849 -8.82275 -0.571 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00502268 0.00406987 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.05 vpr 254.23 MiB 0.11 35864 -1 -1 1 0.01 -1 -1 32648 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260328 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0.00 0.544641 -1.83465 -0.544641 nan 0.47 0.000489919 0.000226814 0.00463432 0.00218307 20 21 1 107788 107788 10441.3 652.579 0.64 0.00773058 0.00396899 742 1670 -1 19 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00224126 0.00124363 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.22 vpr 254.93 MiB 0.1 37000 -1 -1 1 0.05 -1 -1 34808 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261052 6 1 13 14 2 8 9 4 4 16 clb auto 100.7 MiB 0.11 13 244.1 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000263443 0.000240838 0.00748415 0.00450484 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136082 0.00886525 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00739705 0.00603502 +k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 14.79 vpr 261.44 MiB 0.12 46076 -1 -1 1 0.05 -1 -1 34892 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 267712 3 1 25 26 2 8 6 4 4 16 clb auto 106.3 MiB 1 17 250.0 MiB 0.04 0 0.571 -8.64803 -0.571 0.557849 0.53 0.000560438 0.000505834 0.00360459 0.00262507 20 19 1 107788 107788 10441.3 652.579 0.76 0.0119539 0.00893362 742 1670 -1 27 1 6 6 63 36 0 0 63 36 6 6 0 0 9 6 0 0 9 9 0 0 6 6 0 0 18 3 0 0 15 6 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.82275 -0.865 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00502268 0.00406987 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.05 vpr 254.23 MiB 0.11 35864 -1 -1 1 0.01 -1 -1 32648 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260328 6 2 10 12 2 8 10 4 4 16 clb auto 100.4 MiB 0.06 12 243.6 MiB 0.03 0 0.544641 -1.83465 -0.544641 nan 0.47 0.000489919 0.000226814 0.00463432 0.00218307 20 21 1 107788 107788 10441.3 652.579 0.64 0.00773058 0.00396899 742 1670 -1 19 1 6 6 148 96 0 0 148 96 6 6 0 0 18 16 0 0 18 18 0 0 6 6 0 0 53 27 0 0 47 23 0 0 6 0 0 0 0 0 6 0 0 0.81248 nan -2.54321 -0.81248 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00224126 0.00124363 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt index 97a8b4c5da1..9ab3c9f38ba 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.42 vpr 255.39 MiB 0.11 37100 -1 -1 1 0.05 -1 -1 34836 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261516 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.2 MiB 0.04 0.00 0.875884 -3.21653 -0.875884 0.545 0.47 0.000271285 0.00024783 0.00755294 0.00457495 20 15 7 107788 107788 10441.3 652.579 0.66 0.0137643 0.00901687 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00730106 0.00594924 -k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 13.23 vpr 258.31 MiB 0.12 45996 -1 -1 1 0.06 -1 -1 34908 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 264512 3 1 23 24 2 8 6 4 4 16 clb auto 103.2 MiB 0.41 17 246.6 MiB 0.03 0.00 0.571 -8.10303 -0.571 0.557849 0.47 0.00052053 0.00046898 0.00343969 0.00250359 20 19 1 107788 107788 10441.3 652.579 0.67 0.0108999 0.00814426 742 1670 -1 16 1 6 6 65 37 0 0 65 37 6 6 0 0 8 6 0 0 8 8 0 0 6 6 0 0 16 4 0 0 21 7 0 0 6 0 0 0 0 0 6 0 0 0.571 0.557849 -8.27775 -0.571 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00471607 0.00381108 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.08 vpr 254.57 MiB 0.11 35828 -1 -1 1 0.00 -1 -1 32584 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21T14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260676 6 2 10 12 2 8 10 4 4 16 clb auto 100.7 MiB 0.06 13 243.8 MiB 0.02 0.00 0.544641 -1.98049 -0.544641 nan 0.47 0.000490217 0.000225774 0.00246486 0.00125809 20 20 1 107788 107788 10441.3 652.579 0.64 0.00562004 0.00308942 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00259444 0.00157979 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.42 vpr 255.39 MiB 0.11 37100 -1 -1 1 0.05 -1 -1 34836 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261516 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.2 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000271285 0.00024783 0.00755294 0.00457495 20 15 7 107788 107788 10441.3 652.579 0.66 0.0137643 0.00901687 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00730106 0.00594924 +k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 13.23 vpr 258.31 MiB 0.12 45996 -1 -1 1 0.06 -1 -1 34908 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 264512 3 1 23 24 2 8 6 4 4 16 clb auto 103.2 MiB 0.41 17 246.6 MiB 0.03 0 0.865 -8.10303 -0.865 0.557849 0.47 0.00052053 0.00046898 0.00343969 0.00250359 20 19 1 107788 107788 10441.3 652.579 0.67 0.0108999 0.00814426 742 1670 -1 27 1 6 6 65 37 0 0 65 37 6 6 0 0 8 6 0 0 8 8 0 0 6 6 0 0 16 4 0 0 21 7 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.27775 -0.865 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00471607 0.00381108 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.08 vpr 254.57 MiB 0.11 35828 -1 -1 1 0 -1 -1 32584 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260676 6 2 10 12 2 8 10 4 4 16 clb auto 100.7 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000490217 0.000225774 0.00246486 0.00125809 20 20 1 107788 107788 10441.3 652.579 0.64 0.00562004 0.00308942 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00259444 0.00157979 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt index 5d75a350e6a..36a72a857e2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/open_cores_frac/config/golden_results.txt @@ -1,11 +1,11 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_2ripple_N8_22nm.xml Md5Core.v common 1523.19 vpr 631.18 MiB -1 -1 18.63 222000 1 4.87 -1 -1 148456 -1 -1 2775 641 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 646324 641 128 55563 47815 1 18444 3544 63 63 3969 clb auto 328.6 MiB 1069.74 193393 631.2 MiB 130.02 0.98 5.9413 -22687.8 -5.9413 5.9413 65.61 0.0809681 0.0706031 11.9053 9.75852 96 273476 42 1.26034e+08 4.01707e+07 2.39085e+07 6023.80 167.30 36.978 31.0767 245577 21 87227 109942 13221766 2204697 5.72041 5.72041 -23256.4 -5.72041 0 0 2.98904e+07 7530.95 13.57 4.92 2.43619 2.12655 20917 2048 -1 -1 -1 -1 - k6_frac_2ripple_N8_22nm.xml cordic.v common 9.96 vpr 63.02 MiB -1 -1 0.66 29152 4 0.23 -1 -1 36304 -1 -1 30 54 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64536 54 51 503 502 1 316 135 9 9 81 clb auto 25.0 MiB 5.50 1835 63.0 MiB 0.11 0.00 3.38302 -182.201 -3.38302 3.38302 0.20 0.000695677 0.000586605 0.0322825 0.0278063 58 4136 29 1.45065e+06 434271 237595. 2933.27 1.73 0.308508 0.273009 3572 21 2232 8477 471204 108822 3.80526 3.80526 -207.795 -3.80526 0 0 298762. 3688.42 0.10 0.18 0.0633453 0.0579356 224 279 -1 -1 -1 -1 - k6_frac_2uripple_N8_22nm.xml Md5Core.v common 1265.13 vpr 621.28 MiB -1 -1 17.42 221456 1 5.26 -1 -1 148504 -1 -1 2762 641 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 636192 641 128 55563 47815 1 18442 3531 63 63 3969 clb auto 313.9 MiB 686.98 204438 621.3 MiB 141.78 1.17 6.16151 -21971.3 -6.16151 6.16151 61.31 0.0783723 0.0681549 13.0301 10.9186 108 271142 31 1.26708e+08 4.06454e+07 2.65753e+07 6695.71 264.61 44.9129 38.1642 249873 22 80436 103024 12671777 2028676 5.58756 5.58756 -22363.9 -5.58756 0 0 3.32553e+07 8378.77 24.17 8.26 4.54819 3.99514 20888 2048 -1 -1 -1 -1 - k6_frac_2uripple_N8_22nm.xml cordic.v common 4.56 vpr 63.20 MiB -1 -1 0.63 29356 4 0.21 -1 -1 36376 -1 -1 30 54 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64712 54 51 503 502 1 315 135 9 9 81 clb auto 24.9 MiB 0.36 1812 63.2 MiB 0.12 0.00 3.47051 -182.16 -3.47051 3.47051 0.19 0.000863781 0.00073654 0.0311627 0.0268328 62 3866 25 1.45905e+06 441471 249781. 3083.72 1.65 0.274791 0.244683 3265 17 1747 6015 305690 72755 3.6524 3.6524 -199.446 -3.6524 0 0 310465. 3832.90 0.10 0.12 0.0489577 0.0451412 224 279 -1 -1 -1 -1 - k6_frac_N8_22nm.xml Md5Core.v common 1749.99 vpr 704.14 MiB -1 -1 27.88 324380 27 23.05 -1 -1 141788 -1 -1 3326 641 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 721040 641 128 52026 52154 1 23165 4095 69 69 4761 clb auto 316.2 MiB 1268.87 266482 704.1 MiB 104.59 0.84 12.4496 -34653.2 -12.4496 12.4496 76.89 0.0946227 0.0832311 13.6407 11.3985 92 396797 37 1.50071e+08 4.48079e+07 2.78049e+07 5840.14 167.00 41.7559 35.6704 357477 17 107605 226700 17799142 3139273 13.452 13.452 -36283.6 -13.452 0 0 3.46244e+07 7272.51 15.17 6.70 3.04451 2.73162 24368 14777 -1 -1 -1 -1 - k6_frac_N8_22nm.xml cordic.v common 5.06 vpr 62.00 MiB -1 -1 0.71 29652 11 0.37 -1 -1 36780 -1 -1 34 54 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 63488 54 51 465 516 1 319 139 9 9 81 clb auto 23.9 MiB 0.29 2221 62.0 MiB 0.10 0.00 4.82297 -206.45 -4.82297 4.82297 0.20 0.000763492 0.000640713 0.0264532 0.0228199 64 4789 36 1.41552e+06 458048 257695. 3181.41 1.84 0.275023 0.239823 4292 18 2107 7857 464250 107626 5.2135 5.2135 -226.808 -5.2135 0 0 325495. 4018.46 0.11 0.17 0.050087 0.0457904 252 355 -1 -1 -1 -1 - k6_frac_ripple_N8_22nm.xml Md5Core.v common 1406.15 vpr 707.01 MiB -1 -1 18.04 222180 1 5.15 -1 -1 148440 -1 -1 3347 641 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 723976 641 128 55563 47815 1 19493 4116 69 69 4761 clb auto 302.2 MiB 856.04 217390 707.0 MiB 199.59 1.01 6.16544 -21821.3 -6.16544 6.16544 79.96 0.077383 0.0680123 11.7722 9.55336 76 294270 49 1.51752e+08 4.6769e+07 2.35334e+07 4942.95 160.40 46.1957 38.7675 272573 21 90703 122231 13046051 2355052 5.08527 5.08527 -21561.3 -5.08527 0 0 2.91431e+07 6121.21 21.90 8.21 4.45243 3.85285 25690 2048 -1 -1 -1 -1 - k6_frac_ripple_N8_22nm.xml cordic.v common 7.66 vpr 62.58 MiB -1 -1 0.66 29360 4 0.22 -1 -1 36420 -1 -1 33 54 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64080 54 51 503 502 1 316 138 9 9 81 clb auto 24.6 MiB 3.14 1899 62.6 MiB 0.13 0.00 3.99287 -190.736 -3.99287 3.99287 0.20 0.000738244 0.000630734 0.0339162 0.0295037 56 4210 41 1.43308e+06 461137 231774. 2861.41 1.86 0.324554 0.284283 3617 17 1789 6259 385816 96713 3.93871 3.93871 -208.933 -3.93871 0 0 286113. 3532.26 0.10 0.16 0.052109 0.047446 231 279 -1 -1 -1 -1 - k6_frac_uripple_N8_22nm.xml Md5Core.v common 1104.70 vpr 713.57 MiB -1 -1 18.08 221496 1 5.09 -1 -1 148440 -1 -1 3404 641 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 730692 641 128 55563 47815 1 19394 4173 70 70 4900 clb auto 294.0 MiB 423.49 231722 713.6 MiB 188.82 1.48 5.99996 -22437.7 -5.99996 5.99996 78.87 0.0799578 0.0697624 10.3611 8.57823 72 310319 40 1.56988e+08 4.79739e+07 2.32988e+07 4754.86 303.36 46.7544 39.8735 279469 16 75618 94941 10355908 1826905 5.73514 5.73514 -22572.7 -5.73514 0 0 2.91457e+07 5948.09 21.87 6.40 3.31162 2.89997 25825 2048 -1 -1 -1 -1 - k6_frac_uripple_N8_22nm.xml cordic.v common 5.36 vpr 62.15 MiB -1 -1 0.67 29300 4 0.21 -1 -1 36380 -1 -1 34 54 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 63640 54 51 503 502 1 311 139 9 9 81 clb auto 24.2 MiB 0.68 2055 62.1 MiB 0.09 0.00 3.89866 -189.86 -3.89866 3.89866 0.20 0.000727644 0.000622662 0.0231685 0.0201305 56 4591 48 1.43728e+06 479191 231774. 2861.41 2.00 0.33035 0.292052 4078 20 2023 7302 460657 112161 3.8556 3.8556 -212.37 -3.8556 0 0 286113. 3532.26 0.10 0.18 0.0547189 0.0497039 248 279 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_2ripple_N8_22nm.xml Md5Core.v common 967.55 vpr 763.48 MiB -1 -1 21.42 218260 1 3.55 -1 -1 145252 -1 -1 2765 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 781804 641 128 55563 47815 1 18442 3534 63 63 3969 clb auto 281.1 MiB 538.53 193346 3958863 1550116 2317083 91664 724.9 MiB 91.43 0.78 7.15591 -24783.9 -7.15591 7.15591 35.35 0.069551 0.0596698 11.0083 9.1981 -1 -1 -1 -1 100 265108 28 1.26034e+08 4.00259e+07 2.46425e+07 6208.74 216.16 44.9729 37.3415 555724 6871176 -1 241564 19 87044 109997 12783883 2167446 5.78182 5.78182 -22734.5 -5.78182 0 0 3.14324e+07 7919.47 11.63 6.19 5.58 -1 -1 11.63 3.3327 2.85451 20869 2050 -1 -1 -1 -1 + k6_frac_2ripple_N8_22nm.xml cordic.v common 8.95 vpr 64.59 MiB -1 -1 0.89 26192 4 0.16 -1 -1 33384 -1 -1 31 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66140 54 51 503 502 1 316 136 9 9 81 clb auto 25.8 MiB 3.67 1981 10606 1997 7706 903 64.6 MiB 0.14 0.01 4.17161 -228.336 -4.17161 4.17161 0.15 0.00186072 0.00171427 0.0514286 0.0475525 -1 -1 -1 -1 64 3792 30 1.45065e+06 448746 257695. 3181.41 2.54 0.574843 0.497531 8184 62525 -1 3344 18 1920 7095 335845 82840 3.72075 3.72075 -206.153 -3.72075 0 0 325495. 4018.46 0.07 0.13 0.06 -1 -1 0.07 0.0566057 0.0503365 223 281 -1 -1 -1 -1 + k6_frac_2uripple_N8_22nm.xml Md5Core.v common 1559.25 vpr 722.84 MiB -1 -1 21.49 218496 1 3.59 -1 -1 145220 -1 -1 2755 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 740192 641 128 55563 47815 1 18420 3524 63 63 3969 clb auto 275.9 MiB 401.16 189162 3756364 1484461 2184211 87692 722.8 MiB 82.41 0.75 6.93106 -24149.1 -6.93106 6.93106 33.22 0.0717932 0.0614288 10.2573 8.56904 -1 -1 -1 -1 96 272845 49 1.26708e+08 4.05424e+07 2.39085e+07 6023.80 957.73 60.3389 49.6676 543820 6559920 -1 240871 21 88185 112391 12448748 2170100 5.42465 5.42465 -22151.3 -5.42465 0 0 2.98904e+07 7530.95 11.16 6.44 5.45 -1 -1 11.16 3.58618 3.05396 20824 2050 -1 -1 -1 -1 + k6_frac_2uripple_N8_22nm.xml cordic.v common 4.56 vpr 64.47 MiB -1 -1 0.86 25908 4 0.16 -1 -1 33380 -1 -1 31 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66020 54 51 503 502 1 317 136 9 9 81 clb auto 25.8 MiB 0.24 1985 6767 1049 5344 374 64.5 MiB 0.10 0.00 4.17356 -220.898 -4.17356 4.17356 0.15 0.00138081 0.00127221 0.0330425 0.0306558 -1 -1 -1 -1 60 3856 40 1.45905e+06 456186 242836. 2997.97 1.76 0.429337 0.371533 7944 58396 -1 3350 17 1679 5954 301000 77818 3.8968 3.8968 -205.243 -3.8968 0 0 304930. 3764.57 0.07 0.12 0.06 -1 -1 0.07 0.0544767 0.0485746 223 281 -1 -1 -1 -1 + k6_frac_N8_22nm.xml Md5Core.v common 1120.51 vpr 806.71 MiB -1 -1 35.59 328120 27 14.77 -1 -1 138400 -1 -1 3317 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 826068 641 128 52026 52154 1 23512 4086 69 69 4761 clb auto 272.8 MiB 754.36 261133 4150890 1586658 2510234 53998 806.7 MiB 66.92 0.57 15.1822 -39318.8 -15.1822 15.1822 40.15 0.0882437 0.0769439 12.042 10.1836 -1 -1 -1 -1 86 398717 44 1.50071e+08 4.46866e+07 2.62257e+07 5508.44 135.32 40.4871 34.0228 609466 7129297 -1 363314 18 111266 235135 19285517 3561010 13.209 13.209 -36299.7 -13.209 0 0 3.28825e+07 6906.63 13.30 9.39 5.66 -1 -1 13.30 4.36645 3.79962 24398 14777 -1 -1 -1 -1 + k6_frac_N8_22nm.xml cordic.v common 5.30 vpr 64.01 MiB -1 -1 0.90 26384 11 0.25 -1 -1 33576 -1 -1 32 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65548 54 51 461 512 1 320 137 9 9 81 clb auto 24.8 MiB 0.23 2288 7197 1051 5690 456 64.0 MiB 0.10 0.00 6.24973 -250.56 -6.24973 6.24973 0.15 0.00144607 0.00132918 0.0370165 0.0342281 -1 -1 -1 -1 68 4737 28 1.41552e+06 431104 273575. 3377.47 2.36 0.459262 0.397505 8204 65576 -1 4227 16 2032 7777 430507 103502 5.511 5.511 -231.556 -5.511 0 0 341260. 4213.08 0.07 0.09 0.04 -1 -1 0.07 0.0317702 0.0289934 248 351 -1 -1 -1 -1 + k6_frac_ripple_N8_22nm.xml Md5Core.v common 1137.63 vpr 796.55 MiB -1 -1 21.77 218484 1 3.71 -1 -1 145332 -1 -1 3347 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 815668 641 128 55563 47815 1 19485 4116 69 69 4761 clb auto 265.0 MiB 674.41 209187 4719112 1762947 2769356 186809 796.6 MiB 133.07 1.12 7.50454 -24350.9 -7.50454 7.50454 41.02 0.0732288 0.0593247 10.5586 8.73373 -1 -1 -1 -1 78 280465 38 1.51752e+08 4.6769e+07 2.40314e+07 5047.55 201.27 45.7702 37.9151 599066 6522637 -1 262949 17 86466 116965 11441653 2162489 4.92975 4.92975 -21271.4 -4.92975 0 0 3.01399e+07 6330.58 12.77 5.93 5.15 -1 -1 12.77 3.01721 2.57504 25690 2050 -1 -1 -1 -1 + k6_frac_ripple_N8_22nm.xml cordic.v common 6.89 vpr 64.07 MiB -1 -1 0.89 25656 4 0.16 -1 -1 33436 -1 -1 31 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65612 54 51 503 502 1 304 136 9 9 81 clb auto 25.2 MiB 2.05 1922 8163 1239 6107 817 64.1 MiB 0.12 0.01 4.46634 -227.611 -4.46634 4.46634 0.15 0.00138637 0.00127855 0.0380722 0.0352824 -1 -1 -1 -1 58 4010 35 1.43308e+06 433189 237595. 2933.27 2.17 0.473652 0.409252 7864 57025 -1 3504 19 1914 6815 355293 91574 4.00986 4.00986 -203.926 -4.00986 0 0 298762. 3688.42 0.06 0.14 0.06 -1 -1 0.06 0.0573607 0.0506837 231 281 -1 -1 -1 -1 + k6_frac_uripple_N8_22nm.xml Md5Core.v common 725.64 vpr 847.35 MiB -1 -1 21.61 218272 1 3.62 -1 -1 145224 -1 -1 3391 641 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 867688 641 128 55563 47815 1 19453 4160 70 70 4900 clb auto 257.6 MiB 242.61 229476 4786509 1811673 2839137 135699 847.4 MiB 144.98 1.15 8.45033 -26255.9 -8.45033 8.45033 44.55 0.0706407 0.0605663 9.85709 8.24084 -1 -1 -1 -1 74 309564 47 1.56988e+08 4.77907e+07 2.37944e+07 4855.99 205.74 40.3572 33.4092 603630 6360748 -1 281191 24 82458 102666 12068393 2210419 5.62486 5.62486 -22699.9 -5.62486 0 0 2.96071e+07 6042.26 11.42 6.73 5.01 -1 -1 11.42 3.76274 3.16053 25717 2050 -1 -1 -1 -1 + k6_frac_uripple_N8_22nm.xml cordic.v common 5.09 vpr 64.27 MiB -1 -1 0.90 25612 4 0.16 -1 -1 33360 -1 -1 33 54 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65812 54 51 503 502 1 307 138 9 9 81 clb auto 25.3 MiB 0.70 2035 12242 2410 8614 1218 64.3 MiB 0.15 0.00 4.64981 -235.444 -4.64981 4.64981 0.15 0.00138199 0.00127842 0.0546169 0.0504723 -1 -1 -1 -1 54 4324 35 1.43728e+06 465097 226270. 2793.45 1.66 0.427278 0.370182 7624 52756 -1 3604 19 1920 6934 318277 82324 3.81736 3.81736 -208.354 -3.81736 0 0 280165. 3458.82 0.06 0.13 0.05 -1 -1 0.06 0.0571091 0.0505347 247 281 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt index 763d12d7f69..f58fc23a7d9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_arch_list/config/golden_results.txt @@ -1,31 +1,31 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.64 vpr 65.49 MiB -1 -1 0.33 22284 3 0.10 -1 -1 36976 -1 54752 68 99 1 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 67064 99 130 344 474 1 226 298 12 12 144 clb auto 26.3 MiB 0.08 538 74923 23743 38186 12994 65.5 MiB 0.17 0.00 1.85836 -118.859 -1.85836 1.85836 0.33 0.000486505 0.000433551 0.0395107 0.0352707 -1 -1 -1 -1 48 1116 12 5.66058e+06 4.21279e+06 394078. 2736.65 0.75 0.150667 0.136701 13382 75762 -1 1110 10 412 647 31369 9620 1.90517 1.90517 -133.113 -1.90517 -1.14837 -0.298787 503207. 3494.49 0.14 0.03 0.08 -1 -1 0.14 0.0189767 0.0177968 0.01055 0.2565 0.08184 0.6617 -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 14.10 vpr 68.69 MiB -1 -1 0.56 26896 15 0.41 -1 -1 37556 -1 56848 39 162 0 5 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 70340 162 96 1009 950 1 711 302 16 16 256 mult_36 auto 29.5 MiB 0.29 5244 100490 36162 56323 8005 68.7 MiB 0.52 0.01 21.0218 -1540.44 -21.0218 21.0218 0.65 0.00138725 0.00120684 0.153804 0.135182 -1 -1 -1 -1 58 12364 47 1.21132e+07 4.08187e+06 904549. 3533.39 7.36 0.685377 0.618096 27012 180273 -1 9111 18 3141 6470 890891 255235 22.5995 22.5995 -1612.44 -22.5995 0 0 1.15318e+06 4504.63 0.34 0.25 0.17 -1 -1 0.34 0.0908667 0.0846981 0.007774 0.375 0.01842 0.6066 -k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 577.55 vpr 460.78 MiB -1 -1 81.29 357444 123 91.70 -1 -1 82560 -1 119320 1366 114 45 8 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 471836 114 102 21994 21904 1 11836 1635 50 50 2500 memory auto 156.0 MiB 21.09 163873 1060715 378314 659503 22898 460.8 MiB 28.93 0.27 80.0631 -51811.9 -80.0631 80.0631 23.51 0.0767172 0.0635745 6.83032 5.5929 -1 -1 -1 -1 98 248827 34 1.47946e+08 1.0145e+08 1.60641e+07 6425.63 241.77 26.1462 21.8548 348768 3430976 -1 220630 22 44335 165955 10546515 1857252 82.0537 82.0537 -63570.6 -82.0537 -54.234 -0.341744 2.03677e+07 8147.07 8.57 5.63 4.03 -1 -1 8.57 3.05733 2.68846 0.08245 0.4398 0.01125 0.549 -k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.29 vpr 65.68 MiB -1 -1 0.43 22296 3 0.11 -1 -1 37252 -1 54836 68 99 1 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 67260 99 130 344 474 1 226 298 12 12 144 clb auto 26.7 MiB 0.13 629 72933 24501 35348 13084 65.7 MiB 0.18 0.00 1.87772 -119.549 -1.87772 1.87772 0.37 0.00051977 0.000459714 0.0411697 0.0365658 -1 -1 -1 -1 44 1503 13 5.66058e+06 4.21279e+06 360780. 2505.42 0.89 0.173941 0.157684 13094 71552 -1 1291 9 444 678 32652 9532 1.88524 1.88524 -138.119 -1.88524 -0.676272 -0.265573 470765. 3269.20 0.15 0.04 0.08 -1 -1 0.15 0.0197651 0.0186328 0.01201 0.2318 0.06967 0.6986 -k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml diffeq1.v common 16.90 vpr 68.78 MiB -1 -1 0.66 26996 15 0.45 -1 -1 37864 -1 57100 39 162 0 5 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 70432 162 96 1009 950 1 711 302 16 16 256 mult_36 auto 29.8 MiB 0.40 5244 100490 36162 56322 8006 68.8 MiB 0.64 0.01 21.0218 -1540.44 -21.0218 21.0218 0.86 0.00242426 0.00217373 0.209853 0.186614 -1 -1 -1 -1 60 12120 38 1.21132e+07 4.08187e+06 934704. 3651.19 8.81 0.859922 0.778088 27268 184674 -1 9238 21 3171 6591 898709 258665 22.6022 22.6022 -1615.35 -22.6022 0 0 1.17756e+06 4599.85 0.38 0.31 0.20 -1 -1 0.38 0.126989 0.118088 0.008138 0.3663 0.01781 0.6159 -k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml LU8PEEng.v common 580.08 vpr 462.27 MiB -1 -1 81.14 357920 123 96.43 -1 -1 82376 -1 119492 1283 114 45 8 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 473364 114 102 21994 21904 1 11396 1552 50 50 2500 memory auto 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11640 32 1.21132e+07 3.92018e+06 780512. 3048.87 4.45 0.687777 0.624546 25484 153448 -1 9689 15 3086 6229 925159 229377 22.1237 22.1237 -1616.56 -22.1237 0 0 1.00276e+06 3917.05 0.33 0.27 0.16 -1 -1 0.33 0.0927712 0.0869862 0.007966 0.3547 0.01635 0.629 -k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 903.74 vpr 459.57 MiB -1 -1 76.30 357412 123 94.44 -1 -1 82144 -1 119384 1303 114 45 8 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 470604 114 102 21994 21904 1 11945 1572 50 50 2500 memory auto 157.4 MiB 236.80 155446 1015668 369921 626939 18808 459.6 MiB 30.91 0.22 79.7453 -52233.7 -79.7453 79.7453 32.96 0.057856 0.0500088 7.72209 6.32253 -1 -1 -1 -1 98 235418 31 1.47946e+08 9.80543e+07 1.60641e+07 6425.63 329.58 28.1814 23.6363 348768 3430976 -1 212823 21 45556 172847 10528121 1854644 81.5508 81.5508 -63599.7 -81.5508 -17.3574 -0.295467 2.03677e+07 8147.07 7.81 5.08 3.96 -1 -1 7.81 2.81265 2.48664 0.0847 0.4264 0.01149 0.5621 -k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.50 vpr 65.84 MiB -1 -1 0.43 22032 3 0.11 -1 -1 37572 -1 55080 68 99 1 0 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 67424 99 130 344 474 1 224 298 12 12 144 clb auto 26.6 MiB 0.18 640 74923 24032 38029 12862 65.8 MiB 0.19 0.00 1.85836 -119.386 -1.85836 1.85836 0.35 0.000508109 0.000449314 0.0420681 0.037305 -1 -1 -1 -1 48 1399 19 5.66058e+06 4.21279e+06 394078. 2736.65 0.97 0.195813 0.177019 13382 75762 -1 1315 10 382 581 31540 8904 1.97104 1.97104 -135.474 -1.97104 -0.999065 -0.298787 503207. 3494.49 0.21 0.05 0.08 -1 -1 0.21 0.0264135 0.0245771 0.01192 0.2466 0.07003 0.6833 -k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 14.77 vpr 68.82 MiB -1 -1 0.61 26804 15 0.46 -1 -1 37804 -1 57100 36 162 0 5 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 70468 162 96 1009 950 1 713 299 16 16 256 mult_36 auto 29.7 MiB 1.34 5364 72227 19590 45379 7258 68.8 MiB 0.42 0.01 21.0826 -1528.67 -21.0826 21.0826 0.70 0.0015561 0.00136801 0.129656 0.114768 -1 -1 -1 -1 48 12805 41 1.21132e+07 3.92018e+06 756778. 2956.16 6.62 0.755014 0.68285 25228 149258 -1 9805 16 3331 6769 959822 240776 22.0604 22.0604 -1637.72 -22.0604 0 0 968034. 3781.38 0.39 0.29 0.19 -1 -1 0.39 0.0979586 0.0917977 0.008221 0.3371 0.01616 0.6467 -k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 795.00 vpr 457.32 MiB -1 -1 77.67 357620 123 105.62 -1 -1 82744 -1 119076 1201 114 45 8 success v8.0.0-11451-g5181cb646 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-190-generic x86_64 2024-10-03T13:06:42 qlsof04.quicklogic.om /home/smahmoudi/Desktop/openfpga/OpenFPGA/vtr-verilog-to-routing/vtr_flow/tasks 468296 114 102 21994 21904 1 11170 1470 50 50 2500 memory auto 157.1 MiB 229.77 145223 903810 323881 562576 17353 457.3 MiB 23.38 0.20 78.3462 -52922.5 -78.3462 78.3462 26.68 0.0415042 0.034747 5.1886 4.17196 -1 -1 -1 -1 92 224213 40 1.47946e+08 9.25569e+07 1.52089e+07 6083.58 231.27 23.1628 19.3148 338772 3221652 -1 200921 20 44271 169310 10439629 1870593 79.3368 79.3368 -63585.9 -79.3368 -30.0926 -0.295467 1.93279e+07 7731.17 8.50 7.66 3.68 -1 -1 8.50 4.13252 3.69005 0.08467 0.4033 0.01157 0.5851 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.76 vpr 64.06 MiB -1 -1 0.45 18428 3 0.09 -1 -1 33228 -1 53036 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65596 99 130 344 474 1 226 298 12 12 144 clb auto 24.8 MiB 0.08 690 66963 18463 34948 13552 64.1 MiB 0.23 0.00 1.84453 -119.387 -1.84453 1.84453 0.26 0.00128301 0.00121619 0.0902368 0.085465 -1 -1 -1 -1 48 1235 27 5.66058e+06 4.21279e+06 394078. 2736.65 0.88 0.373857 0.343183 13382 75762 -1 1211 8 384 646 27249 8414 1.92052 1.92052 -141.203 -1.92052 -0.22504 -0.106568 503207. 3494.49 0.11 0.04 0.07 -1 -1 0.11 0.027115 0.0250754 0.01051 0.26 0.08082 0.6592 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 14.27 vpr 67.39 MiB -1 -1 0.71 23632 15 0.35 -1 -1 34492 -1 54792 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69008 162 96 1009 950 1 711 302 16 16 256 mult_36 auto 28.2 MiB 0.26 5690 95430 30621 57523 7286 67.4 MiB 0.71 0.01 21.0118 -1578.46 -21.0118 21.0118 0.51 0.00329249 0.00309405 0.327743 0.307697 -1 -1 -1 -1 48 13017 37 1.21132e+07 4.08187e+06 756778. 2956.16 7.85 1.49988 1.37661 25228 149258 -1 10215 19 3466 7106 912370 260096 21.8757 21.8757 -1697.9 -21.8757 0 0 968034. 3781.38 0.22 0.33 0.13 -1 -1 0.22 0.146899 0.13583 0.007773 0.3631 0.01709 0.6198 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 401.39 vpr 460.05 MiB -1 -1 83.22 343248 123 58.49 -1 -1 79500 -1 117196 1366 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 471088 114 102 21994 21904 1 11836 1635 50 50 2500 memory auto 154.8 MiB 20.21 157807 1070343 385976 662554 21813 460.0 MiB 25.59 0.21 79.4041 -53458.1 -79.4041 79.4041 19.31 0.0604453 0.0527448 7.45004 6.20215 -1 -1 -1 -1 94 240754 50 1.47946e+08 1.0145e+08 1.55181e+07 6207.23 114.06 27.7995 22.9975 341268 3271592 -1 215929 21 44770 168610 10181079 1913380 79.6681 79.6681 -67309 -79.6681 -34.1184 -0.295467 1.95446e+07 7817.85 7.00 6.34 2.88 -1 -1 7.00 3.52242 3.0254 0.08167 0.4293 0.0115 0.5592 + k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.68 vpr 64.21 MiB -1 -1 0.49 18412 3 0.09 -1 -1 33192 -1 53180 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65752 99 130 344 474 1 226 298 12 12 144 clb auto 25.2 MiB 0.10 819 72933 24290 33841 14802 64.2 MiB 0.24 0.00 1.91347 -122.834 -1.91347 1.91347 0.26 0.00128041 0.00121074 0.0975158 0.0923199 -1 -1 -1 -1 46 1427 13 5.66058e+06 4.21279e+06 378970. 2631.74 1.69 0.37035 0.339938 13238 73581 -1 1364 9 400 647 30525 8792 1.87624 1.87624 -136.601 -1.87624 -1.17589 -0.322548 486261. 3376.82 0.10 0.05 0.07 -1 -1 0.10 0.029177 0.0269441 0.01251 0.2572 0.06872 0.6741 + k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml diffeq1.v common 13.20 vpr 67.45 MiB -1 -1 0.72 23304 15 0.35 -1 -1 34404 -1 54880 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69064 162 96 1009 950 1 711 302 16 16 256 mult_36 auto 28.2 MiB 0.33 5690 95430 30623 57523 7284 67.4 MiB 0.72 0.01 21.0118 -1578.35 -21.0118 21.0118 0.52 0.00334815 0.00314845 0.334671 0.314364 -1 -1 -1 -1 48 13572 38 1.21132e+07 4.08187e+06 756778. 2956.16 6.63 1.3536 1.2446 25228 149258 -1 10088 17 3403 6982 882550 253315 21.8901 21.8901 -1680.47 -21.8901 0 0 968034. 3781.38 0.22 0.31 0.13 -1 -1 0.22 0.135825 0.125866 0.008049 0.3475 0.01649 0.636 + k6_N10_I40_Fi6_L4_frac1_ff2_45nm.xml LU8PEEng.v common 408.55 vpr 462.37 MiB -1 -1 83.91 346936 123 56.59 -1 -1 79516 -1 117232 1283 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 473464 114 102 21994 21904 1 11396 1552 50 50 2500 memory auto 158.9 MiB 48.19 155931 971608 341857 610635 19116 462.4 MiB 25.21 0.21 80.3837 -53565.2 -80.3837 80.3837 20.66 0.0618498 0.0542286 7.48256 6.24492 -1 -1 -1 -1 96 229667 22 1.47946e+08 9.69764e+07 1.58254e+07 6330.17 92.97 25.1374 20.8491 343768 3324272 -1 208496 21 41726 161181 9376663 1766124 80.5561 80.5561 -67304.6 -80.5561 -13.3147 -0.295467 1.97871e+07 7914.84 6.32 5.96 2.94 -1 -1 6.32 3.48565 2.98525 0.08322 0.4235 0.01132 0.5652 + k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.77 vpr 64.30 MiB -1 -1 0.47 18588 3 0.09 -1 -1 33172 -1 53072 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65844 99 130 344 474 1 226 298 12 12 144 clb auto 25.1 MiB 0.15 699 66963 17966 34693 14304 64.3 MiB 0.23 0.00 1.84343 -124.37 -1.84343 1.84343 0.27 0.00123085 0.00116207 0.0901875 0.0853725 -1 -1 -1 -1 34 1396 8 5.66058e+06 4.21279e+06 307677. 2136.65 1.83 0.530992 0.483083 12584 59343 -1 1233 10 404 639 23079 7765 1.94353 1.94353 -145.674 -1.94353 -0.336499 -0.167028 377431. 2621.05 0.09 0.05 0.05 -1 -1 0.09 0.0313345 0.0289285 0.01001 0.231 0.07204 0.697 + k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 13.25 vpr 67.53 MiB -1 -1 0.72 23416 15 0.35 -1 -1 34272 -1 54808 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69152 162 96 1009 950 1 705 302 16 16 256 mult_36 auto 28.3 MiB 0.84 5916 86322 26942 52489 6891 67.5 MiB 0.65 0.01 21.2591 -1580.87 -21.2591 21.2591 0.54 0.00333899 0.00313775 0.30219 0.283938 -1 -1 -1 -1 48 12788 29 1.21132e+07 4.08187e+06 791884. 3093.30 6.16 1.45115 1.33083 26208 159478 -1 10226 17 3178 6770 896758 257736 22.1828 22.1828 -1735.12 -22.1828 0 0 1.01413e+06 3961.44 0.24 0.32 0.13 -1 -1 0.24 0.137182 0.127174 0.008014 0.3561 0.01656 0.6273 + k6_N10_I47_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 680.75 vpr 490.74 MiB -1 -1 81.98 346216 123 60.04 -1 -1 79272 -1 117192 1288 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 502520 114 102 21994 21904 1 12045 1557 50 50 2500 memory auto 155.5 MiB 213.60 164488 1011797 361199 628216 22382 490.7 MiB 26.52 0.22 79.4472 -51530.1 -79.4472 79.4472 22.32 0.060741 0.0533068 7.58406 6.36451 -1 -1 -1 -1 96 243545 47 1.47946e+08 9.72458e+07 1.65526e+07 6621.02 194.25 27.7583 23.1223 355864 3561008 -1 217786 21 41299 157335 9832993 1863421 80.3477 80.3477 -63213.1 -80.3477 -9.95257 -0.29436 2.06346e+07 8253.84 6.55 6.06 3.05 -1 -1 6.55 3.47074 2.99437 0.08657 0.4192 0.01142 0.5694 + k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.40 vpr 64.41 MiB -1 -1 0.46 18612 3 0.09 -1 -1 33252 -1 52968 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65952 99 130 344 474 1 226 298 12 12 144 clb auto 25.4 MiB 0.13 692 72933 23276 35223 14434 64.4 MiB 0.24 0.00 1.86464 -118.633 -1.86464 1.86464 0.27 0.00127857 0.00121127 0.0978445 0.0926191 -1 -1 -1 -1 38 1411 12 5.66058e+06 4.21279e+06 334530. 2323.13 1.40 0.417201 0.382648 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k6_N10_I47_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 590.93 vpr 489.86 MiB -1 -1 82.75 346848 123 58.04 -1 -1 79280 -1 117184 1193 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 501620 114 102 21994 21904 1 11319 1462 50 50 2500 memory auto 156.6 MiB 191.22 150803 905508 321541 566075 17892 489.9 MiB 22.88 0.19 78.1077 -50345.2 -78.1077 78.1077 21.98 0.0591849 0.0516876 7.17008 5.99965 -1 -1 -1 -1 92 228120 37 1.47946e+08 9.21257e+07 1.59225e+07 6369.02 133.10 26.7258 22.1743 350868 3451476 -1 203270 20 41572 162541 9562123 1847272 78.237 78.237 -64005.6 -78.237 -38.6467 -0.293253 2.01686e+07 8067.44 6.81 6.03 2.89 -1 -1 6.81 3.4232 2.94021 0.08721 0.4013 0.01147 0.5872 + k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.75 vpr 64.53 MiB -1 -1 0.47 18468 3 0.09 -1 -1 33276 -1 53036 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66076 99 130 344 474 1 224 298 12 12 144 clb auto 25.3 MiB 0.15 684 73928 22492 35269 16167 64.5 MiB 0.25 0.00 1.84564 -120.454 -1.84564 1.84564 0.28 0.00128312 0.00121622 0.099544 0.0942601 -1 -1 -1 -1 32 1444 14 5.66058e+06 4.21279e+06 307825. 2137.67 0.69 0.279002 0.257511 12860 59602 -1 1374 12 375 565 30620 10341 2.02431 2.02431 -141.661 -2.02431 -0.372022 -0.169903 375846. 2610.04 0.09 0.05 0.05 -1 -1 0.09 0.0357317 0.0329107 0.009994 0.2606 0.06791 0.6715 + k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 11.09 vpr 67.76 MiB -1 -1 0.72 23484 15 0.35 -1 -1 34496 -1 54884 36 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69384 162 96 1009 950 1 712 299 16 16 256 mult_36 auto 28.5 MiB 0.82 5783 78221 22549 49384 6288 67.8 MiB 0.60 0.01 21.2118 -1583.01 -21.2118 21.2118 0.56 0.00335661 0.00314936 0.275732 0.259044 -1 -1 -1 -1 46 13220 42 1.21132e+07 3.92018e+06 791147. 3090.42 4.06 0.996512 0.917657 26792 163197 -1 10183 19 3349 7152 989589 281475 22.2653 22.2653 -1681.46 -22.2653 0 0 1.01637e+06 3970.19 0.23 0.34 0.13 -1 -1 0.23 0.146642 0.135717 0.008056 0.352 0.01624 0.6318 + k6_N10_I53_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 685.71 vpr 541.36 MiB -1 -1 82.72 346304 123 60.41 -1 -1 79620 -1 117176 1274 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 554352 114 102 21994 21904 1 11815 1543 50 50 2500 memory auto 156.5 MiB 261.00 166633 946215 318795 604305 23115 541.4 MiB 23.62 0.21 80.1279 -54074.7 -80.1279 80.1279 26.36 0.0593802 0.0519284 6.93138 5.84084 -1 -1 -1 -1 94 248407 44 1.47946e+08 9.64913e+07 1.68500e+07 6739.98 149.04 27.7074 23.0826 363732 3705320 -1 218597 20 39669 154060 10430670 2004897 80.2496 80.2496 -66632.5 -80.2496 -14.4798 -0.29436 2.11127e+07 8445.07 6.74 6.02 3.27 -1 -1 6.74 3.35396 2.8887 0.08961 0.4087 0.01166 0.5796 + k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.69 vpr 64.59 MiB -1 -1 0.47 18536 3 0.09 -1 -1 33168 -1 53016 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66140 99 130 344 474 1 224 298 12 12 144 clb auto 25.6 MiB 0.14 723 72933 21131 35508 16294 64.6 MiB 0.24 0.00 1.84896 -122.984 -1.84896 1.84896 0.28 0.00129708 0.00123013 0.0982963 0.0931302 -1 -1 -1 -1 32 1546 9 5.66058e+06 4.21279e+06 307825. 2137.67 1.66 0.461106 0.422085 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k6_N10_I53_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 710.23 vpr 546.39 MiB -1 -1 84.01 346708 123 57.00 -1 -1 79472 -1 117204 1175 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 559508 114 102 21994 21904 1 10942 1444 50 50 2500 memory auto 156.6 MiB 247.45 149383 890666 315853 555376 19437 546.4 MiB 24.29 0.22 78.9433 -49861.2 -78.9433 78.9433 26.06 0.0637968 0.0519727 7.43281 6.14665 -1 -1 -1 -1 92 224977 28 1.47946e+08 9.11556e+07 1.65231e+07 6609.23 189.49 27.8764 23.0735 361236 3648468 -1 197674 21 36197 148054 8655924 1696159 79.8587 79.8587 -61942.5 -79.8587 -11.4535 -0.29436 2.08892e+07 8355.67 6.76 5.76 3.02 -1 -1 6.76 3.44382 2.97064 0.08992 0.3929 0.01157 0.5955 + k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.83 vpr 64.24 MiB -1 -1 0.46 18588 3 0.09 -1 -1 33268 -1 53060 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65780 99 130 344 474 1 226 298 12 12 144 clb auto 25.0 MiB 0.14 690 66963 18463 34948 13552 64.2 MiB 0.23 0.00 1.84453 -119.387 -1.84453 1.84453 0.26 0.00128966 0.00122151 0.0906009 0.0857911 -1 -1 -1 -1 48 1219 27 5.66058e+06 4.21279e+06 394078. 2736.65 0.88 0.374327 0.343576 13382 75762 -1 1213 10 380 620 26636 8291 1.92052 1.92052 -132.564 -1.92052 -0.22504 -0.106568 503207. 3494.49 0.11 0.05 0.07 -1 -1 0.11 0.031463 0.0290047 0.01061 0.2612 0.08008 0.6587 + k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml diffeq1.v common 13.92 vpr 67.27 MiB -1 -1 0.74 23740 15 0.35 -1 -1 34420 -1 54776 37 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 68880 162 96 1009 950 1 705 300 16 16 256 mult_36 auto 28.1 MiB 0.78 5822 99597 35964 57057 6576 67.3 MiB 0.75 0.01 20.9826 -1581.32 -20.9826 20.9826 0.51 0.00340159 0.00318809 0.352654 0.330998 -1 -1 -1 -1 46 13288 46 1.21132e+07 3.97408e+06 727248. 2840.81 6.84 1.58393 1.45671 24972 144857 -1 10547 19 3468 7301 1024533 298496 22.4428 22.4428 -1807.38 -22.4428 0 0 934704. 3651.19 0.21 0.34 0.12 -1 -1 0.21 0.144733 0.133839 0.00776 0.3586 0.01653 0.6249 + k6_N10_I40_Fi7_L4_frac1_ff1_45nm.xml LU8PEEng.v common 530.63 vpr 452.32 MiB -1 -1 84.49 343012 123 57.56 -1 -1 79496 -1 117260 1312 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 463172 114 102 21994 21904 1 12069 1581 50 50 2500 memory auto 155.7 MiB 153.23 156855 1014241 368235 623960 22046 452.3 MiB 24.95 0.21 79.7937 -51339.3 -79.7937 79.7937 19.16 0.0602961 0.0527292 7.34313 6.15426 -1 -1 -1 -1 96 234956 41 1.47946e+08 9.85393e+07 1.58254e+07 6330.17 110.51 24.5347 20.3374 343768 3324272 -1 213019 20 45703 171940 10043077 1887993 79.5447 79.5447 -64945.1 -79.5447 -27.0382 -0.295467 1.97871e+07 7914.84 6.68 5.96 2.93 -1 -1 6.68 3.33648 2.88206 0.08305 0.4251 0.01164 0.5633 + k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 4.60 vpr 64.32 MiB -1 -1 0.46 18460 3 0.09 -1 -1 33116 -1 52940 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65868 99 130 344 474 1 226 298 12 12 144 clb auto 25.3 MiB 0.13 819 72933 24290 33841 14802 64.3 MiB 0.24 0.00 1.91347 -122.834 -1.91347 1.91347 0.26 0.00127684 0.00120774 0.0977163 0.092509 -1 -1 -1 -1 46 1423 13 5.66058e+06 4.21279e+06 378970. 2631.74 1.68 0.370142 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k6_N10_I40_Fi7_L4_frac1_ff2_45nm.xml LU8PEEng.v common 567.80 vpr 459.82 MiB -1 -1 83.88 346828 123 56.93 -1 -1 79404 -1 117236 1232 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 470852 114 102 21994 21904 1 11410 1501 50 50 2500 memory auto 157.1 MiB 153.85 152566 937811 338282 579692 19837 459.8 MiB 23.16 0.20 79.5093 -52803.3 -79.5093 79.5093 19.01 0.0589847 0.0516048 7.12415 5.9667 -1 -1 -1 -1 94 230017 31 1.47946e+08 9.42277e+07 1.55181e+07 6207.23 151.42 27.1606 22.5407 341268 3271592 -1 206976 21 43395 164909 10164437 1931987 79.3467 79.3467 -64718.7 -79.3467 -7.07382 -0.296573 1.95446e+07 7817.85 6.05 6.03 2.95 -1 -1 6.05 3.41938 2.93997 0.08398 0.4124 0.01155 0.5761 + k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.79 vpr 64.62 MiB -1 -1 0.46 18580 3 0.09 -1 -1 33112 -1 53044 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66176 99 130 344 474 1 224 298 12 12 144 clb auto 25.4 MiB 0.15 678 73928 21255 36531 16142 64.6 MiB 0.25 0.00 1.84343 -119.532 -1.84343 1.84343 0.27 0.00127236 0.00120574 0.0989421 0.0936831 -1 -1 -1 -1 50 1296 14 5.66058e+06 4.21279e+06 406292. 2821.48 1.82 0.448976 0.411503 13526 77840 -1 1195 11 357 532 29874 9121 1.99509 1.99509 -135.514 -1.99509 -0.544742 -0.178238 520805. 3616.70 0.11 0.05 0.07 -1 -1 0.11 0.0334864 0.0308874 0.01027 0.2615 0.07863 0.6599 + k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml diffeq1.v common 10.02 vpr 67.49 MiB -1 -1 0.73 23636 15 0.35 -1 -1 34472 -1 54844 36 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69108 162 96 1009 950 1 713 299 16 16 256 mult_36 auto 28.3 MiB 0.75 5721 86213 28592 52244 5377 67.5 MiB 0.66 0.01 20.8058 -1501.7 -20.8058 20.8058 0.51 0.00342119 0.00321645 0.305002 0.28669 -1 -1 -1 -1 48 13175 30 1.21132e+07 3.92018e+06 756778. 2956.16 3.01 0.967828 0.892591 25228 149258 -1 10301 18 3425 6878 942155 258318 22.3533 22.3533 -1697.63 -22.3533 0 0 968034. 3781.38 0.22 0.33 0.14 -1 -1 0.22 0.143607 0.132965 0.007929 0.3557 0.01643 0.6279 + k6_N10_I40_Fi8_L4_frac1_ff1_45nm.xml LU8PEEng.v common 625.06 vpr 452.82 MiB -1 -1 84.98 342824 123 57.69 -1 -1 79376 -1 117200 1303 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 463692 114 102 21994 21904 1 11945 1572 50 50 2500 memory auto 156.6 MiB 165.49 160111 988260 342703 624333 21224 452.8 MiB 23.88 0.23 79.9872 -53373.2 -79.9872 79.9872 18.91 0.0587079 0.0512977 7.09493 5.97271 -1 -1 -1 -1 98 240200 31 1.47946e+08 9.80543e+07 1.60641e+07 6425.63 192.41 27.0374 22.491 348768 3430976 -1 216847 21 44681 169424 9942056 1841988 81.5457 81.5457 -64488 -81.5457 -39.6896 -0.29436 2.03677e+07 8147.07 6.25 5.93 3.10 -1 -1 6.25 3.40108 2.93127 0.08479 0.4269 0.01147 0.5616 + k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml ch_intrinsics.v common 3.82 vpr 64.68 MiB -1 -1 0.48 18524 3 0.09 -1 -1 33252 -1 53000 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 66236 99 130 344 474 1 224 298 12 12 144 clb auto 25.7 MiB 0.13 698 72933 20188 36234 16511 64.7 MiB 0.24 0.00 1.84564 -121.191 -1.84564 1.84564 0.26 0.00128124 0.00121391 0.0977819 0.0926146 -1 -1 -1 -1 48 1220 12 5.66058e+06 4.21279e+06 394078. 2736.65 0.84 0.349739 0.321525 13382 75762 -1 1200 11 356 571 27848 8427 1.97152 1.97152 -138.744 -1.97152 -0.366576 -0.220625 503207. 3494.49 0.11 0.05 0.07 -1 -1 0.11 0.0335359 0.030924 0.01177 0.2373 0.07035 0.6923 + k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml diffeq1.v common 12.60 vpr 67.55 MiB -1 -1 0.73 23468 15 0.35 -1 -1 34400 -1 54856 36 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69172 162 96 1009 950 1 713 299 16 16 256 mult_36 auto 28.4 MiB 0.93 5721 86213 28592 52244 5377 67.6 MiB 0.66 0.01 20.8058 -1501.7 -20.8058 20.8058 0.51 0.00335344 0.00314925 0.303909 0.285307 -1 -1 -1 -1 50 11869 21 1.21132e+07 3.92018e+06 780512. 3048.87 5.52 1.32663 1.21819 25484 153448 -1 10126 17 3362 6747 918313 252436 22.3405 22.3405 -1650.85 -22.3405 0 0 1.00276e+06 3917.05 0.22 0.31 0.13 -1 -1 0.22 0.137518 0.127577 0.008272 0.3466 0.01554 0.6378 + k6_N10_I40_Fi8_L4_frac1_ff2_45nm.xml LU8PEEng.v common 598.55 vpr 491.77 MiB -1 -1 84.05 346908 123 53.64 -1 -1 79372 -1 117228 1201 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 503568 114 102 21994 21904 1 11170 1470 50 50 2500 memory auto 156.4 MiB 166.03 150651 903810 320390 563000 20420 459.0 MiB 22.23 0.19 78.4561 -52150.3 -78.4561 78.4561 18.73 0.058846 0.0512813 7.13124 5.98955 -1 -1 -1 -1 96 226476 38 1.47946e+08 9.25569e+07 1.58254e+07 6330.17 173.31 36.0661 29.773 343768 3324272 -1 204225 21 42293 163966 10269335 1942383 79.7709 79.7709 -64638.4 -79.7709 -5.0051 -0.29436 1.97871e+07 7914.84 6.66 6.08 2.93 -1 -1 6.66 3.42255 2.94526 0.08545 0.4092 0.0116 0.5791 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt index 285a938c836..cc62481848e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/power_extended_circuit_list/config/golden_results.txt @@ -1,15 +1,15 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 118.17 yosys 239.31 MiB -1 -1 51.84 245056 13 12.95 -1 -1 50988 -1 -1 313 257 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 95156 257 32 5001 5033 1 3011 602 23 23 529 clb auto 56.0 MiB 5.68 20073 92.9 MiB 3.10 0.05 7.61128 -3510.49 -7.61128 7.61128 2.19 0.0111481 0.00983092 0.916096 0.788394 60 35506 34 2.70004e+07 1.68688e+07 2.06423e+06 3902.13 20.90 5.4675 4.72714 30778 18 12207 37399 1098944 213018 8.87264 8.87264 -3988.79 -8.87264 0 0 2.59942e+06 4913.83 1.24 1.06 0.707414 0.634904 0.01734 0.4421 0.03657 0.5213 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 130.38 yosys 302.73 MiB -1 -1 18.70 309992 7 21.41 -1 -1 60784 -1 -1 537 36 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 123272 36 100 6697 6797 1 3126 673 29 29 841 clb auto 77.8 MiB 4.69 41345 113.1 MiB 5.96 0.06 5.0253 -1944.45 -5.0253 5.0253 3.63 0.0214375 0.0185487 2.09612 1.71533 66 67063 48 4.4999e+07 2.89411e+07 3.69960e+06 4399.04 43.46 8.21932 6.87193 62012 17 15462 69778 3185690 420494 5.80294 5.80294 -2196.36 -5.80294 0 0 4.59256e+06 5460.83 2.14 2.18 1.24423 1.10278 0.02472 0.3552 0.06214 0.5826 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 24.82 vpr 66.18 MiB -1 -1 15.48 35192 4 0.33 -1 -1 37500 -1 -1 51 195 1 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67772 195 193 1088 1281 1 613 440 15 15 225 io auto 28.3 MiB 0.37 2873 66.2 MiB 0.63 0.01 2.15453 -974.75 -2.15453 2.15453 0.74 0.00245513 0.00221571 0.223119 0.201239 38 6306 20 1.03862e+07 3.29659e+06 544128. 2418.35 2.59 0.885138 0.807423 5528 13 1819 2712 205627 56709 2.87081 2.87081 -1195.56 -2.87081 -1.12498 -0.225697 690492. 3068.85 0.27 0.16 0.0993493 0.092867 0.01341 0.3908 0.05272 0.5565 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 4.12 vpr 62.71 MiB -1 -1 0.35 21964 3 0.10 -1 -1 36320 -1 -1 68 99 1 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64216 99 130 343 473 1 230 298 12 12 144 clb auto 24.2 MiB 0.10 571 62.7 MiB 0.19 0.00 1.63028 -111.073 -1.63028 1.63028 0.39 0.00057726 0.000511834 0.0463341 0.0412497 48 1238 11 5.66058e+06 4.21279e+06 394078. 2736.65 0.85 0.150288 0.136516 1104 12 413 672 30654 9331 1.97152 1.97152 -135.95 -1.97152 -0.565496 -0.22459 503207. 3494.49 0.17 0.04 0.0237397 0.0221527 0.01024 0.2567 0.08152 0.6618 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 13.46 vpr 65.84 MiB -1 -1 0.51 26972 15 0.48 -1 -1 37332 -1 -1 38 162 0 5 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67416 162 96 993 934 1 696 301 16 16 256 mult_36 auto 28.1 MiB 0.32 5333 65.8 MiB 0.58 0.01 19.8134 -1613.84 -19.8134 19.8134 0.82 0.00196503 0.00176669 0.216397 0.194672 50 11841 28 1.21132e+07 4.02797e+06 780512. 3048.87 5.66 0.860795 0.785647 9624 18 3046 5877 1921714 505718 22.589 22.589 -1796.16 -22.589 0 0 1.00276e+06 3917.05 0.36 0.58 0.130005 0.122138 0.007573 0.3655 0.01688 0.6176 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq2.v common 12.22 vpr 63.56 MiB -1 -1 0.41 25532 16 0.33 -1 -1 36568 -1 -1 26 66 0 5 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 65084 66 96 602 543 1 412 193 16 16 256 mult_36 auto 25.5 MiB 0.29 3291 63.6 MiB 0.26 0.00 16.0938 -894.619 -16.0938 16.0938 0.81 0.00127432 0.00114171 0.104197 0.0935966 44 8497 45 1.21132e+07 3.38124e+06 694168. 2711.59 5.84 0.55853 0.511939 6726 18 2515 5229 1795297 493920 17.9318 17.9318 -1032.8 -17.9318 0 0 904549. 3533.39 0.33 0.48 0.0819937 0.0771717 0.007449 0.3408 0.02068 0.6385 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 623.93 vpr 395.42 MiB -1 -1 75.93 339996 122 99.45 -1 -1 81636 -1 -1 1377 114 45 8 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 404908 114 102 21867 21777 1 11713 1646 50 50 2500 memory auto 189.6 MiB 24.18 159901 395.4 MiB 31.48 0.27 66.9303 -51944.3 -66.9303 66.9303 35.97 0.0625446 0.0549037 7.72914 6.27941 96 244541 40 1.47946e+08 1.02043e+08 1.58254e+07 6330.17 229.03 32.8888 27.1166 217988 20 43499 165318 31857426 7188217 79.3851 79.3851 -66427.4 -79.3851 -23.4783 -0.29436 1.97871e+07 7914.84 9.70 14.56 4.42177 3.7852 0.08209 0.4334 0.01151 0.5551 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkDelayWorker32B.v common 123.18 vpr 298.46 MiB -1 -1 16.17 127512 5 4.96 -1 -1 59956 -1 -1 460 506 47 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 305628 506 553 3055 3608 1 2790 1566 50 50 2500 memory auto 50.6 MiB 4.09 13904 298.5 MiB 5.28 0.07 6.43708 -1764.15 -6.43708 6.43708 35.74 0.0195755 0.0178485 2.37601 2.13444 38 21640 15 1.47946e+08 5.05479e+07 6.86584e+06 2746.33 24.11 7.18102 6.58732 20682 15 3922 4906 3639753 889525 7.0521 7.0521 -2169.44 -7.0521 -5.81849 -0.218188 8.69095e+06 3476.38 5.45 1.77 0.858304 0.808275 0.1725 0.1372 0.03966 0.8231 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkPktMerge.v common 24.96 vpr 68.00 MiB -1 -1 1.31 29404 2 0.16 -1 -1 37232 -1 -1 26 311 15 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 69628 311 156 972 1128 1 953 508 28 28 784 memory auto 30.0 MiB 0.62 8280 68.0 MiB 1.14 0.02 3.76248 -4168.06 -3.76248 3.76248 3.43 0.00440448 0.00379767 0.487529 0.417469 40 14592 15 4.25198e+07 9.62124e+06 2.13295e+06 2720.61 8.64 1.57197 1.38917 13576 12 2654 3024 3284354 1036497 4.3854 4.3854 -5158.81 -4.3854 -23.6495 -0.360359 2.67004e+06 3405.67 1.35 1.14 0.179296 0.165453 0.08422 0.1581 0.01827 0.8236 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkSMAdapter4B.v common 31.25 vpr 74.75 MiB -1 -1 7.40 57784 7 3.64 -1 -1 42068 -1 -1 152 193 5 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 76540 193 205 2152 2357 1 1167 555 20 20 400 memory auto 37.3 MiB 1.36 9273 74.7 MiB 1.55 0.02 4.44685 -2678.72 -4.44685 4.44685 1.55 0.00520222 0.00457072 0.547293 0.473279 50 17122 28 2.07112e+07 1.09319e+07 1.26944e+06 3173.59 6.08 1.90602 1.67909 15475 14 4537 11714 1075798 262577 5.04741 5.04741 -3136.83 -5.04741 -10.2297 -0.342703 1.63222e+06 4080.54 0.71 0.58 0.279612 0.256468 0.03043 0.2195 0.02571 0.7548 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 105.67 vpr 89.84 MiB -1 -1 6.53 70868 27 6.63 -1 -1 42044 -1 -1 236 385 2 1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 92000 385 394 3905 4236 1 2378 1018 27 27 729 io auto 51.6 MiB 3.14 31412 88.3 MiB 4.79 0.05 12.29 -11845.4 -12.29 12.29 3.20 0.0117449 0.0106209 1.43941 1.29258 78 50872 44 3.93038e+07 1.4211e+07 3.65949e+06 5019.88 60.83 6.51779 5.83078 44991 15 10522 36709 3037271 554357 13.3042 13.3042 -13206 -13.3042 0 0 4.63207e+06 6354.00 2.22 1.62 0.709343 0.647741 0.02338 0.4631 0.02805 0.5089 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml raygentop.v common 35.96 vpr 76.71 MiB -1 -1 5.21 49332 8 1.71 -1 -1 42112 -1 -1 133 235 1 6 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 78556 235 305 2594 2755 1 1498 680 19 19 361 io auto 39.3 MiB 3.14 12169 76.7 MiB 2.05 0.03 4.58675 -2577.4 -4.58675 4.58675 1.36 0.0063415 0.00572791 0.682959 0.614263 60 25617 50 1.72706e+07 1.00919e+07 1.37250e+06 3801.94 11.00 2.51442 2.2699 20583 15 5829 16792 2902566 635419 5.11721 5.11721 -2950.33 -5.11721 -0.0437416 -0.0437416 1.72845e+06 4787.94 0.72 1.00 0.318587 0.295606 0.02699 0.4157 0.02832 0.556 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 26.31 vpr 77.65 MiB -1 -1 3.26 50356 21 3.59 -1 -1 43384 -1 -1 146 38 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 79512 38 36 2570 2606 1 1069 220 17 17 289 clb auto 40.0 MiB 1.39 10001 77.6 MiB 0.81 0.01 12.3748 -2448.1 -12.3748 12.3748 1.01 0.00498816 0.00430442 0.365427 0.314078 50 18301 44 1.34605e+07 7.86852e+06 892012. 3086.55 6.20 1.92486 1.65674 14613 15 4475 13292 455628 80494 14.2542 14.2542 -2891.84 -14.2542 0 0 1.14637e+06 3966.67 0.45 0.45 0.305824 0.276669 0.006823 0.375 0.03027 0.5947 - k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 7130.01 vpr 1.60 GiB -1 -1 623.16 1405836 63 4078.03 -1 -1 352728 -1 -1 6712 36 159 27 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:29 gh-actions-runner-vtr-auto-spawned1 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1673400 36 356 125109 123894 1 34558 7290 97 97 9409 clb auto 813.1 MiB 61.58 466750 1523.7 MiB 142.30 0.95 59.2176 -274107 -59.2176 59.2176 95.16 0.145711 0.124348 22.7677 18.9883 88 619753 49 5.71422e+08 4.59526e+08 5.63268e+07 5986.48 1431.27 99.9647 83.5614 582599 20 118740 386373 70938972 15957299 66.0327 66.0327 -345349 -66.0327 -0.672583 -0.168146 7.06419e+07 7507.91 29.52 25.19 9.15042 8.01416 0.2728 0.3812 0.01373 0.6051 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml bgm.v common 101.34 parmys 236.79 MiB -1 -1 60.71 242472 13 8.21 -1 -1 47864 -1 49620 321 257 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 95300 257 32 5008 5040 1 2969 610 23 23 529 clb auto 50.4 MiB 3.82 20279 215248 66110 139947 9191 93.1 MiB 3.04 0.04 8.70616 -3949.99 -8.70616 8.70616 1.18 0.0125771 0.0113805 1.0992 0.970008 -1 -1 -1 -1 56 34377 21 2.70004e+07 1.73e+07 1.92373e+06 3636.54 8.22 3.45323 3.01988 56706 387443 -1 30578 16 11916 36297 982790 202359 9.34373 9.34373 -4057.11 -9.34373 0 0 2.45466e+06 4640.18 0.60 0.82 0.32 -1 -1 0.60 0.512599 0.462114 0.01666 0.4299 0.03362 0.5365 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml blob_merge.v common 107.46 parmys 306.12 MiB -1 -1 20.79 313468 7 12.29 -1 -1 61008 -1 50612 547 36 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 159172 36 100 6778 6878 1 3152 683 30 30 900 clb auto 67.4 MiB 3.53 43003 265211 75875 171128 18208 113.8 MiB 5.03 0.06 5.7259 -2235.23 -5.7259 5.7259 2.15 0.0185179 0.0154456 1.73258 1.47032 -1 -1 -1 -1 70 65187 20 4.8774e+07 2.948e+07 4.18297e+06 4647.75 38.88 8.89422 7.5224 106732 854442 -1 61867 16 14594 66731 2752238 371387 6.2856 6.2856 -2335.12 -6.2856 0 0 5.26086e+06 5845.40 1.29 1.60 0.70 -1 -1 1.29 0.836319 0.749628 0.02599 0.3676 0.06197 0.5704 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml boundtop.v common 24.16 vpr 67.42 MiB -1 -1 17.13 32316 4 0.24 -1 -1 34324 -1 55220 50 195 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 69040 195 193 1087 1280 1 611 439 15 15 225 io auto 28.5 MiB 0.29 3380 103793 26292 68639 8862 67.4 MiB 0.54 0.01 2.49928 -1085.58 -2.49928 2.49928 0.45 0.00353825 0.00330455 0.231878 0.216292 -1 -1 -1 -1 38 6431 21 1.03862e+07 3.2427e+06 544128. 2418.35 1.99 1.01597 0.930332 21038 109288 -1 5638 14 1680 2547 165707 45554 2.61737 2.61737 -1202.07 -2.61737 -0.383541 -0.179345 690492. 3068.85 0.16 0.17 0.09 -1 -1 0.16 0.118647 0.10973 0.01444 0.3894 0.05366 0.5569 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml ch_intrinsics.v common 3.90 vpr 64.11 MiB -1 -1 0.46 18576 3 0.09 -1 -1 33260 -1 53084 68 99 1 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 65652 99 130 344 474 1 226 298 12 12 144 clb auto 24.9 MiB 0.08 690 66963 18463 34948 13552 64.1 MiB 0.23 0.00 1.84453 -119.387 -1.84453 1.84453 0.26 0.00128062 0.00121358 0.0901314 0.0853406 -1 -1 -1 -1 48 1235 27 5.66058e+06 4.21279e+06 394078. 2736.65 0.89 0.376068 0.345073 13382 75762 -1 1211 8 384 646 27249 8414 1.92052 1.92052 -141.203 -1.92052 -0.22504 -0.106568 503207. 3494.49 0.11 0.04 0.07 -1 -1 0.11 0.0270219 0.0250048 0.01051 0.26 0.08082 0.6592 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq1.v common 10.77 vpr 67.23 MiB -1 -1 0.74 23536 15 0.37 -1 -1 34412 -1 54864 39 162 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 68840 162 96 1009 950 1 711 302 16 16 256 mult_36 auto 28.0 MiB 0.26 5690 95430 30621 57523 7286 67.2 MiB 0.71 0.01 21.0118 -1578.46 -21.0118 21.0118 0.51 0.00332849 0.00313083 0.328391 0.308461 -1 -1 -1 -1 48 13017 37 1.21132e+07 4.08187e+06 756778. 2956.16 4.22 1.0699 0.986615 25228 149258 -1 10215 19 3466 7106 912370 260096 21.8757 21.8757 -1697.9 -21.8757 0 0 968034. 3781.38 0.22 0.33 0.13 -1 -1 0.22 0.149551 0.138422 0.007773 0.3631 0.01709 0.6198 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml diffeq2.v common 11.72 vpr 65.73 MiB -1 -1 0.58 22544 16 0.25 -1 -1 33408 -1 53836 25 66 0 5 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 67312 66 96 616 557 1 415 192 16 16 256 mult_36 auto 26.2 MiB 0.24 3582 35584 8711 22727 4146 65.7 MiB 0.31 0.01 17.0763 -933.216 -17.0763 17.0763 0.51 0.00238059 0.00225121 0.161867 0.152888 -1 -1 -1 -1 38 9038 38 1.21132e+07 3.32735e+06 614590. 2400.74 6.60 0.921446 0.844635 23696 123034 -1 7156 21 2451 5027 1039467 341839 18.1068 18.1068 -1021.94 -18.1068 0 0 780512. 3048.87 0.18 0.32 0.11 -1 -1 0.18 0.111255 0.102688 0.007306 0.3288 0.0194 0.6518 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml LU8PEEng.v common 412.25 vpr 459.94 MiB -1 -1 83.91 345680 123 55.18 -1 -1 79452 -1 117364 1366 114 45 8 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 470976 114 102 21994 21904 1 11836 1635 50 50 2500 memory auto 154.7 MiB 20.14 157807 1070343 385976 662554 21813 459.9 MiB 27.15 0.21 79.4041 -53458.1 -79.4041 79.4041 20.21 0.0604698 0.0528011 7.69778 6.42684 -1 -1 -1 -1 94 240754 50 1.47946e+08 1.0145e+08 1.55181e+07 6207.23 125.92 26.5625 22.0155 341268 3271592 -1 215929 21 44770 168610 10181079 1913380 79.6681 79.6681 -67309 -79.6681 -34.1184 -0.295467 1.95446e+07 7817.85 5.86 5.76 2.89 -1 -1 5.86 3.26586 2.8046 0.08167 0.4293 0.0115 0.5592 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkDelayWorker32B.v common 90.48 vpr 331.86 MiB -1 -1 18.16 125044 5 3.21 -1 -1 56032 -1 73368 460 506 47 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 339828 506 553 3055 3608 1 2790 1566 50 50 2500 memory auto 46.0 MiB 4.79 16153 1137816 548528 407688 181600 331.9 MiB 5.44 0.07 6.67096 -2020.14 -6.67096 6.67096 19.12 0.0225934 0.0204156 2.93437 2.63134 -1 -1 -1 -1 38 23317 18 1.47946e+08 5.05479e+07 6.86584e+06 2746.33 16.87 8.18989 7.41168 251304 1421084 -1 22431 17 3841 4967 1023796 259831 7.09403 7.09403 -2394.32 -7.09403 -1.60806 -0.199574 8.69095e+06 3476.38 2.76 1.13 1.19 -1 -1 2.76 0.934502 0.861192 0.1726 0.1419 0.03943 0.8187 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkPktMerge.v common 21.17 vpr 71.31 MiB -1 -1 1.27 25292 2 0.14 -1 -1 33632 -1 60032 26 311 15 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 73020 311 156 972 1128 1 953 508 28 28 784 memory auto 28.8 MiB 0.46 9244 197030 68488 118013 10529 71.3 MiB 1.14 0.02 4.08264 -4469.06 -4.08264 4.08264 1.88 0.00555662 0.00492709 0.564647 0.499581 -1 -1 -1 -1 36 15359 25 4.25198e+07 9.62124e+06 1.94918e+06 2486.20 9.68 2.58077 2.28028 74338 387760 -1 14127 14 3001 3471 707329 200421 4.39536 4.39536 -4930.06 -4.39536 -23.3965 -0.340786 2.40571e+06 3068.51 0.65 0.37 0.32 -1 -1 0.65 0.203975 0.183729 0.08358 0.1547 0.01721 0.828 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mkSMAdapter4B.v common 25.81 vpr 75.85 MiB -1 -1 8.75 54500 7 2.29 -1 -1 39580 -1 59092 155 193 5 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 77668 193 205 2234 2439 1 1177 558 20 20 400 memory auto 35.7 MiB 1.09 9343 230158 76067 129187 24904 75.8 MiB 1.66 0.02 4.77105 -2950.24 -4.77105 4.77105 0.85 0.00679034 0.00613812 0.712263 0.639828 -1 -1 -1 -1 48 16951 19 2.07112e+07 1.10936e+07 1.23055e+06 3076.38 4.06 1.80116 1.60396 40448 245963 -1 14947 15 4199 10676 555153 128354 5.33264 5.33264 -3131.09 -5.33264 -6.85654 -0.29768 1.57502e+06 3937.55 0.37 0.39 0.21 -1 -1 0.37 0.26107 0.236959 0.029 0.2155 0.0258 0.7587 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml or1200.v common 59.82 vpr 99.94 MiB -1 -1 7.76 67916 27 4.04 -1 -1 38688 -1 61160 230 385 2 1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 102336 385 394 3906 4237 1 2371 1012 27 27 729 io auto 45.8 MiB 2.74 31818 549436 207916 318095 23425 88.1 MiB 5.14 0.06 13.6891 -13601.7 -13.6891 13.6891 1.80 0.015847 0.01475 2.00047 1.83115 -1 -1 -1 -1 74 52043 45 3.93038e+07 1.38876e+07 3.51708e+06 4824.52 23.64 7.06874 6.48735 88217 717307 -1 45806 15 11143 38956 2327403 423270 13.7426 13.7426 -14238.9 -13.7426 0 0 4.41327e+06 6053.86 1.15 1.18 0.59 -1 -1 1.15 0.620583 0.577856 0.02262 0.455 0.02732 0.5177 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml raygentop.v common 26.77 vpr 77.02 MiB -1 -1 6.02 45696 8 1.03 -1 -1 37700 -1 60816 132 235 1 6 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 78872 235 305 2600 2761 1 1513 679 19 19 361 io auto 36.9 MiB 2.30 12446 257217 87938 156711 12568 77.0 MiB 2.00 0.03 5.21052 -2695.25 -5.21052 5.21052 0.78 0.00833798 0.00759325 0.784503 0.720451 -1 -1 -1 -1 56 23724 29 1.72706e+07 1.0038e+07 1.27879e+06 3542.35 6.44 2.59347 2.36584 38159 255829 -1 21061 16 6083 16778 1518471 388985 5.74403 5.74403 -2918.04 -5.74403 -0.678968 -0.063748 1.63234e+06 4521.70 0.37 0.64 0.21 -1 -1 0.37 0.322829 0.298228 0.02425 0.4068 0.02614 0.567 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml sha.v common 19.90 vpr 78.46 MiB -1 -1 4.15 47060 21 2.26 -1 -1 40792 -1 45652 149 38 0 0 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 80344 38 36 2570 2606 1 1067 223 17 17 289 clb auto 37.6 MiB 1.11 9186 42135 10514 28822 2799 78.5 MiB 0.87 0.01 14.489 -2637.24 -14.489 14.489 0.59 0.00570235 0.00505996 0.410899 0.362544 -1 -1 -1 -1 48 15409 28 1.34605e+07 8.03021e+06 864508. 2991.38 3.30 1.52379 1.3128 28519 171069 -1 13295 15 4245 12043 362530 70167 15.0234 15.0234 -2942.08 -15.0234 0 0 1.10659e+06 3829.03 0.25 0.37 0.14 -1 -1 0.25 0.250361 0.222953 0.006573 0.364 0.03019 0.6058 + k6_N10_I40_Fi6_L4_frac1_ff1_45nm.xml mcml.v common 5120.01 vpr 1.66 GiB -1 -1 669.92 1429688 64 3238.48 -1 -1 348532 -1 316988 6755 36 159 27 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 1745216 36 356 125423 124208 1 35759 7333 98 98 9604 clb auto 669.3 MiB 69.08 472751 9976873 4211332 5688117 77424 1704.3 MiB 166.62 1.28 62.922 -266875 -62.922 62.922 79.42 0.238495 0.197947 34.8953 29.1342 -1 -1 -1 -1 84 619524 38 5.9175e+08 4.61843e+08 5.50586e+07 5732.88 291.80 112.255 92.7458 1265060 11766760 -1 588054 18 120512 381178 21916553 4319201 63.8888 63.8888 -334021 -63.8888 0 0 6.99411e+07 7282.50 23.74 17.67 10.44 -1 -1 23.74 11.6929 10.0211 0.2761 0.3715 0.01425 0.6143 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt index f3dfc0ea25e..a3d58104f0a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.float.small.v common 1260.60 vpr 1.65 GiB -1 -1 82.85 943096 6 503.07 -1 -1 203916 -1 -1 1992 114 356 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1727512 114 86 73955 63740 1 36598 2692 104 104 10816 memory auto 602.4 MiB 46.60 824826 1687.0 MiB 116.85 0.90 6.47196 -303223 -6.47196 6.47196 6.03 0.257057 0.204075 33.4945 27.1837 -1 1108103 18 3.44415e+08 1.41138e+08 2.37404e+08 21949.3 76.27 47.2537 39.0222 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 2995.62 vpr 5.21 GiB -1 -1 121.94 1217796 9 1000.94 -1 -1 571064 -1 -1 5866 1428 1144 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5466852 1428 2108 167028 128685 1 100323 10834 194 194 37636 memory auto 1291.1 MiB 278.74 2092925 5338.7 MiB 406.01 2.56 9.34336 -1.35131e+06 -9.34336 9.34336 14.57 0.330195 0.266824 59.6404 49.5844 -1 2887552 17 1.20484e+09 3.94261e+08 8.28785e+08 22021.1 103.20 78.0666 66.033 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 11822.63 vpr 33.73 GiB -1 -1 301.82 1498692 4 2262.81 -1 -1 565160 -1 -1 4071 21 9017 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 35366520 21 26 134015 127194 1 74552 13240 534 534 285156 memory auto 1575.7 MiB 1255.79 3658361 34537.6 MiB 338.82 2.62 14.3492 -1.78071e+06 -14.3492 14.3492 219.35 0.387252 0.315621 66.8828 52.1825 -1 4244397 13 9.28675e+09 1.38166e+09 6.26248e+09 21961.6 73.80 83.5895 66.8884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.float.small.v common 1068.21 vpr 1.88 GiB -1 -1 110.69 930728 6 445.27 -1 -1 199964 -1 -1 1998 114 356 -1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 1971564 114 86 74339 64124 1 36263 2698 104 104 10816 memory auto 494.2 MiB 45.91 837299 2255578 853320 1293833 108425 1925.4 MiB 91.80 0.70 7.38685 -337841 -7.38685 7.38685 0.10 0.26105 0.226933 34.5308 28.5894 -1 -1 -1 -1 -1 1123690 16 3.44415e+08 1.41306e+08 2.36688e+08 21883.2 48.20 47.1429 39.4245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 2948.82 vpr 5.90 GiB -1 -1 166.20 1233468 9 742.44 -1 -1 565628 -1 -1 5863 1428 1144 -1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 6186936 1428 2108 167036 128693 1 100353 10831 194 194 37636 memory auto 1034.3 MiB 297.91 1911950 21092463 8889289 10615756 1587418 6041.9 MiB 570.71 3.42 13.7488 -1.49441e+06 -13.7488 13.7488 0.23 0.615123 0.537901 116.246 98.5856 -1 -1 -1 -1 -1 2690563 15 1.20484e+09 3.94177e+08 8.26603e+08 21963.1 61.79 142.653 121.696 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 13533.79 vpr 39.26 GiB -1 -1 386.60 1503068 4 2106.20 -1 -1 561408 -1 -1 4062 21 9017 -1 success v8.0.0-11683-gf3326338a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-03T17:46:01 betzgrp-wintermute.eecg.utoronto.ca /home/gholam39/vtr/feature/vtr-verilog-to-routing 41169996 21 26 134109 127288 1 74703 13231 534 534 285156 memory auto 1344.1 MiB 1835.62 3633223 25196690 12025307 13086177 85206 40205.1 MiB 652.38 3.80 13.6669 -1.87459e+06 -13.6669 13.6669 1.86 0.863375 0.716443 163.799 128.72 -1 -1 -1 -1 -1 4235395 13 9.28675e+09 1.3814e+09 6.26030e+09 21953.9 81.75 196.429 156.233 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index a40279b9f9c..9e5f6a99351 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 0.93 vpr 65.66 MiB -1 -1 0.06 20352 1 0.01 -1 -1 35860 -1 -1 3 9 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67236 9 8 75 70 1 34 20 5 5 25 clb auto 27.3 MiB 0.38 91 452 103 339 10 65.7 MiB 0.00 0.00 2.64007 -28.7664 -2.64007 2.64007 0.02 7.4568e-05 6.6193e-05 0.00195079 0.00178739 38 154 16 151211 75605.7 48493.3 1939.73 0.11 0.0243483 0.0205304 2100 8065 -1 119 18 114 142 4814 2350 2.64007 2.64007 -31.8474 -2.64007 0 0 61632.8 2465.31 0.01 0.01 0.01 -1 -1 0.01 0.00485388 0.00446806 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 3.87 vpr 66.77 MiB -1 -1 0.08 20736 1 0.01 -1 -1 35944 -1 -1 7 19 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68372 19 18 308 249 1 142 44 6 6 36 clb auto 28.4 MiB 2.88 521 2662 840 1802 20 66.8 MiB 0.02 0.00 4.88121 -98.944 -4.88121 4.88121 0.04 0.000207626 0.000184303 0.0103914 0.00951356 54 1083 35 403230 176413 113905. 3164.04 0.39 0.0844877 0.0734258 4050 20995 -1 745 17 630 985 35752 13957 5.5504 5.5504 -118.789 -5.5504 0 0 146644. 4073.44 0.01 0.02 0.01 -1 -1 0.01 0.014306 0.0132257 55 83 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.40 vpr 64.12 MiB -1 -1 0.11 20096 1 0.02 -1 -1 36000 -1 -1 3 9 0 -1 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65664 9 8 75 70 1 34 20 5 5 25 clb auto 25.6 MiB 0.60 97 74 18 56 0 64.1 MiB 0.00 0.00 2.64007 -29.44 -2.64007 2.64007 0.03 0.000119511 0.000105355 0.00150744 0.00144146 -1 -1 -1 -1 20 183 15 151211 75605.7 29112.5 1164.50 0.11 0.0175261 0.0154045 1812 4729 -1 161 15 134 153 5442 3071 2.98537 2.98537 -38.4554 -2.98537 0 0 37105.9 1484.24 0.00 0.01 0.01 -1 -1 0.00 0.00675063 0.00621765 13 18 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 6.11 vpr 65.06 MiB -1 -1 0.13 20864 1 0.02 -1 -1 36332 -1 -1 7 19 0 -1 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66624 19 18 308 249 1 142 44 6 6 36 clb auto 26.7 MiB 4.50 509 2277 492 1758 27 65.1 MiB 0.04 0.00 4.8135 -98.9875 -4.8135 4.8135 0.06 0.000372692 0.000330895 0.0147327 0.0133843 -1 -1 -1 -1 60 910 23 403230 176413 127342. 3537.27 0.64 0.156558 0.137174 4190 22875 -1 726 16 651 1079 37320 14467 4.73636 4.73636 -105.338 -4.73636 0 0 157803. 4383.41 0.02 0.03 0.02 -1 -1 0.02 0.0215368 0.0200712 55 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt index e34e4d38d17..b7a7b9a3999 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.30 vpr 57.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 84e0337 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:40:08 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 59208 2 2 22 24 2 4 6 4 4 16 clb auto 19.5 MiB 0.01 4 15 2 10 3 57.8 MiB 0.00 0.00 1.297 0 0 1.297 0.01 4.3769e-05 3.8064e-05 0.000324999 0.000293005 4 6 2 72000 36000 2827.54 176.721 0.01 0.00228834 0.0020767 644 852 -1 6 2 4 4 138 80 1.297 1.297 0 0 0 0 4025.56 251.598 0.00 0.00 0.00 -1 -1 0.00 0.00162095 0.00152882 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.20 vpr 57.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 59180 2 2 22 24 2 4 6 4 4 16 clb auto 19.4 MiB 0.01 8 15 5 8 2 57.8 MiB 0.00 0.00 1.297 0 0 1.297 0.01 4.865e-05 4.0365e-05 0.000331746 0.000291111 -1 -1 -1 -1 6 13 3 72000 36000 4025.56 251.598 0.01 0.00265857 0.00243025 660 1032 -1 12 5 7 7 429 325 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00194089 0.00183475 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt index 93572eb9f3e..d911c28e4e3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 3.02 vpr 64.76 MiB -1 -1 0.23 21996 3 0.05 -1 -1 36460 -1 -1 67 99 1 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66316 99 130 343 473 1 217 297 13 13 169 clb auto 26.2 MiB 0.86 456 64.8 MiB 0.12 0.00 34 1050 8 0 0 460544. 2725.11 0.60 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time + k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 4.53 vpr 66.66 MiB -1 -1 0.36 21504 3 0.08 -1 -1 41652 -1 -1 66 99 1 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68264 99 130 344 474 1 218 296 13 13 169 clb auto 27.6 MiB 1.16 826 30862 5429 11872 13561 66.7 MiB 0.05 0.00 28 1633 9 0 0 403031. 2384.80 1.91 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index fe6c3262d6b..d1daf36ffe7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59823 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59823 -1 1.07141 -1 1.75805 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44686 -1 3.30941 -1 -1.48832 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59823 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59823 -1 1.07141 -1 1.75805 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44686 -1 3.30941 -1 -1.48832 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.07141 -1 1.37913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.30941 -1 -1.86724 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.07141 -1 1.37913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.30941 -1 -1.86724 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/config.txt index cd08958fd4c..fbdf4b90a3e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/config.txt @@ -44,4 +44,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -check_equivalent -starting_stage abc --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --seed 5 +script_params=-track_memory_usage -check_equivalent -starting_stage abc --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --route_chan_width 40 --seed 5 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt index db6090c3a6a..ec8c2cbb8a4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.24 vpr 61.37 MiB -1 -1 -1 -1 0 0.01 -1 -1 35364 -1 -1 1 0 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 62844 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.9 MiB 0.00 0 3 0 0 3 61.4 MiB 0.00 0.00 nan 0 0 nan 0.00 1.0018e-05 5.139e-06 5.6154e-05 3.4203e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.00110329 0.000979672 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.00104785 0.00102177 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.24 vpr 61.98 MiB -1 -1 -1 -1 0 0.01 -1 -1 35496 -1 -1 1 0 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63464 -1 1 1 2 0 1 2 3 3 9 -1 auto 23.6 MiB 0.00 0 3 0 0 3 62.0 MiB 0.00 0.00 nan 0 0 nan 0.00 1.081e-05 5.871e-06 7.3257e-05 4.9954e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.00102207 0.000971097 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.00102052 0.000997346 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.24 vpr 62.13 MiB -1 -1 -1 -1 0 0.01 -1 -1 33460 -1 -1 1 0 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63620 6 1 1 8 0 1 8 3 3 9 -1 auto 23.8 MiB 0.00 0 21 0 11 10 62.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1842e-05 6.512e-06 6.6872e-05 4.1936e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.0010546 0.000994369 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.00106282 0.00102829 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.24 vpr 62.01 MiB -1 -1 -1 -1 0 0.01 -1 -1 33476 -1 -1 1 0 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63496 6 1 1 8 0 1 8 3 3 9 -1 auto 23.5 MiB 0.00 0 21 0 11 10 62.0 MiB 0.00 0.00 nan 0 0 nan 0.00 8.255e-06 4.478e-06 5.6015e-05 3.737e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.000971969 0.000926575 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.00100296 0.000981066 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.25 vpr 62.00 MiB -1 -1 -1 -1 1 0.01 -1 -1 35520 -1 -1 1 2 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63488 2 1 3 4 0 3 4 3 3 9 -1 auto 23.5 MiB 0.00 9 9 1 6 2 62.0 MiB 0.00 0.00 0.442454 -0.442454 -0.442454 nan 0.00 1.3495e-05 9.157e-06 8.8405e-05 6.5853e-05 14 21 16 3900 3900 2841.42 315.713 0.01 0.00139569 0.00123637 322 679 -1 5 2 5 5 74 52 0.59141 nan -0.59141 -0.59141 0 0 4264.82 473.869 0.00 0.00 0.00 -1 -1 0.00 0.00112433 0.00108767 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.30 vpr 62.01 MiB -1 -1 -1 -1 2 0.02 -1 -1 36328 -1 -1 1 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63496 5 1 7 8 0 7 7 3 3 9 -1 auto 23.8 MiB 0.00 20 18 7 7 4 62.0 MiB 0.00 0.00 0.701708 -0.701708 -0.701708 nan 0.00 2.3043e-05 1.7643e-05 0.000144409 0.000116247 18 14 6 3900 3900 4264.82 473.869 0.01 0.00197653 0.00164318 346 735 -1 22 18 51 51 2109 1776 1.33334 nan -1.33334 -1.33334 0 0 5011.22 556.802 0.00 0.00 0.00 -1 -1 0.00 0.00137266 0.00125138 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.30 vpr 62.14 MiB -1 -1 -1 -1 2 0.02 -1 -1 37616 -1 -1 1 5 0 0 success e1c7cb1 Release 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0.00 1.20682 -5.54363 -1.20682 nan 0.03 6.45e-05 5.6165e-05 0.000384815 0.000349871 24 291 50 23400 11700 20975.0 838.999 0.09 0.00832869 0.00689782 1420 4462 -1 203 23 273 1147 57568 24503 1.79815 nan -7.13942 -1.79815 0 0 27052.1 1082.08 0.01 0.01 0.00 -1 -1 0.01 0.00295877 0.00262608 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x4.blif common 0.47 vpr 62.28 MiB -1 -1 -1 -1 4 0.03 -1 -1 36000 -1 -1 5 7 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63776 7 8 39 47 0 39 20 5 5 25 clb auto 23.8 MiB 0.01 166 236 55 168 13 62.3 MiB 0.00 0.00 1.53492 -7.68167 -1.53492 nan 0.03 4.6517e-05 3.9854e-05 0.000757944 0.000671611 28 390 19 23400 19500 25328.9 1013.15 0.08 0.00830959 0.00701527 1476 4870 -1 345 18 424 1625 97221 41104 2.1436 nan -10.1282 -2.1436 0 0 29680.9 1187.23 0.01 0.02 0.00 -1 -1 0.01 0.00326751 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/home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64208 10 10 95 105 0 95 31 6 6 36 clb auto 24.3 MiB 0.01 458 607 80 489 38 62.7 MiB 0.01 0.00 2.54057 -18.2603 -2.54057 nan 0.05 0.000106788 9.1771e-05 0.00197953 0.00177718 38 1072 47 165600 42900 55946.4 1554.07 0.35 0.0265862 0.0226733 2940 12782 -1 863 20 990 4097 286923 104030 2.92618 nan -21.5852 -2.92618 0 0 73011.6 2028.10 0.02 0.04 0.01 -1 -1 0.02 0.0061451 0.00551558 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 1.00 vpr 62.84 MiB -1 -1 -1 -1 8 0.06 -1 -1 41536 -1 -1 11 11 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64344 11 11 94 105 0 94 33 6 6 36 clb auto 24.3 MiB 0.01 429 657 85 535 37 62.8 MiB 0.01 0.00 2.9648 -21.4457 -2.9648 nan 0.05 0.000103943 9.2442e-05 0.00200059 0.00180664 40 1112 36 165600 42900 61410.5 1705.85 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min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.29 vpr 60.09 MiB -1 -1 -1 -1 0 0.01 -1 -1 35140 -1 -1 1 0 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on 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-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index 3ff8dccb714..0a6d9b6d152 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.15 vpr 64.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66040 5 3 11 14 2 9 10 4 4 16 clb auto 26.1 MiB 0.00 22 30 9 14 7 64.5 MiB 0.00 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 3.4514e-05 2.6389e-05 0.000188251 0.000157435 8 18 2 107788 107788 4794.78 299.674 0.01 0.00136356 0.00126067 564 862 -1 18 4 10 10 213 96 0.757297 0.571 -2.63894 -0.757297 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00132991 0.0012563 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.15 vpr 64.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66172 5 3 11 14 2 9 10 4 4 16 clb auto 26.2 MiB 0.00 23 30 5 16 9 64.6 MiB 0.00 0.00 0.571 0 0 0.571 0.01 3.1699e-05 2.5357e-05 0.000167513 0.000139209 8 29 4 107788 107788 4794.78 299.674 0.01 0.00129724 0.00119452 564 862 -1 25 4 15 15 546 342 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00123336 0.00115491 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.15 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66304 5 3 11 14 2 9 10 4 4 16 clb auto 26.5 MiB 0.00 20 30 10 18 2 64.8 MiB 0.00 0.00 0.645499 -2.18826 -0.645499 0.571 0.01 5.5523e-05 4.2379e-05 0.000203498 0.000159839 8 17 3 107788 107788 4794.78 299.674 0.01 0.0014548 0.0013129 564 862 -1 14 4 15 15 278 103 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00123664 0.00115953 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.15 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66308 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 20 30 11 18 1 64.8 MiB 0.00 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 2.4636e-05 1.5899e-05 0.000174577 0.000131877 8 17 8 107788 107788 4794.78 299.674 0.01 0.00153355 0.00133955 564 862 -1 15 8 21 21 322 143 1.57153 0.571 -4.91875 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00136833 0.00125557 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.16 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66300 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 21 30 10 15 5 64.7 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 2.8303e-05 1.9276e-05 0.000183072 0.000124494 8 21 8 107788 107788 4794.78 299.674 0.01 0.00162656 0.00142678 564 862 -1 25 3 11 11 428 274 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0012549 0.00118367 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.15 vpr 64.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66232 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 21 100 23 56 21 64.7 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.9153e-05 3.219e-05 0.000324196 0.000258224 8 22 3 107788 107788 4794.78 299.674 0.01 0.00152952 0.00138796 564 862 -1 20 2 9 9 230 115 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00122034 0.00116368 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.26 vpr 63.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64544 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 22 30 9 14 7 63.0 MiB 0.00 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 3.21e-05 2.4325e-05 0.000202798 0.000163594 -1 -1 -1 -1 8 18 2 107788 107788 4794.78 299.674 0.01 0.00183578 0.00170245 564 862 -1 18 4 10 10 199 87 0.757297 0.571 -2.63894 -0.757297 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00182289 0.00172861 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.26 vpr 62.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64400 5 3 11 14 2 9 10 4 4 16 clb auto 24.4 MiB 0.00 23 30 5 16 9 62.9 MiB 0.00 0.00 0.571 0 0 0.571 0.01 2.7071e-05 2.112e-05 0.000180878 0.000149129 -1 -1 -1 -1 8 27 3 107788 107788 4794.78 299.674 0.01 0.00188235 0.00175706 564 862 -1 25 5 14 14 430 265 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00179432 0.00170513 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.26 vpr 62.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64360 5 3 11 14 2 9 10 4 4 16 clb auto 24.5 MiB 0.00 20 30 10 18 2 62.9 MiB 0.00 0.00 0.645658 -2.18842 -0.645658 0.571 0.01 3.7729e-05 2.5928e-05 0.000260113 0.000177741 -1 -1 -1 -1 8 17 3 107788 107788 4794.78 299.674 0.01 0.00195031 0.00174505 564 862 -1 14 5 15 15 285 110 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00183013 0.00171342 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.26 vpr 62.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64484 5 3 11 14 2 9 10 4 4 16 clb auto 24.5 MiB 0.00 20 30 11 18 1 63.0 MiB 0.00 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 3.8442e-05 2.5618e-05 0.00023637 0.000176478 -1 -1 -1 -1 8 17 8 107788 107788 4794.78 299.674 0.01 0.00229296 0.00202345 564 862 -1 15 8 21 21 324 150 1.57153 0.571 -4.91875 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00192818 0.00176248 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.26 vpr 62.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64408 5 3 11 14 2 9 10 4 4 16 clb auto 24.4 MiB 0.01 20 30 8 18 4 62.9 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 4.1447e-05 3.1048e-05 0.000250166 0.000200113 -1 -1 -1 -1 8 33 10 107788 107788 4794.78 299.674 0.01 0.0023527 0.00209277 564 862 -1 19 2 11 11 275 141 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00169051 0.00161308 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.25 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64488 5 3 11 14 2 9 10 4 4 16 clb auto 24.5 MiB 0.00 21 100 23 56 21 63.0 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.0426e-05 2.4245e-05 0.000455896 0.00036643 -1 -1 -1 -1 8 22 3 107788 107788 4794.78 299.674 0.01 0.00222626 0.00202944 564 862 -1 20 2 9 9 213 106 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00168704 0.00161249 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt index e20a70078a0..cd1c68f4910 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 0.81 vpr 65.85 MiB 0.01 6016 -1 -1 1 0.01 -1 -1 35776 -1 -1 3 9 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67428 9 8 71 66 1 35 20 5 5 25 clb auto 27.4 MiB 0.36 107 182 46 135 1 65.8 MiB 0.00 0.00 2.68643 -28.4013 -2.68643 2.68643 0.02 6.5012e-05 5.6766e-05 0.00123208 0.00115463 36 185 13 151211 75605.7 46719.2 1868.77 0.10 0.0225451 0.0190652 2052 7582 -1 146 10 108 137 4740 2447 2.68643 2.68643 -31.0287 -2.68643 0 0 57775.2 2311.01 0.00 0.01 0.01 -1 -1 0.00 0.00385153 0.00361726 14 17 16 6 0 0 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 2.78 vpr 66.76 MiB 0.01 6272 -1 -1 1 0.01 -1 -1 33876 -1 -1 8 19 0 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68364 19 18 299 240 1 150 45 6 6 36 clb auto 28.4 MiB 2.04 535 3885 1278 2560 47 66.8 MiB 0.03 0.00 4.80824 -97.5504 -4.80824 4.80824 0.04 0.000220352 0.000197239 0.013825 0.0125729 50 962 24 403230 201615 107229. 2978.57 0.20 0.0646538 0.0570817 3946 19047 -1 817 19 675 1076 42248 16898 5.14316 5.14316 -107.229 -5.14316 0 0 134937. 3748.26 0.01 0.02 0.01 -1 -1 0.01 0.0147259 0.0137101 62 82 85 13 0 0 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.21 vpr 63.90 MiB 0.01 5888 -1 -1 1 0.02 -1 -1 35760 -1 -1 3 9 0 -1 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65436 9 8 71 66 1 35 20 5 5 25 clb auto 25.5 MiB 0.55 102 371 120 247 4 63.9 MiB 0.01 0.00 2.68643 -28.5368 -2.68643 2.68643 0.03 0.000105979 9.1341e-05 0.00248903 0.00227506 -1 -1 -1 -1 34 229 25 151211 75605.7 45067.1 1802.68 0.09 0.022787 0.019687 2028 7167 -1 171 16 182 242 7354 3960 3.16043 3.16043 -38.0845 -3.16043 0 0 54748.7 2189.95 0.01 0.01 0.01 -1 -1 0.01 0.00650462 0.00600276 14 17 16 6 0 0 + k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 5.11 vpr 65.14 MiB 0.01 6144 -1 -1 1 0.02 -1 -1 34136 -1 -1 8 19 0 -1 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66708 19 18 299 240 1 150 45 6 6 36 clb auto 26.9 MiB 3.57 505 2525 548 1948 29 65.1 MiB 0.04 0.00 4.80824 -97.6181 -4.80824 4.80824 0.06 0.000351768 0.000312054 0.0152117 0.0138406 -1 -1 -1 -1 68 855 19 403230 201615 143382. 3982.83 0.68 0.159122 0.139456 4366 25715 -1 697 19 708 1171 41239 15710 5.0764 5.0764 -103.347 -5.0764 0 0 176130. 4892.50 0.02 0.04 0.03 -1 -1 0.02 0.0232049 0.021551 62 82 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt index 67438b42e30..b5f2f1a2242 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 4.81 vpr 207.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 5941692-dirty release IPO VTR_ASSERT_LEVEL=3 sanitizers GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-27T23:00:35 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 63825 2 2 22 24 2 4 6 4 4 16 clb auto 51.5 MiB 0.10 4 15 2 10 3 192.8 MiB 0.02 0.00 1.297 0 0 1.297 0.49 0.000472548 0.000433891 0.00258794 0.00211333 4 6 2 72000 36000 2827.54 176.721 1.75 0.0226752 0.0196524 644 852 -1 6 2 4 4 138 80 1.297 1.297 0 0 0 0 4025.56 251.598 0.01 0.02 0.16 -1 -1 0.01 0.00604643 0.0051332 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.20 vpr 57.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 59056 2 2 22 24 2 4 6 4 4 16 clb auto 19.2 MiB 0.00 8 15 5 8 2 57.7 MiB 0.00 0.00 1.297 0 0 1.297 0.01 4.7147e-05 3.8732e-05 0.000324416 0.000284392 -1 -1 -1 -1 6 13 3 72000 36000 4025.56 251.598 0.01 0.00265373 0.002411 660 1032 -1 12 5 7 7 429 325 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00202488 0.00190683 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt index 377804dd2e9..67f054d3173 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.27 vpr 66.64 MiB 0.03 9984 -1 -1 4 0.11 -1 -1 40356 -1 -1 19 11 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 68240 11 30 262 292 2 104 60 7 7 49 clb auto 27.9 MiB 0.04 534 1698 67 1561 70 66.6 MiB 0.02 0.00 2.46229 -183.132 -2.46229 2.30786 0.05 0.000271357 0.000227515 0.00621294 0.00543836 20 762 38 1.07788e+06 1.02399e+06 49980.0 1020.00 0.44 0.121211 0.10048 2664 9102 -1 658 40 1163 2905 97572 29592 2.48064 2.28958 -187.312 -2.48064 0 0 65453.8 1335.79 0.01 0.05 0.01 -1 -1 0.01 0.0255642 0.0220947 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_N10_mem32K_40nm.xml stereovision3.v common 1.89 vpr 64.95 MiB 0.05 10112 -1 -1 4 0.17 -1 -1 38408 -1 -1 19 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66512 11 30 262 292 2 104 60 7 7 49 clb auto 26.2 MiB 0.07 543 1815 85 1663 67 65.0 MiB 0.04 0.00 2.42365 -183.03 -2.42365 2.30003 0.08 0.000468706 0.000384899 0.0139664 0.0124455 -1 -1 -1 -1 32 636 29 1.07788e+06 1.02399e+06 77018.1 1571.80 0.55 0.184182 0.153846 3048 13294 -1 584 18 615 1453 47899 13726 2.38789 2.24182 -185.883 -2.38789 0 0 93715.6 1912.56 0.02 0.04 0.01 -1 -1 0.02 0.0242388 0.0214475 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt index 3b5280c3ab4..e6e7c8778e5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 3.18 vpr 61.45 MiB 0.07 9776 -1 -1 4 0.18 -1 -1 33272 -1 -1 13 11 0 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 62924 11 30 262 292 2 110 54 7 7 49 clb auto 23.0 MiB 0.20 397 61.4 MiB 0.11 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000592895 0.000508012 0.013785 0.0121915 14 321 2 1.07788e+06 700622 -1 -1 0.71 0.102337 0.0909925 324 2 143 217 16065 6700 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.0156335 0.0151149 - x_uniform_y_gaussian.xml stereovision3.v common 3.13 vpr 61.90 MiB 0.07 9808 -1 -1 4 0.16 -1 -1 33268 -1 -1 13 11 0 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 63388 11 30 262 292 2 110 54 7 7 49 clb auto 23.5 MiB 0.33 396 61.9 MiB 0.11 0.00 1.91988 -135.359 -1.91988 1.85222 0.02 0.000622741 0.000541242 0.0134697 0.0117154 10 340 8 1.07788e+06 700622 -1 -1 0.71 0.0930003 0.0824859 325 3 176 260 20160 8504 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.05 0.0171543 0.016409 - x_gaussian_y_gaussian.xml stereovision3.v common 3.08 vpr 61.63 MiB 0.07 9880 -1 -1 4 0.18 -1 -1 33236 -1 -1 13 11 0 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 63108 11 30 262 292 2 110 54 7 7 49 clb auto 23.2 MiB 0.36 395 61.6 MiB 0.11 0.00 1.91988 -135.359 -1.91988 1.85222 0.02 0.000476461 0.000398681 0.0156876 0.0137495 14 328 3 1.07788e+06 700622 -1 -1 0.55 0.0972827 0.0870043 324 2 146 217 15436 6346 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.07 0.0137984 0.0132152 - x_delta_y_uniform.xml stereovision3.v common 3.13 vpr 61.68 MiB 0.06 10084 -1 -1 4 0.18 -1 -1 33212 -1 -1 13 11 0 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 63156 11 30 262 292 2 110 54 7 7 49 clb auto 23.2 MiB 0.28 392 61.7 MiB 0.07 0.00 1.91988 -135.359 -1.91988 1.85222 0.03 0.000551726 0.00047922 0.0214832 0.0193278 54 311 11 1.07788e+06 700622 -1 -1 0.74 0.156932 0.137837 311 2 140 210 13011 5434 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.06 0.0133677 0.0128658 - x_delta_y_delta.xml stereovision3.v common 3.46 vpr 61.80 MiB 0.10 9936 -1 -1 4 0.15 -1 -1 33220 -1 -1 13 11 0 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 63288 11 30 262 292 2 110 54 7 7 49 clb auto 23.3 MiB 0.31 362 61.8 MiB 0.07 0.00 1.91988 -135.359 -1.91988 1.85222 0.03 0.000339761 0.000277964 0.0165305 0.0143473 48 279 10 1.07788e+06 700622 -1 -1 0.99 0.178847 0.156353 274 4 198 287 18668 7356 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.04 0.0174239 0.0165747 - x_uniform_y_delta.xml stereovision3.v common 3.30 vpr 61.55 MiB 0.08 9872 -1 -1 4 0.20 -1 -1 33396 -1 -1 13 11 0 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 63032 11 30 262 292 2 110 54 7 7 49 clb auto 23.1 MiB 0.22 351 61.6 MiB 0.23 0.00 1.91988 -135.359 -1.91988 1.85222 0.03 0.000595612 0.000510755 0.0233039 0.0203167 44 267 11 1.07788e+06 700622 -1 -1 0.84 0.169621 0.149371 267 2 147 222 13334 5190 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.06 0.0156514 0.0150841 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + x_gaussian_y_uniform.xml stereovision3.v common 1.42 vpr 65.81 MiB 0.05 9984 -1 -1 4 0.17 -1 -1 37836 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67388 11 30 262 292 2 110 54 7 7 49 clb auto 27.0 MiB 0.12 431 2298 449 1774 75 65.8 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000483914 0.000384949 0.0147089 0.012636 -1 -1 -1 -1 12 326 3 1.07788e+06 700622 -1 -1 0.20 0.0742174 0.0638404 2680 3516 -1 316 3 175 255 10988 5508 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0145719 0.0139138 + x_uniform_y_gaussian.xml stereovision3.v common 1.44 vpr 65.54 MiB 0.05 9856 -1 -1 4 0.17 -1 -1 37820 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67108 11 30 262 292 2 110 54 7 7 49 clb auto 26.9 MiB 0.11 392 1890 346 1476 68 65.5 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000458868 0.000376323 0.0123402 0.0106294 -1 -1 -1 -1 12 287 5 1.07788e+06 700622 -1 -1 0.21 0.0867101 0.074128 2680 3516 -1 268 3 167 248 10043 4782 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.015461 0.0147632 + x_gaussian_y_gaussian.xml stereovision3.v common 1.50 vpr 65.58 MiB 0.05 9984 -1 -1 4 0.17 -1 -1 37476 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67156 11 30 262 292 2 110 54 7 7 49 clb auto 26.9 MiB 0.12 398 2196 430 1697 69 65.6 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000468656 0.000387965 0.0139473 0.0119918 -1 -1 -1 -1 12 284 8 1.07788e+06 700622 -1 -1 0.28 0.0788417 0.0678402 2680 3516 -1 273 3 184 266 11521 5744 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0151497 0.0144591 + x_delta_y_uniform.xml stereovision3.v common 1.67 vpr 65.78 MiB 0.05 9984 -1 -1 4 0.17 -1 -1 40712 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67356 11 30 262 292 2 110 54 7 7 49 clb auto 27.0 MiB 0.11 474 1992 348 1574 70 65.8 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000450631 0.000369149 0.0127092 0.0109666 -1 -1 -1 -1 48 367 4 1.07788e+06 700622 -1 -1 0.46 0.187113 0.157611 2680 3516 -1 363 2 162 240 11458 5656 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0141159 0.0135524 + x_delta_y_delta.xml stereovision3.v common 1.41 vpr 65.68 MiB 0.05 9984 -1 -1 4 0.17 -1 -1 38292 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67260 11 30 262 292 2 110 54 7 7 49 clb auto 26.9 MiB 0.12 411 2094 373 1653 68 65.7 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000478875 0.000382715 0.0140865 0.0122714 -1 -1 -1 -1 48 306 4 1.07788e+06 700622 -1 -1 0.20 0.107373 0.0919185 2680 3516 -1 300 3 176 263 11898 5867 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.014938 0.0142467 + x_uniform_y_delta.xml stereovision3.v common 1.47 vpr 65.57 MiB 0.05 9984 -1 -1 4 0.17 -1 -1 37488 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67144 11 30 262 292 2 110 54 7 7 49 clb auto 26.9 MiB 0.11 405 2196 394 1718 84 65.6 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000448588 0.000370342 0.0136716 0.0117962 -1 -1 -1 -1 58 286 2 1.07788e+06 700622 -1 -1 0.28 0.112457 0.0956247 2680 3516 -1 286 2 161 239 8848 4226 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0140539 0.0134498 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt index 14c7bba32a0..aa786b4ddf8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59823 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59823 -1 1.07141 -1 1.75805 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44686 -1 3.30941 -1 -1.48832 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.07141 -1 1.37913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.30941 -1 -1.86724 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/config.txt index cd08958fd4c..fbdf4b90a3e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/config.txt @@ -44,4 +44,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt #Script parameters -script_params=-track_memory_usage -check_equivalent -starting_stage abc --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --seed 5 +script_params=-track_memory_usage -check_equivalent -starting_stage abc --gen_post_synthesis_netlist on --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --route_chan_width 40 --seed 5 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt index 7dfb524615c..a3d3b0a40d7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.23 vpr 62.12 MiB -1 -1 -1 -1 0 0.01 -1 -1 33488 -1 -1 1 0 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63612 -1 1 1 2 0 1 2 3 3 9 -1 auto 23.6 MiB 0.00 0 3 0 0 3 62.1 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2454e-05 7.204e-06 6.5813e-05 4.3372e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.000972617 0.000911483 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.000976033 0.000955064 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.23 vpr 61.88 MiB -1 -1 -1 -1 0 0.01 -1 -1 33108 -1 -1 1 0 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63360 -1 1 1 2 0 1 2 3 3 9 -1 auto 23.6 MiB 0.00 0 3 0 0 3 61.9 MiB 0.00 0.00 nan 0 0 nan 0.00 1.0189e-05 5.38e-06 6.5013e-05 4.235e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.000924047 0.000874774 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.00135636 0.00132808 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.25 vpr 62.00 MiB -1 -1 -1 -1 0 0.01 -1 -1 35092 -1 -1 1 0 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63488 6 1 1 8 0 1 8 3 3 9 -1 auto 23.6 MiB 0.00 0 21 0 11 10 62.0 MiB 0.00 0.00 nan 0 0 nan 0.00 1.08e-05 5.891e-06 9.4257e-05 6.8679e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.000991463 0.000932092 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.000976666 0.000955045 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.25 vpr 62.00 MiB -1 -1 -1 -1 0 0.01 -1 -1 33476 -1 -1 1 0 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63492 6 1 1 8 0 1 8 3 3 9 -1 auto 23.5 MiB 0.00 0 21 0 11 10 62.0 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2183e-05 6.672e-06 6.8478e-05 4.4622e-05 2 0 1 3900 3900 966.985 107.443 0.00 0.00104759 0.000996631 258 293 -1 0 1 0 0 0 0 nan nan 0 0 0 0 966.985 107.443 0.00 0.00 0.00 -1 -1 0.00 0.00114576 0.00111767 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.24 vpr 61.92 MiB -1 -1 -1 -1 1 0.01 -1 -1 35380 -1 -1 1 2 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63404 2 1 3 4 0 3 4 3 3 9 -1 auto 23.6 MiB 0.00 9 9 1 6 2 61.9 MiB 0.00 0.00 0.442454 -0.442454 -0.442454 nan 0.00 7.794e-06 4.839e-06 6.5711e-05 4.8199e-05 14 21 16 3900 3900 2841.42 315.713 0.01 0.00129465 0.0011587 322 679 -1 5 2 5 5 74 52 0.59141 nan -0.59141 -0.59141 0 0 4264.82 473.869 0.00 0.00 0.00 -1 -1 0.00 0.00104874 0.000997054 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.30 vpr 62.01 MiB -1 -1 -1 -1 2 0.02 -1 -1 36492 -1 -1 1 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63500 5 1 7 8 0 7 7 3 3 9 -1 auto 23.6 MiB 0.00 20 18 7 7 4 62.0 MiB 0.00 0.00 0.701708 -0.701708 -0.701708 nan 0.00 1.2073e-05 8.717e-06 9.5529e-05 7.6535e-05 18 14 6 3900 3900 4264.82 473.869 0.01 0.0019632 0.00159343 346 735 -1 22 18 51 51 2109 1776 1.33334 nan -1.33334 -1.33334 0 0 5011.22 556.802 0.00 0.00 0.00 -1 -1 0.00 0.0013234 0.00120622 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.30 vpr 62.14 MiB -1 -1 -1 -1 2 0.02 -1 -1 37492 -1 -1 1 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63628 5 1 7 8 0 7 7 3 3 9 -1 auto 23.8 MiB 0.00 20 18 8 7 3 62.1 MiB 0.00 0.00 0.701708 -0.701708 -0.701708 nan 0.00 1.2693e-05 9.347e-06 0.000116254 9.5757e-05 14 23 9 3900 3900 2841.42 315.713 0.01 0.00163861 0.00145246 322 679 -1 18 9 22 22 577 440 1.23352 nan -1.23352 -1.23352 0 0 4264.82 473.869 0.00 0.00 0.00 -1 -1 0.00 0.00125101 0.00116254 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.22 vpr 62.13 MiB -1 -1 -1 -1 1 0.01 -1 -1 33624 -1 -1 1 3 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63624 3 1 5 6 1 4 5 3 3 9 -1 auto 23.8 MiB 0.00 9 12 5 3 4 62.1 MiB 0.00 0.00 0.274843 -0.535084 -0.274843 0.274843 0.00 9.998e-06 6.843e-06 9.171e-05 7.2575e-05 14 20 4 3900 3900 2841.42 315.713 0.01 0.00157941 0.00147902 322 679 -1 6 1 3 3 67 52 0.411504 0.411504 -0.743397 -0.411504 0 0 4264.82 473.869 0.00 0.00 0.00 -1 -1 0.00 0.00101855 0.000992124 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.28 vpr 62.14 MiB -1 -1 -1 -1 1 0.02 -1 -1 35792 -1 -1 1 3 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63628 4 1 4 6 0 4 6 3 3 9 -1 auto 23.8 MiB 0.00 12 15 5 4 6 62.1 MiB 0.00 0.00 0.442454 -0.442454 -0.442454 nan 0.00 1.8294e-05 1.3074e-05 8.2594e-05 6.1684e-05 12 10 13 3900 3900 2582.62 286.957 0.00 0.00129752 0.00116274 314 651 -1 5 1 4 4 82 62 0.529227 nan -0.529227 -0.529227 0 0 3970.02 441.113 0.00 0.00 0.00 -1 -1 0.00 0.000989778 0.000966254 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_2x2.blif common 0.21 vpr 62.05 MiB -1 -1 -1 -1 1 0.02 -1 -1 36024 -1 -1 1 4 0 0 exited with return code 2 e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63540 4 4 8 12 0 8 9 3 3 9 -1 auto 23.8 MiB 0.00 25 27 10 13 4 62.1 MiB 0.00 0.00 0.442454 -1.76982 -0.442454 nan 0.00 1.5989e-05 1.2313e-05 0.000135973 0.000114855 20 42 18 3900 3900 4445.42 493.935 0.01 0.00271823 0.00218574 354 763 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00 0.00 0.00 -1 -1 0.00 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x3.blif common 0.45 vpr 62.33 MiB -1 -1 -1 -1 3 0.03 -1 -1 37348 -1 -1 3 6 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63824 6 6 28 34 0 28 15 5 5 25 clb auto 23.9 MiB 0.00 103 51 16 35 0 62.3 MiB 0.00 0.00 1.20682 -5.54363 -1.20682 nan 0.03 6.5532e-05 5.6345e-05 0.000362477 0.000328062 24 291 50 23400 11700 20975.0 838.999 0.09 0.00842523 0.00696631 1420 4462 -1 203 23 273 1147 57568 24503 1.79815 nan -7.13942 -1.79815 0 0 27052.1 1082.08 0.01 0.01 0.00 -1 -1 0.01 0.00303588 0.00269461 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x4.blif common 0.46 vpr 62.28 MiB -1 -1 -1 -1 4 0.03 -1 -1 38016 -1 -1 5 7 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63776 7 8 39 47 0 39 20 5 5 25 clb auto 23.8 MiB 0.01 166 236 55 168 13 62.3 MiB 0.00 0.00 1.53492 -7.68167 -1.53492 nan 0.03 6.2787e-05 5.5644e-05 0.000904391 0.000813461 28 390 19 23400 19500 25328.9 1013.15 0.09 0.00844921 0.00711013 1476 4870 -1 345 18 424 1625 97221 41104 2.1436 nan -10.1282 -2.1436 0 0 29680.9 1187.23 0.01 0.02 0.00 -1 -1 0.01 0.00324908 0.00290646 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_4x4.blif common 0.92 vpr 62.48 MiB -1 -1 -1 -1 8 0.04 -1 -1 38280 -1 -1 7 8 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63976 8 8 51 59 0 51 23 6 6 36 clb auto 24.1 MiB 0.01 218 87 23 62 2 62.5 MiB 0.00 0.00 2.65232 -12.8401 -2.65232 nan 0.05 0.00010712 9.623e-05 0.000592006 0.000547633 28 635 50 165600 27300 45013.2 1250.37 0.45 0.0231976 0.0192994 2604 9324 -1 531 20 525 2156 148800 55475 3.2769 nan -17.2194 -3.2769 0 0 53593.6 1488.71 0.01 0.02 0.01 -1 -1 0.01 0.00401954 0.00358337 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.96 vpr 62.47 MiB -1 -1 -1 -1 7 0.05 -1 -1 38160 -1 -1 11 10 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63972 10 10 95 105 0 95 31 6 6 36 clb auto 24.0 MiB 0.01 458 607 80 489 38 62.5 MiB 0.01 0.00 2.54057 -18.2603 -2.54057 nan 0.05 0.000103744 8.9057e-05 0.00195849 0.0017585 38 1072 47 165600 42900 55946.4 1554.07 0.41 0.0295403 0.0251736 2940 12782 -1 863 20 990 4097 286923 104030 2.92618 nan -21.5852 -2.92618 0 0 73011.6 2028.10 0.02 0.04 0.01 -1 -1 0.02 0.00612337 0.00548198 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 0.98 vpr 62.71 MiB -1 -1 -1 -1 8 0.05 -1 -1 40416 -1 -1 11 11 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64216 11 11 94 105 0 94 33 6 6 36 clb auto 24.2 MiB 0.01 429 657 85 535 37 62.7 MiB 0.01 0.00 2.9648 -21.4457 -2.9648 nan 0.05 0.000161302 0.000148878 0.00224002 0.00203969 40 1112 36 165600 42900 61410.5 1705.85 0.42 0.0287244 0.0244922 2992 13730 -1 884 19 850 3542 252924 89086 3.47123 nan -25.0388 -3.47123 0 0 78756.9 2187.69 0.02 0.04 0.01 -1 -1 0.02 0.0059244 0.00528593 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_1bit.blif common 0.28 vpr 62.14 MiB -1 -1 -1 -1 1 0.02 -1 -1 38728 -1 -1 1 3 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63628 3 2 5 7 0 5 6 3 3 9 -1 auto 23.8 MiB 0.00 15 15 8 4 3 62.1 MiB 0.00 0.00 0.442454 -0.884909 -0.442454 nan 0.00 1.9005e-05 1.4186e-05 0.000116908 9.2382e-05 16 26 17 3900 3900 3970.02 441.113 0.01 0.00138483 0.00123021 330 691 -1 24 12 34 59 1656 1302 0.897144 nan -1.78596 -0.897144 0 0 4445.42 493.935 0.00 0.00 0.00 -1 -1 0.00 0.00126285 0.0011792 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.31 vpr 62.17 MiB -1 -1 -1 -1 2 0.02 -1 -1 37736 -1 -1 1 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63660 5 3 9 12 0 9 9 3 3 9 -1 auto 23.6 MiB 0.00 26 27 10 10 7 62.2 MiB 0.00 0.00 0.701708 -1.84587 -0.701708 nan 0.00 2.9094e-05 2.3013e-05 0.000162313 0.000137477 20 41 14 3900 3900 4445.42 493.935 0.03 0.00470101 0.00358969 354 763 -1 62 23 83 142 5466 4364 2.28942 nan -4.87234 -2.28942 0 0 5185.22 576.135 0.00 0.00 0.00 -1 -1 0.00 0.00167993 0.00148994 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.30 vpr 62.08 MiB -1 -1 -1 -1 3 0.02 -1 -1 37368 -1 -1 1 7 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63572 7 4 13 17 0 13 12 3 3 9 -1 auto 23.6 MiB 0.00 37 38 21 15 2 62.1 MiB 0.00 0.00 0.960961 -3.06608 -0.960961 nan 0.00 3.4835e-05 2.8744e-05 0.00021968 0.000193231 24 55 20 3900 3900 5011.22 556.802 0.02 0.0034395 0.00281572 378 957 -1 47 16 74 136 4091 2875 1.45584 nan -4.58947 -1.45584 0 0 6337.42 704.157 0.00 0.00 0.00 -1 -1 0.00 0.00168199 0.00150036 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.30 vpr 62.23 MiB -1 -1 -1 -1 4 0.03 -1 -1 37876 -1 -1 1 9 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63728 9 5 17 22 0 17 15 3 3 9 -1 auto 23.8 MiB 0.00 48 51 31 11 9 62.2 MiB 0.00 0.00 1.22021 -4.54555 -1.22021 nan 0.00 2.4027e-05 1.9828e-05 0.000203142 0.000178704 28 55 17 3900 3900 5935.82 659.535 0.01 0.00360742 0.00299184 394 1003 -1 58 13 87 148 4928 3501 1.86558 nan -6.3789 -1.86558 0 0 6854.42 761.602 0.00 0.00 0.00 -1 -1 0.00 0.00173866 0.00159953 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.39 vpr 62.16 MiB -1 -1 -1 -1 4 0.03 -1 -1 39264 -1 -1 2 11 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 63652 11 6 24 30 0 24 19 4 4 16 clb auto 23.8 MiB 0.00 85 69 11 46 12 62.2 MiB 0.00 0.00 1.38419 -6.92615 -1.38419 nan 0.01 3.5296e-05 2.8123e-05 0.000285254 0.000254216 28 127 18 7800 7800 12557.4 784.840 0.07 0.00805822 0.00657388 812 2356 -1 155 18 208 453 20911 11455 1.85994 nan -8.56093 -1.85994 0 0 14986.4 936.652 0.00 0.01 0.00 -1 -1 0.00 0.00224724 0.00199391 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.29 vpr 60.26 MiB -1 -1 -1 -1 0 0.01 -1 -1 33120 -1 -1 1 0 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61704 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.9 MiB 0.00 0 3 0 0 3 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2243e-05 6.312e-06 7.1764e-05 4.4203e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00136779 0.00130369 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.29 vpr 59.90 MiB -1 -1 -1 -1 0 0.01 -1 -1 33592 -1 -1 1 0 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61340 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.6 MiB 0.00 0 3 0 0 3 59.9 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1612e-05 6.272e-06 7.7714e-05 5.1887e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00142631 0.00136526 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt index 3ff8dccb714..962dab28b44 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.15 vpr 64.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66040 5 3 11 14 2 9 10 4 4 16 clb auto 26.1 MiB 0.00 22 30 9 14 7 64.5 MiB 0.00 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 3.4514e-05 2.6389e-05 0.000188251 0.000157435 8 18 2 107788 107788 4794.78 299.674 0.01 0.00136356 0.00126067 564 862 -1 18 4 10 10 213 96 0.757297 0.571 -2.63894 -0.757297 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00132991 0.0012563 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.15 vpr 64.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66172 5 3 11 14 2 9 10 4 4 16 clb auto 26.2 MiB 0.00 23 30 5 16 9 64.6 MiB 0.00 0.00 0.571 0 0 0.571 0.01 3.1699e-05 2.5357e-05 0.000167513 0.000139209 8 29 4 107788 107788 4794.78 299.674 0.01 0.00129724 0.00119452 564 862 -1 25 4 15 15 546 342 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00123336 0.00115491 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.15 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66304 5 3 11 14 2 9 10 4 4 16 clb auto 26.5 MiB 0.00 20 30 10 18 2 64.8 MiB 0.00 0.00 0.645499 -2.18826 -0.645499 0.571 0.01 5.5523e-05 4.2379e-05 0.000203498 0.000159839 8 17 3 107788 107788 4794.78 299.674 0.01 0.0014548 0.0013129 564 862 -1 14 4 15 15 278 103 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00123664 0.00115953 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.15 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66308 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 20 30 11 18 1 64.8 MiB 0.00 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 2.4636e-05 1.5899e-05 0.000174577 0.000131877 8 17 8 107788 107788 4794.78 299.674 0.01 0.00153355 0.00133955 564 862 -1 15 8 21 21 322 143 1.57153 0.571 -4.91875 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00136833 0.00125557 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.16 vpr 64.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66300 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 21 30 10 15 5 64.7 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 2.8303e-05 1.9276e-05 0.000183072 0.000124494 8 21 8 107788 107788 4794.78 299.674 0.01 0.00162656 0.00142678 564 862 -1 25 3 11 11 428 274 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0012549 0.00118367 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.15 vpr 64.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 66232 5 3 11 14 2 9 10 4 4 16 clb auto 26.3 MiB 0.00 21 100 23 56 21 64.7 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.9153e-05 3.219e-05 0.000324196 0.000258224 8 22 3 107788 107788 4794.78 299.674 0.01 0.00152952 0.00138796 564 862 -1 20 2 9 9 230 115 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00122034 0.00116368 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.25 vpr 63.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64552 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 22 30 9 14 7 63.0 MiB 0.00 0.00 0.814339 -2.77068 -0.814339 0.571 0.01 3.3273e-05 2.5789e-05 0.000195305 0.000156493 -1 -1 -1 -1 8 18 2 107788 107788 4794.78 299.674 0.01 0.00191594 0.00178193 564 862 -1 18 4 10 10 199 87 0.757297 0.571 -2.63894 -0.757297 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0017257 0.00162955 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.25 vpr 62.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64304 5 3 11 14 2 9 10 4 4 16 clb auto 24.5 MiB 0.00 23 30 5 16 9 62.8 MiB 0.00 0.00 0.571 0 0 0.571 0.01 2.9394e-05 2.3103e-05 0.000166559 0.000136184 -1 -1 -1 -1 8 27 3 107788 107788 4794.78 299.674 0.01 0.00191206 0.00174692 564 862 -1 25 5 14 14 430 265 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00178866 0.00169955 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.25 vpr 63.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64612 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 20 30 10 18 2 63.1 MiB 0.00 0.00 0.645658 -2.18842 -0.645658 0.571 0.01 3.9483e-05 2.7812e-05 0.000241821 0.000190264 -1 -1 -1 -1 8 17 3 107788 107788 4794.78 299.674 0.01 0.00193712 0.00176247 564 862 -1 14 5 15 15 285 110 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00179303 0.00167797 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.25 vpr 62.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64500 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 20 30 11 18 1 63.0 MiB 0.00 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 4.3501e-05 2.9475e-05 0.000247333 0.000183292 -1 -1 -1 -1 8 17 8 107788 107788 4794.78 299.674 0.01 0.00222242 0.00195057 564 862 -1 15 8 21 21 324 150 1.57153 0.571 -4.91875 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0019705 0.00180493 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.25 vpr 63.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64536 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 20 30 8 18 4 63.0 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 4.0285e-05 2.9986e-05 0.000237512 0.000186077 -1 -1 -1 -1 8 33 10 107788 107788 4794.78 299.674 0.01 0.00230311 0.00203041 564 862 -1 19 2 11 11 275 141 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00171065 0.00163028 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.24 vpr 62.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64376 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 21 100 23 56 21 62.9 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.1088e-05 2.4636e-05 0.000450966 0.000361847 -1 -1 -1 -1 8 22 3 107788 107788 4794.78 299.674 0.01 0.00226169 0.0020643 564 862 -1 20 2 9 9 213 106 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00164492 0.00157611 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt index b2d88760d9f..bc9ec03821b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.65 vpr 62.42 MiB 0.02 6244 -1 -1 1 0.03 -1 -1 30092 -1 -1 3 9 0 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63916 9 8 75 70 1 36 20 5 5 25 clb auto 23.8 MiB 0.53 81 290 96 193 1 62.4 MiB 0.01 0.00 2.64007 -27.5319 -2.64007 2.64007 0.03 0.000286892 0.000265466 0.00417798 0.00390875 44 134 16 151211 75605.7 54748.7 2189.95 0.27 0.0802385 0.0697674 2196 9177 -1 138 14 129 140 4385 2259 2.64007 2.64007 -32.9995 -2.64007 0 0 71025.7 2841.03 0.01 0.02 0.01 -1 -1 0.01 0.0102672 0.00927022 13 18 19 7 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 3.51 vpr 62.67 MiB 0.03 6144 -1 -1 1 0.02 -1 -1 30152 -1 -1 2 11 0 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64176 11 10 108 97 1 47 23 4 4 16 clb auto 24.1 MiB 2.52 110 119 41 58 20 62.7 MiB 0.01 0.00 3.45122 -42.0432 -3.45122 3.45122 0.02 0.00040098 0.000372114 0.00301776 0.00286337 34 232 28 50403.8 50403.8 21558.4 1347.40 0.19 0.0915775 0.0804679 1020 3049 -1 176 19 195 278 7163 4170 3.67968 3.67968 -49.4902 -3.67968 0 0 26343.3 1646.46 0.00 0.03 0.01 -1 -1 0.00 0.0171347 0.0154135 15 27 29 8 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 5.69 vpr 63.01 MiB 0.02 6184 -1 -1 1 0.02 -1 -1 30504 -1 -1 6 13 0 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64524 13 12 149 129 1 70 31 5 5 25 clb auto 24.4 MiB 4.28 174 847 168 658 21 63.0 MiB 0.02 0.00 3.51316 -52.7791 -3.51316 3.51316 0.03 0.000536862 0.000499181 0.0116677 0.0109304 62 271 18 151211 151211 75076.4 3003.05 0.48 0.179803 0.159314 2460 12058 -1 233 14 285 358 11388 5337 3.27616 3.27616 -51.4022 -3.27616 0 0 92558.6 3702.35 0.01 0.03 0.02 -1 -1 0.01 0.0186299 0.0169676 24 38 42 9 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 3.39 vpr 63.38 MiB 0.03 6232 -1 -1 1 0.05 -1 -1 30156 -1 -1 6 15 0 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64900 15 14 196 165 1 95 35 5 5 25 clb auto 24.9 MiB 2.07 285 2999 874 2055 70 63.4 MiB 0.06 0.00 3.87456 -65.0363 -3.87456 3.87456 0.03 0.000687139 0.000638718 0.0389859 0.0363394 40 532 34 151211 151211 50368.7 2014.75 0.36 0.199043 0.178709 2124 8279 -1 477 17 466 627 22181 10506 4.7677 4.7677 -87.427 -4.7677 0 0 63348.9 2533.96 0.01 0.04 0.01 -1 -1 0.01 0.0271383 0.0247399 37 51 57 11 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 6.05 vpr 62.98 MiB 0.03 6368 -1 -1 1 0.03 -1 -1 30272 -1 -1 5 17 0 -1 success v8.0.0-11333-g6a44da44e-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T21:53:04 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64496 17 16 251 206 1 121 38 5 5 25 clb auto 24.5 MiB 4.36 379 1487 482 996 9 63.0 MiB 0.04 0.00 3.96728 -77.1356 -3.96728 3.96728 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