diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 61dd775abb9..608d0bbf1d5 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1517,6 +1517,21 @@ VPR uses a negotiated congestion algorithm (based on Pathfinder) to perform rout * `swns` - setup Worst Negative Slack (sWNS) [ns] * `stns` - Setup Total Negative Slack (sTNS) [ns] + +.. option:: --generate_net_timing_report {on | off} + + Generates a net timing report for each net in the design. For each net, the timing information written in the following format: + + .. code-block:: none + + netname : Fanout : + (bounding_box_xmin,bounding_box_ymin,bounding_box_layer_min),(bounding_box_xmax,bounding_box_ymax,bounding_box_layer_max) : + source_instance : + : + : ... + + **Default:** ``off`` + .. option:: --route_verbosity Controls the verbosity of routing output. diff --git a/vpr/src/analysis/timing_reports.cpp b/vpr/src/analysis/timing_reports.cpp index 281a40b67a0..36cb99c0207 100644 --- a/vpr/src/analysis/timing_reports.cpp +++ b/vpr/src/analysis/timing_reports.cpp @@ -1,7 +1,14 @@ #include "timing_reports.h" +#include +#include + +#include "timing_reports.h" +#include "rr_graph.h" + #include "tatum/TimingReporter.hpp" +#include "vtr_version.h" #include "vpr_types.h" #include "globals.h" @@ -10,6 +17,121 @@ #include "VprTimingGraphResolver.h" +/** + * @brief Get the bounding box of a net. + * If the net is completely absorbed into a cluster block, return the bounding box of the cluster block. + * Otherwise, return the bounding box of the net's route tree. + * If a net is not routed, bounding box is returned with default values (OPEN). + * + * @param atom_net_id The id of the atom net to get the bounding box of. + */ +static t_bb get_net_bounding_box(const AtomNetId atom_net_id) { + const auto& route_trees = g_vpr_ctx.routing().route_trees; + const auto& rr_graph = g_vpr_ctx.device().rr_graph; + + // Lambda to get the bounding box of a route tree + auto route_tree_bb = [&](const RouteTree& route_tree) { + t_bb bb; + + // Set the initial bounding box to the root node's location + RRNodeId route_tree_root = route_tree.root().inode; + bb.xmin = rr_graph.node_xlow(route_tree_root); + bb.xmax = rr_graph.node_xhigh(route_tree_root); + bb.ymin = rr_graph.node_ylow(route_tree_root); + bb.ymax = rr_graph.node_yhigh(route_tree_root); + bb.layer_min = rr_graph.node_layer(route_tree_root); + bb.layer_max = rr_graph.node_layer(route_tree_root); + + // Iterate over all nodes in the route tree and update the bounding box + for (auto& rt_node : route_tree.all_nodes()) { + RRNodeId inode = rt_node.inode; + + if (rr_graph.node_xlow(inode) < bb.xmin) + bb.xmin = rr_graph.node_xlow(inode); + if (rr_graph.node_xhigh(inode) > bb.xmax) + bb.xmax = rr_graph.node_xhigh(inode); + + if (rr_graph.node_ylow(inode) < bb.ymin) + bb.ymin = rr_graph.node_ylow(inode); + if (rr_graph.node_yhigh(inode) > bb.ymax) + bb.ymax = rr_graph.node_yhigh(inode); + + if (rr_graph.node_layer(inode) < bb.layer_min) + bb.layer_min = rr_graph.node_layer(inode); + if (rr_graph.node_layer(inode) > bb.layer_max) + bb.layer_max = rr_graph.node_layer(inode); + } + return bb; + }; + + if (g_vpr_ctx.routing().is_flat) { + // If flat router is used, route tree data structure can be used + // directly to get the bounding box of the net + const auto& route_tree = route_trees[atom_net_id]; + if (!route_tree) + return t_bb(); + return route_tree_bb(*route_tree); + } else { + // If two-stage router is used, we need to first get the cluster net id + // corresponding to the atom net and then get the bounding box of the net + // from the route tree. If the net is completely absorbed into a cluster block, + const auto& atom_lookup = g_vpr_ctx.atom().lookup(); + const auto& cluster_net_id = atom_lookup.clb_nets(atom_net_id); + std::vector bbs; + t_bb max_bb; + // There maybe multiple cluster nets corresponding to a single atom net. + // We iterate over all cluster nets and the final bounding box is the union + // of all cluster net bounding boxes + if (cluster_net_id != vtr::nullopt) { + for (const auto& clb_net_id : *cluster_net_id) { + const auto& route_tree = route_trees[clb_net_id]; + if (!route_tree) + continue; + bbs.push_back(route_tree_bb(*route_tree)); + } + if (bbs.empty()) { + return t_bb(); + } + // Assign the first cluster net's bounding box to the final bounding box + // and then iteratively update it with the union of bounding boxes of + // all cluster nets + max_bb = bbs[0]; + for (size_t i = 1; i < bbs.size(); ++i) { + max_bb.xmin = std::min(bbs[i].xmin, max_bb.xmin); + max_bb.xmax = std::max(bbs[i].xmax, max_bb.xmax); + max_bb.ymin = std::min(bbs[i].ymin, max_bb.ymin); + max_bb.ymax = std::max(bbs[i].ymax, max_bb.ymax); + max_bb.layer_min = std::min(bbs[i].layer_min, max_bb.layer_min); + max_bb.layer_max = std::max(bbs[i].layer_max, max_bb.layer_max); + } + return max_bb; + } else { + // If there is no cluster net corresponding to the atom net, + // it means the net is completely absorbed into a cluster block. + // In that case, we set the bounding box the cluster block's bounding box + const auto& atom_ctx = g_vpr_ctx.atom(); + const auto& atom_nlist = atom_ctx.netlist(); + AtomPinId source_pin = atom_nlist.net_driver(atom_net_id); + + AtomBlockId atom_block = atom_nlist.pin_block(source_pin); + VTR_ASSERT(atom_block != AtomBlockId::INVALID()); + ClusterBlockId cluster_block = atom_lookup.atom_clb(atom_block); + VTR_ASSERT(cluster_block != ClusterBlockId::INVALID()); + + const t_pl_loc& cluster_block_loc = g_vpr_ctx.placement().block_locs()[cluster_block].loc; + const auto& grid = g_vpr_ctx.device().grid; + vtr::Rect tile_bb = grid.get_tile_bb({cluster_block_loc.x, cluster_block_loc.y, cluster_block_loc.layer}); + const int block_layer = cluster_block_loc.layer; + return t_bb(tile_bb.xmin(), + tile_bb.xmax(), + tile_bb.ymin(), + tile_bb.ymax(), + block_layer, + block_layer); + } + } +} + void generate_setup_timing_stats(const std::string& prefix, const SetupTimingInfo& timing_info, const AnalysisDelayCalculator& delay_calc, @@ -61,3 +183,76 @@ void generate_hold_timing_stats(const std::string& prefix, timing_reporter.report_unconstrained_hold(prefix + "report_unconstrained_timing.hold.rpt", *timing_info.hold_analyzer()); } + +void generate_net_timing_report(const std::string& prefix, + const SetupHoldTimingInfo& timing_info, + const AnalysisDelayCalculator& delay_calc) { + /* Create a report file for net timing information */ + std::ofstream os(prefix + "report_net_timing.rpt"); + const auto& atom_netlist = g_vpr_ctx.atom().netlist(); + const auto& atom_lookup = g_vpr_ctx.atom().lookup(); + + const auto& timing_ctx = g_vpr_ctx.timing(); + const auto& timing_graph = timing_ctx.graph; + + os << "# This file is generated by VTR" << std::endl; + os << "# Version: " << vtr::VERSION << std::endl; + os << "# Revision: " << vtr::VCS_REVISION << std::endl; + os << "# For each net, the timing information is reported in the following format:" << std::endl; + os << "# netname : Fanout : " + << "(bounding_box_xmin,bounding_box_ymin,bounding_box_layermin),(bounding_box_xmax,bounding_box_ymax,bounding_box_layermax) : " + << "source_instance : " + << " : " + << " : ..." + << std::endl; + + os << std::endl; + + for (const auto& net : atom_netlist.nets()) { + /* Skip constant nets */ + if (atom_netlist.net_is_constant(net)) { + continue; + } + + const auto& net_name = atom_netlist.net_name(net); + + /* Get source pin and its timing information */ + const auto& source_pin = *atom_netlist.net_pins(net).begin(); + auto source_pin_slack = timing_info.setup_pin_slack(source_pin); + /* Timing graph node id corresponding to the net's source pin */ + auto tg_source_node = atom_lookup.atom_pin_tnode(source_pin); + VTR_ASSERT(tg_source_node.is_valid()); + + const size_t fanout = atom_netlist.net_sinks(net).size(); + const auto& net_bb = get_net_bounding_box(net); + os << net_name << " : " + << fanout << " : " + << "(" << net_bb.xmin << "," << net_bb.ymin << "," << net_bb.layer_min << "),(" + << net_bb.xmax << "," << net_bb.ymax << "," << net_bb.layer_max << ") : " + << atom_netlist.pin_name(source_pin).c_str() << " " << source_pin_slack << " : "; + + /* Iterate over all fanout pins and print their timing information */ + for (size_t net_pin_index = 1; net_pin_index <= fanout; ++net_pin_index) { + const auto& pin = *(atom_netlist.net_pins(net).begin() + net_pin_index); + + /* Get timing graph node id corresponding to the fanout pin */ + const auto& tg_sink_node = atom_lookup.atom_pin_tnode(pin); + VTR_ASSERT(tg_sink_node.is_valid()); + + /* Get timing graph edge id between atom pins */ + const auto& tg_edge_id = timing_graph->find_edge(tg_source_node, tg_sink_node); + VTR_ASSERT(tg_edge_id.is_valid()); + + /* Get timing information for the fanout pin */ + const auto& pin_setup_slack = timing_info.setup_pin_slack(pin); + const auto& pin_delay = delay_calc.max_edge_delay(*timing_graph, tg_edge_id); + + const auto& pin_name = atom_netlist.pin_name(pin); + os << pin_name << " " << std::scientific << pin_setup_slack << " " << pin_delay; + if (net_pin_index < fanout) { + os << " : "; + } + } + os << "," << std::endl; + } +} diff --git a/vpr/src/analysis/timing_reports.h b/vpr/src/analysis/timing_reports.h index 72e1013dece..0aec721d76a 100644 --- a/vpr/src/analysis/timing_reports.h +++ b/vpr/src/analysis/timing_reports.h @@ -21,4 +21,21 @@ void generate_hold_timing_stats(const std::string& prefix, bool is_flat, const BlkLocRegistry& blk_loc_registry); +/** + * @brief Generates timing information for each net in atom netlist. For each net, the timing information + * is reported in the following format: + * netname : Fanout : + * (bounding_box_xmin,bounding_box_ymin,bounding_box_layermin),(bounding_box_xmax,bounding_box_ymax,bounding_box_layermax) : + * source_instance : + * : + * : ... + * + * @param prefix The prefix for the report file to be added to filename: report_net_timing.rpt + * @param timing_info Updated timing information + * @param delay_calc Delay calculator + */ +void generate_net_timing_report(const std::string& prefix, + const SetupHoldTimingInfo& timing_info, + const AnalysisDelayCalculator& delay_calc); + #endif diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 25556636617..7f3ab8bfc45 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -719,6 +719,7 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi analysis_opts.timing_update_type = Options.timing_update_type; analysis_opts.write_timing_summary = Options.write_timing_summary; + analysis_opts.generate_net_timing_report = Options.generate_net_timing_report; } static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch) { diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index d4b70892580..f092f77ae0d 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -3088,6 +3088,11 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .help("Writes implemented design final timing summary to the specified JSON, XML or TXT file.") .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.generate_net_timing_report, "--generate_net_timing_report") + .help("Generates a net timing report for each net in the design.") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + auto& power_grp = parser.add_argument_group("power analysis options"); power_grp.add_argument(args.do_power, "--power") diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 61051940b3a..1220490aec4 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -272,6 +272,7 @@ struct t_options { argparse::ArgValue post_synth_netlist_unconn_output_handling; argparse::ArgValue post_synth_netlist_module_parameters; argparse::ArgValue write_timing_summary; + argparse::ArgValue generate_net_timing_report; }; argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_options& args); diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index b841c23bd36..4dc4732c90c 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -1475,6 +1475,10 @@ void vpr_analysis(const Netlist<>& net_list, merged_netlist_writer(atom_ctx.netlist().netlist_name(), analysis_delay_calc, Arch.models, vpr_setup.AnalysisOpts); } + if (vpr_setup.AnalysisOpts.generate_net_timing_report) { + generate_net_timing_report(/*prefix=*/"", *timing_info, *analysis_delay_calc); + } + //Do power analysis // TODO: Still assumes that cluster net list is used if (vpr_setup.PowerOpts.do_power) { diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 8fc929ed06a..d09870dc317 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1352,6 +1352,7 @@ struct t_analysis_opts { bool timing_report_skew; std::string echo_dot_timing_graph_node; std::string write_timing_summary; + bool generate_net_timing_report; e_timing_update_type timing_update_type; }; diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt index 79ab5b22460..ae8e519b4a4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/config.txt @@ -24,7 +24,10 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common = -starting_stage vpr +script_params_common = -starting_stage vpr --generate_net_timing_report on script_params_list_add=--timing_report_detail netlist script_params_list_add=--timing_report_detail aggregated script_params_list_add=--timing_report_detail detailed +script_params_list_add=--timing_report_detail netlist --flat_routing on +script_params_list_add=--timing_report_detail aggregated --flat_routing on +script_params_list_add=--timing_report_detail detailed --flat_routing on diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index a5bee947840..f82233e2459 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.50 vpr 67.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68660 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.6443e-05 3.2529e-05 0.000274786 0.000214986 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00211509 0.0019009 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0017763 0.00169895 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.49 vpr 67.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8016e-05 3.4218e-05 0.000283686 0.000224427 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0022472 0.00206472 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00179634 0.00171755 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.51 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68932 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 6.2523e-05 4.6425e-05 0.000366128 0.000294026 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00236124 0.00216436 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00189537 0.00181322 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.37 vpr 65.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66624 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 24 21 30 9 19 2 65.1 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.4867e-05 1.6785e-05 0.000178305 0.000138626 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0013303 0.00121195 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0010544 0.00100577 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.38 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66628 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 24 21 30 9 19 2 65.1 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5617e-05 1.7506e-05 0.000177134 0.000138581 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0012973 0.00118019 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00105506 0.00100757 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.41 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 66628 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.00 24 21 30 9 19 2 65.1 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5232e-05 1.7334e-05 0.000170999 0.000134182 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00125289 0.00113927 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00129683 0.00123 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist_--flat_routing_on 0.81 vpr 70.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 72112 5 3 11 14 2 9 10 4 4 16 clb auto 30.9 MiB 0.01 24 21 30 9 19 2 70.4 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.5406e-05 1.7598e-05 0.000175321 0.000137685 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.25 0.00131841 0.00118136 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.12 0.00 0.00 0.11 0.00 0.00103786 0.000967845 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated_--flat_routing_on 0.81 vpr 70.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 72492 5 3 11 14 2 9 10 4 4 16 clb auto 30.9 MiB 0.01 24 21 30 9 19 2 70.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5095e-05 1.6967e-05 0.000167727 0.000130306 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.26 0.00127606 0.0011399 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.12 0.00 0.00 0.12 0.00 0.00102446 0.000963839 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed_--flat_routing_on 0.85 vpr 70.42 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12677-g548d53abc-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-58-generic x86_64 2025-05-12T11:28:52 betzgrp-wintermute /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 72112 5 3 11 14 2 9 10 4 4 16 clb auto 30.9 MiB 0.01 24 21 30 9 19 2 70.4 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.5982e-05 1.7909e-05 0.000172322 0.000134495 -1 -1 -1 -1 20 25 2 107788 107788 13586.0 849.124 0.26 0.00129831 0.00116036 858 2299 78 23 2 11 15 317 166 0.605686 0.545 -3.71515 -0.605686 0 0 18030.6 1126.91 0.00 0.13 0.00 0.00 0.12 0.00 0.00101752 0.000959208