Skip to content

Commit 665f39f

Browse files
dalancedalance
authored
Merge pull request #2561 from taichi-ishitani/emit_global_function
Fix emit name of global function defined in dependent project
2 parents 715bb95 + 96d7a9e commit 665f39f

4 files changed

Lines changed: 41 additions & 9 deletions

File tree

‎crates/emitter/src/emitter.rs‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6054,16 +6054,18 @@ pub fn symbol_string(
60546054
base.kind,
60556055
SymbolKind::Module(_) | SymbolKind::Interface(_) | SymbolKind::Package(_)
60566056
);
6057+
let global_func = base.namespace.paths[0] != context.project_name.unwrap()
6058+
&& base.is_global_function();
60576059

6058-
let add_namespace = (scope_depth >= 2) | !visible | top_level;
6060+
let add_namespace = (scope_depth >= 2) | !visible | top_level | global_func;
60596061
if add_namespace {
60606062
ret.push_str(&namespace_string(symbol_namespace, generic_tables, context));
60616063
}
60626064
if context.build_opt.hashed_mangled_name {
60636065
let name = symbol
60646066
.generic_maps()
60656067
.first()
6066-
.map(|x| x.name(!add_namespace, true))
6068+
.map(|x| x.name(false, true)) // namespace has already been added
60676069
.unwrap();
60686070
ret.push_str(&name);
60696071
} else {

‎testcases/map/68_std.sv.map‎

Lines changed: 1 addition & 1 deletion
Some generated files are not rendered by default. Learn more about customizing how changed files appear on GitHub.

‎testcases/sv/68_std.sv‎

Lines changed: 18 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,22 @@ module veryl_testcase_Module68A (
2121
);
2222
endmodule
2323

24-
module veryl_testcase___Module68B____std___axi4_pkg__32__8__8__8__8__8__8__8____std___axi4_lite_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_ADDRESS_WIDTH____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH____std___axi4_stream_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES__2____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH__5 (
24+
module veryl_testcase_Module68B (
25+
input var logic [2-1:0] i_select,
26+
input var logic [4-1:0][4-1:0] i_d ,
27+
output var logic [4-1:0] o_d
28+
);
29+
__std_mux #(
30+
.WIDTH (4),
31+
.ENTRIES (4)
32+
) u (
33+
.i_select (i_select),
34+
.i_data (i_d ),
35+
.o_data (o_d )
36+
);
37+
endmodule
38+
39+
module veryl_testcase___Module68C____std___axi4_pkg__32__8__8__8__8__8__8__8____std___axi4_lite_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_ADDRESS_WIDTH____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH____std___axi4_stream_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES__2____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH__5 (
2540
__std___axi4_if____std___axi4_pkg__32__8__8__8__8__8__8__8.slave axi4_if ,
2641
__std___axi4_lite_if____std___axi4_lite_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_ADDRESS_WIDTH____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH.slave axi4_lite_if ,
2742
__std___axi4_stream_if____std___axi4_stream_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES__2____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH__5.receiver axi4_stream_if
@@ -61,7 +76,7 @@ endmodule
6176

6277

6378

64-
module veryl_testcase_Module68C;
79+
module veryl_testcase_Module68D;
6580
__std___axi4_if____std___axi4_pkg__32__8__8__8__8__8__8__8 axi4_if ();
6681
__std___axi4_lite_if____std___axi4_lite_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_ADDRESS_WIDTH____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH axi4_lite_if ();
6782
__std___axi4_stream_if____std___axi4_stream_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES__2____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH__5 axi4_stream_if ();
@@ -125,7 +140,7 @@ module veryl_testcase_Module68C;
125140
always_comb axi4_lite_if.awid = 0;
126141
always_comb axi4_lite_if.arid = 0;
127142

128-
veryl_testcase___Module68B____std___axi4_pkg__32__8__8__8__8__8__8__8____std___axi4_lite_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_ADDRESS_WIDTH____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH____std___axi4_stream_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES__2____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH__5 u (
143+
veryl_testcase___Module68C____std___axi4_pkg__32__8__8__8__8__8__8__8____std___axi4_lite_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_ADDRESS_WIDTH____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH____std___axi4_stream_pkg____std___axi4_pkg__32__8__8__8__8__8__8__8_DATA_WIDTH_BYTES__2____std___axi4_pkg__32__8__8__8__8__8__8__8_ID_LENGTH__5 u (
129144
.axi4_if (axi4_if ),
130145
.axi4_lite_if (axi4_lite_if ),
131146
.axi4_stream_if (axi4_stream_if)

‎testcases/veryl/68_std.veryl‎

Lines changed: 18 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,22 @@ module Module68A (
2121
);
2222
}
2323

24-
module Module68B::<AXI4_PKG: $std::axi4_prototype, AXI4_LITE_PKG: $std::axi4_lite_prototype, AXI4_STREAM_PKG: $std::axi4_stream_prototype> (
24+
module Module68B (
25+
i_select: input logic<2> ,
26+
i_d : input logic<4, 4>,
27+
o_d : output logic<4> ,
28+
) {
29+
inst u: $std::mux #(
30+
WIDTH : 4,
31+
ENTRIES: 4,
32+
) (
33+
i_select: i_select,
34+
i_data : i_d ,
35+
o_data : o_d ,
36+
);
37+
}
38+
39+
module Module68C::<AXI4_PKG: $std::axi4_prototype, AXI4_LITE_PKG: $std::axi4_lite_prototype, AXI4_STREAM_PKG: $std::axi4_stream_prototype> (
2540
axi4_if : modport $std::axi4_if::<AXI4_PKG>::slave ,
2641
axi4_lite_if : modport $std::axi4_lite_if::<AXI4_LITE_PKG>::slave ,
2742
axi4_stream_if: modport $std::axi4_stream_if::<AXI4_STREAM_PKG>::receiver,
@@ -35,7 +50,7 @@ alias package axi_pkg = $std::axi4_pkg::<32, 8, 8, 8, 8, 8, 8, 8>;
3550
alias package axi_lite_pkg = $std::axi4_lite_pkg::<axi_pkg::ADDRESS_WIDTH, axi_pkg::DATA_WIDTH_BYTES, axi_pkg::ID_LENGTH>;
3651
alias package axi_stream_pkg = $std::axi4_stream_pkg::<axi_pkg::DATA_WIDTH_BYTES, 2, axi_pkg::ID_LENGTH, 5>;
3752

38-
module Module68C {
53+
module Module68D {
3954
inst axi4_if : $std::axi4_if::<axi_pkg>;
4055
inst axi4_lite_if : $std::axi4_lite_if::<axi_lite_pkg>;
4156
inst axi4_stream_if : $std::axi4_stream_if::<axi_stream_pkg>;
@@ -46,7 +61,7 @@ module Module68C {
4661
assign axi4_lite_if.awid = 0;
4762
assign axi4_lite_if.arid = 0;
4863

49-
inst u: Module68B::<axi_pkg, axi_lite_pkg, axi_stream_pkg> (
64+
inst u: Module68C::<axi_pkg, axi_lite_pkg, axi_stream_pkg> (
5065
axi4_if : axi4_if ,
5166
axi4_lite_if : axi4_lite_if ,
5267
axi4_stream_if: axi4_stream_if,

0 commit comments

Comments
 (0)