Fix AOT-C unary result left unmasked in a 65..128-bit context

Author: dalance

crates/simulator/src/backend/aot_c/emit.rs

@@ -3557,6 +3557,15 @@ fn emit_expr_inner(expr: &ProtoExpression, needs_clean: bool) -> Option<String>
                     if needs_clean && expr_context.width > 0 && expr_context.width < 64 {
                         let mask = (1u64 << expr_context.width) - 1;
                         Some(format!("(({}) & 0x{:x}ULL)", inner, mask))
+                    } else if needs_clean && expr_context.width > 64 && expr_context.width < 128 {
+                        // 65..128-bit context over a ≤64-bit operand: the
+                        // int64 result sign-extends through the __uint128_t
+                        // promotion (supplying the ones in [xw..width) for
+                        // ~/-), then the mask trims [width..128).
+                        Some(mask_u128(
+                            &format!("((__uint128_t)(__int128_t)({inner}))"),
+                            expr_context.width,
+                        ))
                     } else {
                         Some(inner)
                     }

crates/simulator/src/tests/simulation.rs

@@ -19039,3 +19039,42 @@ fn reduction_xnor_is_even_parity() {
         }
     }
 }
+
+#[test]
+fn aot_c_unary_masked_in_wide_context() {
+    // A unary ~/- over a ≤64-bit operand evaluated in a 65..128-bit context
+    // was emitted as a dirty int64 by the AOT-C backend: promoted to
+    // __uint128_t it sign-extends past the context width, so comparisons
+    // reading the high bits miscompiled (eq/en = 0 instead of 1).
+    let code = r#"
+    module Top (
+        a : input  logic<32>,
+        eq: output logic,
+        en: output logic,
+    ) {
+        var b: logic<100>;
+        var c: logic<100>;
+        assign b = ~{68'd0, a};
+        assign c = 100'd0 - {68'd0, a};
+        assign eq = b == ~a;
+        assign en = c == -a;
+    }
+    "#;
+
+    for config in Config::all() {
+        let ir = analyze(code, &config);
+        let mut sim = Simulator::new(ir, None);
+        sim.set("a", Value::new(5, 32, false));
+        sim.step(&Event::Clock(VarId::SYNTHETIC));
+        assert_eq!(
+            sim.get("eq").unwrap(),
+            Value::new(1, 1, false),
+            "eq config={config:?}"
+        );
+        assert_eq!(
+            sim.get("en").unwrap(),
+            Value::new(1, 1, false),
+            "en config={config:?}"
+        );
+    }
+}