Merge pull request #3145 from veryl-lang/pr/01-analyzer-assign-rhs-width

fix(analyzer): size assignment RHS against the LHS bit-select width

Author: dalance

crates/analyzer/src/conv/declaration.rs

@@ -15,11 +15,12 @@ use crate::conv::checker::inst::check_inst;
 use crate::conv::checker::modport::{check_modport, check_modport_default, check_modport_in_port};
 use crate::conv::checker::port::{check_direction, check_port_default_value, check_port_direction};
 use crate::conv::utils::{
-    TypePosition, check_assign_clock_domain, eval_array_range_assign, eval_assign_statement,
-    eval_clock, eval_const_assign, eval_expr, eval_factor_symbol, eval_factor_symbol_external,
-    eval_generate_for_range, eval_reset, eval_size, eval_type, eval_variable, expand_connect,
-    expand_connect_const, get_component, get_overridden_params, get_port_connects, get_return_str,
-    insert_port_connect, try_infer_decl_type, try_infer_var_assign, var_path_to_assign_destination,
+    TypePosition, assign_rhs_context_type, check_assign_clock_domain, eval_array_range_assign,
+    eval_assign_statement, eval_clock, eval_const_assign, eval_expr, eval_factor_symbol,
+    eval_factor_symbol_external, eval_generate_for_range, eval_reset, eval_size, eval_type,
+    eval_variable, expand_connect, expand_connect_const, get_component, get_overridden_params,
+    get_port_connects, get_return_str, insert_port_connect, try_infer_decl_type,
+    try_infer_var_assign, var_path_to_assign_destination,
 };
 use crate::conv::{Affiliation, Context, Conv};
 use crate::definition_table::{self, Definition};
@@ -948,12 +949,8 @@ impl Conv<&AssignDeclaration> for ir::Declaration {
                     let mut expr = if let Some(inferred) = inferred {
                         inferred
                     } else {
-                        eval_expr(
-                            context,
-                            Some(dst.comptime.r#type.clone()),
-                            &value.expression,
-                            false,
-                        )?
+                        let ctx_type = assign_rhs_context_type(context, &dst);
+                        eval_expr(context, Some(ctx_type), &value.expression, false)?
                     };
 
                     let statements = eval_assign_statement(context, &mut dst, &mut expr, token)?;

crates/analyzer/src/conv/statement.rs

@@ -1,10 +1,10 @@
 use crate::analyzer_error::{ComponentInterfaceMismatchKind, MismatchTypeKind};
 use crate::conv::utils::{
-    TbMethodCallPosition, TypePosition, argument_list, build_for_range, build_for_statement,
-    case_patterns, check_assign_clock_domain, eval_array_range_assign, eval_assign_statement,
-    eval_expr, eval_variable, expand_connect, expand_connect_const, function_call, get_return_str,
-    hoist_component_method_call, single_function_call_factor, switch_condition, tb_method_call,
-    try_infer_decl_type, try_infer_var_assign,
+    TbMethodCallPosition, TypePosition, argument_list, assign_rhs_context_type, build_for_range,
+    build_for_statement, case_patterns, check_assign_clock_domain, eval_array_range_assign,
+    eval_assign_statement, eval_expr, eval_variable, expand_connect, expand_connect_const,
+    function_call, get_return_str, hoist_component_method_call, single_function_call_factor,
+    switch_condition, tb_method_call, try_infer_decl_type, try_infer_var_assign,
 };
 use crate::conv::{Context, Conv};
 use crate::ir::{
@@ -357,12 +357,8 @@ impl Conv<&IdentifierStatement> for ir::StatementBlock {
                             let mut expr = if let Some(inferred) = inferred {
                                 inferred
                             } else {
-                                eval_expr(
-                                    context,
-                                    Some(dst.comptime.r#type.clone()),
-                                    &x.assignment.expression,
-                                    false,
-                                )?
+                                let ctx_type = assign_rhs_context_type(context, &dst);
+                                eval_expr(context, Some(ctx_type), &x.assignment.expression, false)?
                             };
 
                             let statements =
@@ -392,9 +388,10 @@ impl Conv<&IdentifierStatement> for ir::StatementBlock {
                         if let Some(dst) = dst.to_assign_destination(context, false)
                             && let Some(src) = src.to_expression(context)
                         {
+                            let ctx_type = assign_rhs_context_type(context, &dst);
                             let (_, expr) = eval_expr(
                                 context,
-                                Some(dst.comptime.r#type.clone()),
+                                Some(ctx_type),
                                 &x.assignment.expression,
                                 false,
                             )?;

crates/analyzer/src/conv/utils.rs

@@ -650,6 +650,29 @@ pub fn eval_assign_statement(
     Ok(ret)
 }
 
+/// IEEE 1800 sizes an assignment RHS against the LHS *select*, not the whole
+/// variable.  Only observable when the RHS is no wider than the select, since
+/// the context is the max of the two: with an 8-bit `y`, `x[7:0] = (y << 4)
+/// >> 4` is 0x0d at 8 bits and 0xcd at a 32-bit `x`'s width.
+pub fn assign_rhs_context_type(context: &mut Context, dst: &ir::AssignDestination) -> ir::Type {
+    let full = dst.comptime.r#type.clone();
+    if dst.select.is_empty() || dst.comptime.part_select.is_some() {
+        return full;
+    }
+    if !matches!(full.kind, ir::TypeKind::Logic | ir::TypeKind::Bit) {
+        return full;
+    }
+    let Some(w) = dst.total_width(context) else {
+        return full;
+    };
+    if w == 0 || full.total_width().is_none_or(|fw| w >= fw) {
+        return full;
+    }
+    let mut t = full;
+    t.set_concrete_width(Shape::new(vec![Some(w)]));
+    t
+}
+
 /// Expand an array-range assignment LHS (`o[0+:N] = '{...}`) into one assignment
 /// per covered element (recursing inner dims for multi-dim arrays). Returns `None`
 /// to defer to the scalar path when the LHS isn't a range or the RHS isn't an array

crates/simulator/src/tests/simulation.rs

@@ -20297,3 +20297,33 @@ fn package_const_select_multi_dim_width() {
         }
     }
 }
+
+#[test]
+fn assign_rhs_sized_by_lhs_bit_select_width() {
+    // Regression: sized against the 32-bit variable rather than the 8-bit
+    // select, the shift pair was lossless and stored 0xcd.  0x0d is what the
+    // emitted SV produces under both iverilog and Verilator.
+    let code = r#"
+    module Top (
+        y: input  logic<8>,
+        o: output logic<32>,
+    ) {
+        always_comb {
+            o = 0;
+            o[7:0] = (y << 4) >> 4;
+        }
+    }
+    "#;
+
+    for config in Config::all() {
+        let ir = analyze(code, &config);
+        let mut sim = Simulator::new(ir, None);
+        sim.set("y", Value::new(0xcd, 8, false));
+        sim.step(&Event::Clock(VarId::SYNTHETIC));
+        assert_eq!(
+            sim.get("o").unwrap(),
+            Value::new(0x0d, 32, false),
+            "config={config:?}"
+        );
+    }
+}