i was trying to compile https://github.com/olofk/serv for shrike-lite, its synthesising correctly but when comes to generating bitstream, next-pnr (yosys) gave the error, looks like renasas ppl din't implement all the cells or most probably used an example library and didn't mind changing params for their FPGA.

To reproduce

change the servant module deceleration to

(* top *)module servant
(
 (* iopad_external_pin, clkbuf_inhibit *) input wire  wb_clk,
 (* iopad_external_pin *) output wire wb_clk_en,
 (* iopad_external_pin *) input wire  wb_rst,
 (* iopad_external_pin *) output wire q,
 (* iopad_external_pin *) output wire q_en
 );
assign wb_clk_en = 1'b1;
assign q_en = 1'b1;

import these files from serv git repo