Use hedge reading from RAM for work-stealing and similar algorithms on multicore systems to nullify RAM tail latency and gain near perfect determinism

[dumblob]

Describe the feature

See https://github.com/LaurieWired/tailslayer

And detailed explanation in video https://www.youtube.com/watch?v=KKbgulTp3FE

Use Case

I am frustrated with huge tail latency (DRAM refreshes, their non-determinism, etc.) especially with latency-sensitive scenarios (scheduling algorithms for multicore parallel processing waiting for reading the scheduling algorithm data structures!, web server responses, high-frequency trading, etc.).

Proposed Solution

No response

Other Information

No response

Acknowledgements

• I may be able to implement this feature request
• This feature might incur a breaking change

Version used

latest

Environment details (OS name and version, etc.)

any

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[Wajinn]

Some form of implementing this idea would likely be good for V. Possibly also worth getting a mention from LaurieWired, who has some great ideas and insights.