chore: clean root artifacts and normalize docs (#4)

Author: w1ne

.gitignore

@@ -0,0 +1,28 @@
+# Build output
+/target/
+/*.rlib
+
+# Local release/test run outputs
+/final-release-verification/
+/release-demo/
+/release-ready-test/
+
+# Local debug/lint artifacts
+/gdb_test.log
+/clippy_output.txt
+/*_error.log
+
+# Generated root-level chip artifacts (keep source of truth under tests/configs)
+/advanced_stm32.json
+/advanced_stm32.rs
+/dummy_stm32.json
+/dummy_stm32.rs
+/nrf52832.json
+/nrf52832.rs
+/rp2040.json
+/rp2040.rs
+/stm32f401.json
+/stm32f401.rs
+/test_device.json
+/test_device.rs
+/demo_chip.rs

CHANGELOG.md

@@ -16,10 +16,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
     - Verified against STM32F4, RP2040, and nRF52.
 - **Timing Hooks**: Declarative peripheral behavior for registers (SetBits, ClearBits, WriteValue) with periodic and event-based triggers.
 - **Timeline View**: Professional visualization of instruction trace data in the VS Code extension.
-- **Support Strategy**: Defined **Tier 1 Device Support** (STM32F4, RP2040, nRF52) in `docs/SUPPORTED_DEVICES.md`.
-- **Architecture Guide**: New comprehensive `core/docs/ARCHITECTURE.md`.
+- **Support Strategy**: Defined **Tier 1 Device Support** (STM32F4, RP2040, nRF52) in `docs/release_strategy.md`.
+- **Architecture Guide**: New comprehensive `core/docs/architecture_guide.md`.
 - **SVD Ingestor**: New tool (`crates/svd-ingestor`) to generate `PeripheralDescriptor` YAMLs from SVD.
-- **Strategic Horizon**: Long-term vision integrated into `docs/plan.md`.
+- **Strategic Horizon**: Long-term vision integrated into `docs/release_strategy.md`.
 
 ## [0.11.0] - 2026-02-08
 
@@ -28,7 +28,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
     - **Modeling**: Enabled peripheral definition via YAML descriptors using `labwired-config`.
     - **Simulation**: Implemented `GenericPeripheral` in `labwired-core` supporting dynamic MMR modeling, bitwise masking, and reset state.
     - **Integration**: Added support for `type: "declarative"` in chip descriptors, allowing zero-code peripheral additions.
-    - **Documentation**: New [Peripheral Modeling Tutorial](file:///home/andrii/Projects/labwired/docs/tutorial_peripheral_modeling.md) for declarative IP cores.
+    - **Documentation**: New [Peripheral Development Guide](./docs/peripheral_development.md) for declarative IP cores.
 - **ISA Extensions**:
     - **Misc Thumb-2**: Implemented `CLZ` (Count Leading Zeros), `RBIT` (Bit Reverse), `REV`, `REV16`, `REVSH` instructions.
     - **RISC-V Support**: Initial support for RV32I Base Integer Instruction Set with multi-arch GDB support.
@@ -60,8 +60,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
     - **GDB Remote Serial Protocol**: New `labwired-gdbstub` crate allowing connection from standard GDB clients.
     - **Interactive Debugging (DAP)**: `labwired-dap` server for VS Code integration with variable and register inspection.
 - **Documentation**:
-    - [Peripheral Development Guide](file:///home/andrii/Projects/labwired/docs/peripheral_development.md).
-    - [Getting Started with Real Firmware](file:///home/andrii/Projects/labwired/docs/getting_started_firmware.md) onboarding guide.
+    - [Peripheral Development Guide](./docs/peripheral_development.md).
+    - [Getting Started with Real Firmware](./docs/getting_started_firmware.md) onboarding guide.
 
 ## [0.9.0] - 2026-02-04
 

README.md

@@ -34,9 +34,11 @@ We welcome contributions! Please see our community guides:
 Full setup guide: [Getting Started](./docs/getting_started_firmware.md)
 
 ## Documentation
-- [Architecture](./docs/architecture.md)
-- [CI Integration](./docs/ci_integration.md)
-- [GDB Integration](./docs/GDB_INTEGRATION.md)
+- [Architecture Overview](./docs/architecture.md)
+- [Architecture Guide](./docs/architecture_guide.md)
+- [CI Integration Guide](./docs/ci_integration.md)
+- [GDB Integration](./docs/gdb_integration.md)
+- [Release Strategy](./docs/release_strategy.md)
 - [VS Code Debugging](./docs/vscode_debugging.md)
 
 ## License

advanced_stm32.json

@@ -55,7 +55,7 @@ To satisfy Rust's borrow checker and ensure determinism:
 2.  **Resolution Phase**: The Bus processes these requests, modifying memory or triggering CPU exceptions.
 
 ## 3. Peripheral Modeling
-We prioritize **Tier 1 Devices** for deep support (see `docs/SUPPORTED_DEVICES.md`):
+We prioritize **Tier 1 Devices** for deep support (see `docs/release_strategy.md`):
 *   **STM32F4** (Cortex-M4)
 *   **RP2040** (Dual Cortex-M0+)
 *   **nRF52** (Cortex-M4F)

advanced_stm32.rs

@@ -49,4 +49,4 @@ registers:
 
 ## Getting Started
 
-See the [Peripheral Modeling Tutorial](file:///home/andrii/Projects/labwired/docs/tutorial_peripheral_modeling.md) for a step-by-step guide on creating your first declarative peripheral.
+See the [Peripheral Development Guide](./peripheral_development.md) for a step-by-step workflow to build your first declarative peripheral.

clippy_output.txt

@@ -4,13 +4,13 @@ This example demonstrates how to use the `labwired test` runner to verify a real
 
 ## 1. The Building Blocks
 
-### Chip Descriptor ([stm32f103.yaml](file:///home/andrii/Projects/labwired/configs/chips/stm32f103.yaml))
+### Chip Descriptor ([stm32f103.yaml](../../configs/chips/stm32f103.yaml))
 Defines the memory map and peripherals (DMA, EXTI, AFIO, UART).
 
-### System Manifest ([stm32f103-integrated-test.yaml](file:///home/andrii/Projects/labwired/configs/systems/stm32f103-integrated-test.yaml))
+### System Manifest ([stm32f103-integrated-test.yaml](../../configs/systems/stm32f103-integrated-test.yaml))
 Wires the chip into a specific system context. In this case, it just uses the raw chip.
 
-### Firmware ([main.rs](file:///home/andrii/Projects/labwired/crates/firmware/src/main.rs))
+### Firmware ([main.rs](../../crates/firmware/src/main.rs))
 A Rust `no_std` firmware that:
 - Performs 32-bit division.
 - Configures DMA1 Channel 1 for a memory-to-memory transfer.
@@ -19,7 +19,7 @@ A Rust `no_std` firmware that:
 
 ## 2. The Test Script
 
-The test script ([stm32f103_integrated_test.yaml](file:///home/andrii/Projects/labwired/examples/tests/stm32f103_integrated_test.yaml)) automates the simulation:
+The test script ([stm32f103_integrated_test.yaml](../../examples/tests/stm32f103_integrated_test.yaml)) automates the simulation:
 
 ```yaml
 schema_version: "1.0"