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taisirhassantaisirhassan
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Fix Timer2 interrupt flag register - use PIR4 instead of PIR1
1 parent f47429b commit 07d3c4a

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-135
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+136
-135
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‎pic18f26k83/pwm.c‎

Lines changed: 136 additions & 135 deletions
Original file line numberDiff line numberDiff line change
@@ -13,116 +13,116 @@ static w_status_t configure_pps(uint8_t ccp_module, pwm_pin_config_t pin_config)
1313

1414
// Get TRIS register based on port (macros require compile-time constants, so use switch)
1515
switch (pin_config.port) {
16-
case 'A':
17-
tris_reg = &TRISA;
18-
break;
19-
case 'B':
20-
tris_reg = ⧍
21-
break;
22-
case 'C':
23-
tris_reg = &TRISC;
24-
break;
25-
default:
26-
return W_INVALID_PARAM;
16+
case 'A':
17+
tris_reg = &TRISA;
18+
break;
19+
case 'B':
20+
tris_reg = ⧍
21+
break;
22+
case 'C':
23+
tris_reg = &TRISC;
24+
break;
25+
default:
26+
return W_INVALID_PARAM;
2727
}
2828

2929
// Set the pin as output to drive PWM signal
3030
*tris_reg &= ~(1 << pin_config.pin);
3131

3232
// Get PPS register based on port and pin (macros require compile-time constants, so use switch)
3333
switch (pin_config.port) {
34-
case 'A':
35-
switch (pin_config.pin) {
36-
case 0:
37-
pps_reg = &RA0PPS;
38-
break;
39-
case 1:
40-
pps_reg = &RA1PPS;
41-
break;
42-
case 2:
43-
pps_reg = &RA2PPS;
44-
break;
45-
case 3:
46-
pps_reg = &RA3PPS;
47-
break;
48-
case 4:
49-
pps_reg = &RA4PPS;
50-
break;
51-
case 5:
52-
pps_reg = &RA5PPS;
53-
break;
54-
case 6:
55-
pps_reg = &RA6PPS;
56-
break;
57-
case 7:
58-
pps_reg = &RA7PPS;
59-
break;
60-
default:
61-
return W_INVALID_PARAM;
62-
}
63-
break;
64-
case 'B':
65-
switch (pin_config.pin) {
66-
case 0:
67-
pps_reg = &RB0PPS;
68-
break;
69-
case 1:
70-
pps_reg = &RB1PPS;
71-
break;
72-
case 2:
73-
pps_reg = &RB2PPS;
74-
break;
75-
case 3:
76-
pps_reg = &RB3PPS;
77-
break;
78-
case 4:
79-
pps_reg = &RB4PPS;
80-
break;
81-
case 5:
82-
pps_reg = &RB5PPS;
83-
break;
84-
case 6:
85-
pps_reg = &RB6PPS;
86-
break;
87-
case 7:
88-
pps_reg = &RB7PPS;
89-
break;
90-
default:
91-
return W_INVALID_PARAM;
92-
}
93-
break;
94-
case 'C':
95-
switch (pin_config.pin) {
96-
case 0:
97-
pps_reg = &RC0PPS;
98-
break;
99-
case 1:
100-
pps_reg = &RC1PPS;
101-
break;
102-
case 2:
103-
pps_reg = &RC2PPS;
104-
break;
105-
case 3:
106-
pps_reg = &RC3PPS;
107-
break;
108-
case 4:
109-
pps_reg = &RC4PPS;
110-
break;
111-
case 5:
112-
pps_reg = &RC5PPS;
113-
break;
114-
case 6:
115-
pps_reg = &RC6PPS;
116-
break;
117-
case 7:
118-
pps_reg = &RC7PPS;
34+
case 'A':
35+
switch (pin_config.pin) {
36+
case 0:
37+
pps_reg = &RA0PPS;
38+
break;
39+
case 1:
40+
pps_reg = &RA1PPS;
41+
break;
42+
case 2:
43+
pps_reg = &RA2PPS;
44+
break;
45+
case 3:
46+
pps_reg = &RA3PPS;
47+
break;
48+
case 4:
49+
pps_reg = &RA4PPS;
50+
break;
51+
case 5:
52+
pps_reg = &RA5PPS;
53+
break;
54+
case 6:
55+
pps_reg = &RA6PPS;
56+
break;
57+
case 7:
58+
pps_reg = &RA7PPS;
59+
break;
60+
default:
61+
return W_INVALID_PARAM;
62+
}
63+
break;
64+
case 'B':
65+
switch (pin_config.pin) {
66+
case 0:
67+
pps_reg = &RB0PPS;
68+
break;
69+
case 1:
70+
pps_reg = &RB1PPS;
71+
break;
72+
case 2:
73+
pps_reg = &RB2PPS;
74+
break;
75+
case 3:
76+
pps_reg = &RB3PPS;
77+
break;
78+
case 4:
79+
pps_reg = &RB4PPS;
80+
break;
81+
case 5:
82+
pps_reg = &RB5PPS;
83+
break;
84+
case 6:
85+
pps_reg = &RB6PPS;
86+
break;
87+
case 7:
88+
pps_reg = &RB7PPS;
89+
break;
90+
default:
91+
return W_INVALID_PARAM;
92+
}
93+
break;
94+
case 'C':
95+
switch (pin_config.pin) {
96+
case 0:
97+
pps_reg = &RC0PPS;
98+
break;
99+
case 1:
100+
pps_reg = &RC1PPS;
101+
break;
102+
case 2:
103+
pps_reg = &RC2PPS;
104+
break;
105+
case 3:
106+
pps_reg = &RC3PPS;
107+
break;
108+
case 4:
109+
pps_reg = &RC4PPS;
110+
break;
111+
case 5:
112+
pps_reg = &RC5PPS;
113+
break;
114+
case 6:
115+
pps_reg = &RC6PPS;
116+
break;
117+
case 7:
118+
pps_reg = &RC7PPS;
119+
break;
120+
default:
121+
return W_INVALID_PARAM;
122+
}
119123
break;
120124
default:
121125
return W_INVALID_PARAM;
122-
}
123-
break;
124-
default:
125-
return W_INVALID_PARAM;
126126
}
127127

128128
// Assign the CCP module to the corresponding PPS register
@@ -139,23 +139,24 @@ w_status_t pwm_init(uint8_t ccp_module, pwm_pin_config_t pin_config, uint16_t pw
139139
return status; // Return error status if PPS configuration fails
140140
}
141141

142-
// Obtain the address of the CCPxCON register using switch (macros require compile-time constants)
142+
// Obtain the address of the CCPxCON register using switch (macros require compile-time
143+
// constants)
143144
volatile uint8_t *ccp_con;
144145
switch (ccp_module) {
145-
case 1:
146-
ccp_con = &CCP1CON;
147-
break;
148-
case 2:
149-
ccp_con = &CCP2CON;
150-
break;
151-
case 3:
152-
ccp_con = &CCP3CON;
153-
break;
154-
case 4:
155-
ccp_con = &CCP4CON;
156-
break;
157-
default:
158-
return W_INVALID_PARAM;
146+
case 1:
147+
ccp_con = &CCP1CON;
148+
break;
149+
case 2:
150+
ccp_con = &CCP2CON;
151+
break;
152+
case 3:
153+
ccp_con = &CCP3CON;
154+
break;
155+
case 4:
156+
ccp_con = &CCP4CON;
157+
break;
158+
default:
159+
return W_INVALID_PARAM;
159160
}
160161
*ccp_con = 0x8C; // Enable CCP module in PWM mode (PWM mode selection)
161162

@@ -167,8 +168,8 @@ w_status_t pwm_init(uint8_t ccp_module, pwm_pin_config_t pin_config, uint16_t pw
167168
T2CONbits.TMR2ON = 1; // Start Timer2 to begin PWM operation
168169

169170
// Wait for Timer2 to reach the period value before starting PWM
170-
while (!PIR1bits.TMR2IF) {} // Wait until Timer2 overflow flag is set
171-
PIR1bits.TMR2IF = 0; // Clear Timer2 interrupt flag to continue
171+
while (!PIR4bits.TMR2IF) {} // Wait until Timer2 overflow flag is set
172+
PIR4bits.TMR2IF = 0; // Clear Timer2 interrupt flag to continue
172173

173174
return W_SUCCESS; // Return success status after PWM initialization
174175
}
@@ -184,24 +185,24 @@ w_status_t pwm_update_duty_cycle(uint8_t ccp_module, uint16_t duty_cycle) {
184185
volatile uint8_t *ccpr_l;
185186
volatile uint8_t *ccpr_h;
186187
switch (ccp_module) {
187-
case 1:
188-
ccpr_l = &CCPR1L;
189-
ccpr_h = &CCPR1H;
190-
break;
191-
case 2:
192-
ccpr_l = &CCPR2L;
193-
ccpr_h = &CCPR2H;
194-
break;
195-
case 3:
196-
ccpr_l = &CCPR3L;
197-
ccpr_h = &CCPR3H;
198-
break;
199-
case 4:
200-
ccpr_l = &CCPR4L;
201-
ccpr_h = &CCPR4H;
202-
break;
203-
default:
204-
return W_INVALID_PARAM;
188+
case 1:
189+
ccpr_l = &CCPR1L;
190+
ccpr_h = &CCPR1H;
191+
break;
192+
case 2:
193+
ccpr_l = &CCPR2L;
194+
ccpr_h = &CCPR2H;
195+
break;
196+
case 3:
197+
ccpr_l = &CCPR3L;
198+
ccpr_h = &CCPR3H;
199+
break;
200+
case 4:
201+
ccpr_l = &CCPR4L;
202+
ccpr_h = &CCPR4H;
203+
break;
204+
default:
205+
return W_INVALID_PARAM;
205206
}
206207

207208
// Update the lower 8 bits of the duty cycle

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