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x-ximenax-ximena
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Switch both MCU and flash to QSPI mode
1 parent 03edb08 commit 17b8ff9

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+58
-107
lines changed

1 file changed

+58
-107
lines changed

‎stm32h7/mx25l25645g.c‎

Lines changed: 58 additions & 107 deletions
Original file line numberDiff line numberDiff line change
@@ -25,31 +25,30 @@ void MX_QUADSPI_Init(void) {
2525

2626
// Normal SPI command for flash
2727
const QSPI_CommandTypeDef CMD_BASE = {.Instruction = 0x0;
28-
.Address = 0x014;
29-
.AlternateBytes = 0x0;
30-
.AddressSize = QSPI_ADDRESS_8_BITS;
31-
.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS;
28+
// .Address = 0x014;
29+
// .AlternateBytes = 0x0;
30+
// .AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS;
3231
.DummyCycles = 0;
33-
.InstructionMode = QSPI_INSTRUCTION_NONE;
32+
.InstructionMode = QSPI_INSTRUCTION_1_LINE;
3433
.AddressMode = QSPI_ADDRESS_NONE;
3534
.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
3635
.DataMode = QSPI_DATA_NONE;
37-
.NbData = 0x0;
36+
// .NbData = 0x0;
3837
.DdrMode = QSPI_DDR_MODE_DISABLE;
39-
.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
38+
// .DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
4039
.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
4140
}
4241
;
4342

4443
// Quad SPI command for flash
45-
QSPI_CommandTypeDef QSPI_CMD_BASE = {.Instruction = 0x0;
46-
.Address = 0x014;
47-
.AlternateBytes = 0x0;
48-
.AddressSize = QSPI_ADDRESS_8_BITS;
44+
QSPI_CommandTypeDef CMD_BASE_QSPI = {.Instruction = 0x0;
45+
// .Address = 0x014;
46+
// .AlternateBytes = 0x0;
47+
// .AddressSize = QSPI_ADDRESS_8_BITS;
4948
.AlternateBytesSize =
5049
QSPI_ALTERNATE_BYTES_8_BITS; // may need to change to QSPI_ADDRESS_24_BITS or 32
5150
.DummyCycles = 0; // was 8
52-
.InstructionMode = QSPI_INSTRUCTION_1_LINE;
51+
.InstructionMode = QSPI_INSTRUCTION_4_LINES;
5352
.AddressMode = QSPI_ADDRESS_NONE;
5453
.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
5554
.DataMode = QSPI_DATA_NONE;
@@ -60,123 +59,75 @@ QSPI_CommandTypeDef QSPI_CMD_BASE = {.Instruction = 0x0;
6059
}
6160
;
6261

63-
static HAL_StatusTypeDef qspi_read_status(uint8_t *sr) {
64-
QSPI_CommandTypeDef cmd = QSPI_CMD_BASE;
65-
cmd.InstructionMode = QSPI_INSTRUCTION_1_LINE;
66-
cmd.Instruction = MX_CMD_RDSR;
67-
cmd.DataMode = QSPI_DATA_1_LINE;
68-
cmd.NbData = 1;
69-
70-
if (HAL_QSPI_Command(&hqspi, &cmd, Timeout) != HAL_OK) {
71-
return HAL_ERROR;
72-
}
73-
return HAL_QSPI_Receive(&hqspi, sr, Timeout);
74-
}
75-
76-
static HAL_StatusTypeDef qspi_read_config(uint8_t *cr) {
77-
QSPI_CommandTypeDef cmd = QSPI_CMD_BASE;
78-
cmd.InstructionMode = QSPI_INSTRUCTION_1_LINE;
79-
cmd.Instruction = MX_CMD_RDCR;
80-
cmd.DataMode = QSPI_DATA_1_LINE;
81-
cmd.NbData = 1;
82-
83-
if (HAL_QSPI_Command(&hqspi, &cmd, Timeout) != HAL_OK) {
84-
return HAL_ERROR;
85-
}
86-
return HAL_QSPI_Receive(&hqspi, cr, Timeout);
62+
static HAL_StatusTypeDef mx25l_exit_qpi(void)
63+
{
64+
QSPI_CommandTypeDef cmd = CMD_BASE_QSPI;
65+
cmd.Instruction = MX_CMD_RSTQIO; // 0xF5
66+
cmd.DataMode = QSPI_DATA_NONE;
67+
cmd.NbData = 0;
68+
return HAL_QSPI_Command(&hqspi, &cmd, Timeout);
8769
}
8870

89-
static HAL_StatusTypeDef qspi_write_enable(void) {
90-
QSPI_CommandTypeDef cmd = QSPI_CMD_BASE;
91-
cmd.InstructionMode = QSPI_INSTRUCTION_1_LINE;
92-
cmd.Instruction = MX_CMD_WREN;
93-
cmd.DataMode = QSPI_DATA_1_LINE;
71+
// Enable QSPI mode on the flash
72+
HAL_StatusTypeDef mx25l_enter_qpi(void) {
73+
QSPI_CommandTypeDef cmd = CMD_BASE;
74+
cmd.Instruction = MX_CMD_EQIO;
75+
cmd.DataMode = QSPI_DATA_NONE;
9476
cmd.NbData = 0;
95-
9677
return HAL_QSPI_Command(&hqspi, &cmd, Timeout);
9778
}
9879

99-
static HAL_StatusTypeDef qspi_mx25l_wait_wip0(void) {
100-
// Command: Read Status Register (RDSR)
101-
QSPI_CommandTypeDef cmd = {0};
102-
cmd.InstructionMode = QSPI_INSTRUCTION_1_LINE;
103-
cmd.Instruction = MX_CMD_RDSR;
104-
cmd.AddressMode = QSPI_ADDRESS_NONE;
105-
cmd.DataMode = QSPI_DATA_1_LINE;
106-
cmd.NbData = 1;
107-
cmd.DummyCycles = 0;
108-
cmd.DdrMode = QSPI_DDR_MODE_DISABLE;
109-
cmd.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
110-
111-
// Polling config: wait until WIP=0
112-
QSPI_AutoPollingTypeDef cfg = {0};
113-
cfg.Match = 0x00; // WIP must become 0
114-
cfg.Mask = 0x01; // Check only bit0
115-
cfg.MatchMode = QSPI_MATCH_MODE_AND;
116-
cfg.StatusBytesSize = 1;
117-
cfg.Interval = 0x10;
118-
cfg.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
119-
120-
return HAL_QSPI_AutoPolling(&hqspi, &cmd, &cfg, Timeout);
121-
}
122-
123-
// Enable QSPI mode on the MCU
124-
HAL_StatusTypeDef mx25l_enable_qe(void) {
125-
// Initialize status register and config register
126-
uint8_t sr = 0, cr = 0;
80+
// static HAL_StatusTypeDef qspi_write_enable(void) {
81+
// QSPI_CommandTypeDef cmd = CMD_BASE_QSPI;
82+
// cmd.Instruction = MX_CMD_WREN;
83+
// cmd.DataMode = QSPI_DATA_NONE;
84+
// cmd.NbData = 0;
12785

128-
if (qspi_read_status(&sr) != HAL_OK) {
129-
return HAL_ERROR;
130-
}
131-
if (qspi_read_config(&cr) != HAL_OK) {
132-
return HAL_ERROR;
133-
}
86+
// return HAL_QSPI_Command(&hqspi, &cmd, Timeout);
87+
// }
13488

135-
sr |= (1u << 6); // QE = bit 6
136-
uint8_t status_config_bytes[2] = {sr, cr};
89+
// static HAL_StatusTypeDef qspi_mx25l_wait_wip0(void) {
90+
// // Command: Read Status Register (RDSR)
91+
// QSPI_CommandTypeDef cmd = {0};
92+
// cmd.InstructionMode = QSPI_INSTRUCTION_1_LINE;
93+
// cmd.Instruction = MX_CMD_RDSR;
94+
// cmd.AddressMode = QSPI_ADDRESS_NONE;
95+
// cmd.DataMode = QSPI_DATA_1_LINE;
96+
// cmd.NbData = 1;
97+
// cmd.DummyCycles = 0;
98+
// cmd.DdrMode = QSPI_DDR_MODE_DISABLE;
99+
// cmd.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
137100

138-
if (qspi_write_enable() != HAL_OK) {
139-
return HAL_ERROR;
140-
}
101+
// // Polling config: wait until WIP=0
102+
// QSPI_AutoPollingTypeDef cfg = {0};
103+
// cfg.Match = 0x00; // WIP must become 0
104+
// cfg.Mask = 0x01; // Check only bit0
105+
// cfg.MatchMode = QSPI_MATCH_MODE_AND;
106+
// cfg.StatusBytesSize = 1;
107+
// cfg.Interval = 0x10;
108+
// cfg.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
141109

142-
QSPI_CommandTypeDef cmd = QSPI_CMD_BASE;
143-
cmd.InstructionMode = QSPI_INSTRUCTION_1_LINE;
144-
cmd.Instruction = MX_CMD_WRSR;
145-
cmd.DataMode = QSPI_DATA_1_LINE;
146-
cmd.NbData = 2;
110+
// return HAL_QSPI_AutoPolling(&hqspi, &cmd, &cfg, Timeout);
111+
// }
147112

148-
if (HAL_QSPI_Command(&hqspi, &cmd, Timeout) != HAL_OK) {
149-
return HAL_ERROR;
150-
}
151-
if (HAL_QSPI_Transmit(&hqspi, status_config_bytes, Timeout) != HAL_OK) {
152-
return HAL_ERROR;
153-
}
154113

155-
// Wait for the write to finish (WIP = 0)
156-
if (qspi_mx25l_wait_wip0() != HAL_OK) {
157-
return HAL_ERROR;
158-
}
159114

160-
// Verify QE really latched
161-
if (qspi_read_status(&sr) != HAL_OK) {
162-
return HAL_ERROR;
163-
}
164-
return (sr & (1u << 6)) ? HAL_OK : HAL_ERROR;
165-
}
166115

167116
int main(void) {
168-
// Change flash to qspi
169-
170117
HAL_Init();
171118
SystemClock_Config();
172119

173120
// Initialize the QSPI MSP
174121
MX_GPIO_Init();
175-
// Initialize the QSPI mode according to the parameters in the QSPI_InitTypeDef
122+
123+
// Initialize the QSPI mode with 1 instruction line, CMD_BASE
176124
MX_QUADSPI_Init();
177125

178-
// Enable quad mode
179-
mx25l_enable_qe();
126+
// Enable QPI mode on flash
127+
mx25l_enter_qpi();
128+
129+
// From now on instruction becomes 4 lines since qspi is enabled, QSPI_CMD_BASE
130+
180131

181132
while (1) {}
182133
}

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