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compact form for bit vector literals #16

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@drom

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@drom

Verilog allows bit vectors or arbitrary width. Example wire [26:0] state
VCD dump state changes like b101010101010101010101010101
We need a compact binary form of storing such constants.

LEB128 option

MSB --------------------------- LSB
        101010101010101010101010101 27-bit raw binary
       0101010101010101010101010101 Padded to a multiple of 7 bits
 0101010  1010101  0101010  1010101 Split into 7-bit groups
00101010 11010101 10101010 11010101 Add high 1 bits on all but last (most significant) group to form bytes
    0x2A     0xD5     0xAA     0xD5 In hexadecimal
-> D5 AA D5 2A                      Output stream (LSB to MSB)

Verilog / VCD also allows 4-state values like: b10101zzzz01010101xxxx010101

That can be represented as mask value:

       0 1 x z
value: 0 1 0 1
mask:  0 0 1 1

Mask also can be LEB128 encoded.
In the case of a 2-state vector, mask will occupy 1 byte.

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