From 3eff4809d20a5ef8dfbf1e54db2f1acdea820d1e Mon Sep 17 00:00:00 2001 From: Stefan Wallentowitz Date: Fri, 25 Jan 2019 12:53:51 +0100 Subject: [PATCH 1/3] [config] Fix help string Fix help string (ret_stack_size) --- configs/swerv.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/swerv.config b/configs/swerv.config index 6bf7e90..bf74124 100755 --- a/configs/swerv.config +++ b/configs/swerv.config @@ -99,7 +99,7 @@ User options: Additional direct options for the following variables: - -ret_size = {2, 3, 4, ... 8} + -ret_stack_size = {2, 3, 4, ... 8} size of return stack -btb_size = { 32, 48, 64, 128, 256, 512 } size of branch target buffer From 3717ed94ed22d801149831395fb88f291f7a1b9b Mon Sep 17 00:00:00 2001 From: Stefan Wallentowitz Date: Fri, 25 Jan 2019 12:59:24 +0100 Subject: [PATCH 2/3] [structure] Rename SystemVerilog to sv File type discovery is sometimes based on the extension. It is probably good practise to have SystemVerilog files with the .sv extension. --- design/dmi/{rvjtag_tap.v => rvjtag_tap.sv} | 0 design/flist.spyglass | 70 +++++++++++----------- design/flist.vcs | 2 +- design/flist.verilator | 2 +- design/flist.vlog | 2 +- 5 files changed, 38 insertions(+), 38 deletions(-) rename design/dmi/{rvjtag_tap.v => rvjtag_tap.sv} (100%) diff --git a/design/dmi/rvjtag_tap.v b/design/dmi/rvjtag_tap.sv similarity index 100% rename from design/dmi/rvjtag_tap.v rename to design/dmi/rvjtag_tap.sv diff --git a/design/flist.spyglass b/design/flist.spyglass index 137910a..5dbb3e2 100644 --- a/design/flist.spyglass +++ b/design/flist.spyglass @@ -1,45 +1,45 @@ -$RV_ROOT/design/swerv_wrapper.sv -$RV_ROOT/design/mem.sv -$RV_ROOT/design/pic_ctrl.sv -$RV_ROOT/design/swerv.sv -$RV_ROOT/design/dma_ctrl.sv -$RV_ROOT/design/ifu/ifu_aln_ctl.sv -$RV_ROOT/design/ifu/ifu_compress_ctl.sv -$RV_ROOT/design/ifu/ifu_ifc_ctl.sv -$RV_ROOT/design/ifu/ifu_bp_ctl.sv -$RV_ROOT/design/ifu/ifu_ic_mem.sv -$RV_ROOT/design/ifu/ifu_mem_ctl.sv -$RV_ROOT/design/ifu/ifu_iccm_mem.sv -$RV_ROOT/design/ifu/ifu.sv -$RV_ROOT/design/dec/dec_decode_ctl.sv -$RV_ROOT/design/dec/dec_gpr_ctl.sv -$RV_ROOT/design/dec/dec_ib_ctl.sv +$RV_ROOT/design/swerv_wrapper.sv +$RV_ROOT/design/mem.sv +$RV_ROOT/design/pic_ctrl.sv +$RV_ROOT/design/swerv.sv +$RV_ROOT/design/dma_ctrl.sv +$RV_ROOT/design/ifu/ifu_aln_ctl.sv +$RV_ROOT/design/ifu/ifu_compress_ctl.sv +$RV_ROOT/design/ifu/ifu_ifc_ctl.sv +$RV_ROOT/design/ifu/ifu_bp_ctl.sv +$RV_ROOT/design/ifu/ifu_ic_mem.sv +$RV_ROOT/design/ifu/ifu_mem_ctl.sv +$RV_ROOT/design/ifu/ifu_iccm_mem.sv +$RV_ROOT/design/ifu/ifu.sv +$RV_ROOT/design/dec/dec_decode_ctl.sv +$RV_ROOT/design/dec/dec_gpr_ctl.sv +$RV_ROOT/design/dec/dec_ib_ctl.sv $RV_ROOT/design/dec/dec_tlu_ctl.sv -$RV_ROOT/design/dec/dec_trigger.sv -$RV_ROOT/design/dec/dec.sv -$RV_ROOT/design/exu/exu_alu_ctl.sv -$RV_ROOT/design/exu/exu_mul_ctl.sv -$RV_ROOT/design/exu/exu_div_ctl.sv -$RV_ROOT/design/exu/exu.sv -$RV_ROOT/design/lsu/lsu.sv -$RV_ROOT/design/lsu/lsu_clkdomain.sv -$RV_ROOT/design/lsu/lsu_addrcheck.sv -$RV_ROOT/design/lsu/lsu_lsc_ctl.sv +$RV_ROOT/design/dec/dec_trigger.sv +$RV_ROOT/design/dec/dec.sv +$RV_ROOT/design/exu/exu_alu_ctl.sv +$RV_ROOT/design/exu/exu_mul_ctl.sv +$RV_ROOT/design/exu/exu_div_ctl.sv +$RV_ROOT/design/exu/exu.sv +$RV_ROOT/design/lsu/lsu.sv +$RV_ROOT/design/lsu/lsu_clkdomain.sv +$RV_ROOT/design/lsu/lsu_addrcheck.sv +$RV_ROOT/design/lsu/lsu_lsc_ctl.sv $RV_ROOT/design/lsu/lsu_stbuf.sv $RV_ROOT/design/lsu/lsu_bus_read_buffer.sv $RV_ROOT/design/lsu/lsu_bus_write_buffer.sv $RV_ROOT/design/lsu/lsu_bus_intf.sv $RV_ROOT/design/lsu/lsu_ecc.sv $RV_ROOT/design/lsu/lsu_dccm_mem.sv -$RV_ROOT/design/lsu/lsu_dccm_ctl.sv -$RV_ROOT/design/lsu/lsu_trigger.sv -$RV_ROOT/design/dbg/dbg.sv -$RV_ROOT/design/dmi/dmi_wrapper.v +$RV_ROOT/design/lsu/lsu_dccm_ctl.sv +$RV_ROOT/design/lsu/lsu_trigger.sv +$RV_ROOT/design/dbg/dbg.sv +$RV_ROOT/design/dmi/dmi_wrapper.v $RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v -$RV_ROOT/design/dmi/rvjtag_tap.v +$RV_ROOT/design/dmi/rvjtag_tap.sv $RV_ROOT/design/dmi/double_flop_sync.v $RV_ROOT/design/dmi/toggle_sync.v -$RV_ROOT/design/lib/beh_lib.sv -$RV_ROOT/design/lib/mem_lib.sv -$RV_ROOT/design/lib/ahb_to_axi4.sv -$RV_ROOT/design/lib/axi4_to_ahb.sv +$RV_ROOT/design/lib/beh_lib.sv +$RV_ROOT/design/lib/mem_lib.sv +$RV_ROOT/design/lib/ahb_to_axi4.sv +$RV_ROOT/design/lib/axi4_to_ahb.sv diff --git a/design/flist.vcs b/design/flist.vcs index 137910a..0923b57 100644 --- a/design/flist.vcs +++ b/design/flist.vcs @@ -36,7 +36,7 @@ $RV_ROOT/design/lsu/lsu_trigger.sv $RV_ROOT/design/dbg/dbg.sv $RV_ROOT/design/dmi/dmi_wrapper.v $RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v -$RV_ROOT/design/dmi/rvjtag_tap.v +$RV_ROOT/design/dmi/rvjtag_tap.sv $RV_ROOT/design/dmi/double_flop_sync.v $RV_ROOT/design/dmi/toggle_sync.v $RV_ROOT/design/lib/beh_lib.sv diff --git a/design/flist.verilator b/design/flist.verilator index 137910a..0923b57 100644 --- a/design/flist.verilator +++ b/design/flist.verilator @@ -36,7 +36,7 @@ $RV_ROOT/design/lsu/lsu_trigger.sv $RV_ROOT/design/dbg/dbg.sv $RV_ROOT/design/dmi/dmi_wrapper.v $RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v -$RV_ROOT/design/dmi/rvjtag_tap.v +$RV_ROOT/design/dmi/rvjtag_tap.sv $RV_ROOT/design/dmi/double_flop_sync.v $RV_ROOT/design/dmi/toggle_sync.v $RV_ROOT/design/lib/beh_lib.sv diff --git a/design/flist.vlog b/design/flist.vlog index 137910a..0923b57 100644 --- a/design/flist.vlog +++ b/design/flist.vlog @@ -36,7 +36,7 @@ $RV_ROOT/design/lsu/lsu_trigger.sv $RV_ROOT/design/dbg/dbg.sv $RV_ROOT/design/dmi/dmi_wrapper.v $RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v -$RV_ROOT/design/dmi/rvjtag_tap.v +$RV_ROOT/design/dmi/rvjtag_tap.sv $RV_ROOT/design/dmi/double_flop_sync.v $RV_ROOT/design/dmi/toggle_sync.v $RV_ROOT/design/lib/beh_lib.sv From 091e09b9d9a50c68eaac4f0c58765196320b40e0 Mon Sep 17 00:00:00 2001 From: Stefan Wallentowitz Date: Sun, 27 Jan 2019 17:30:15 +0100 Subject: [PATCH 3/3] [structure] Move types to package Currently the types are defined flatly in a definition file, which needs to be compiled in the compilation unit before the majority of the modules. The much cleaner way is to do that in a package and include it at the proper place so that both ports and the module itself know the types. --- design/dec/dec.sv | 1 + design/dec/dec_decode_ctl.sv | 2 + design/dec/dec_ib_ctl.sv | 1 + design/dec/dec_tlu_ctl.sv | 1 + design/dec/dec_trigger.sv | 8 +- design/exu/exu.sv | 1 + design/exu/exu_alu_ctl.sv | 1 + design/exu/exu_div_ctl.sv | 1 + design/exu/exu_mul_ctl.sv | 1 + design/flist.spyglass | 1 + design/flist.verilator | 69 ++-- design/ifu/ifu.sv | 1 + design/ifu/ifu_aln_ctl.sv | 1 + design/ifu/ifu_bp_ctl.sv | 5 +- design/ifu/ifu_mem_ctl.sv | 3 +- design/include/def.sv | 513 ---------------------------- design/lib/swerv_types.sv | 516 +++++++++++++++++++++++++++++ design/lsu/lsu.sv | 4 +- design/lsu/lsu_addrcheck.sv | 4 +- design/lsu/lsu_bus_intf.sv | 4 +- design/lsu/lsu_bus_read_buffer.sv | 4 +- design/lsu/lsu_bus_write_buffer.sv | 4 +- design/lsu/lsu_clkdomain.sv | 4 +- design/lsu/lsu_dccm_ctl.sv | 3 +- design/lsu/lsu_ecc.sv | 3 +- design/lsu/lsu_lsc_ctl.sv | 4 +- design/lsu/lsu_stbuf.sv | 1 + design/lsu/lsu_trigger.sv | 10 +- design/swerv.sv | 3 +- design/swerv_wrapper.sv | 11 +- tools/Makefile | 2 +- 31 files changed, 614 insertions(+), 573 deletions(-) delete mode 100644 design/include/def.sv create mode 100644 design/lib/swerv_types.sv diff --git a/design/dec/dec.sv b/design/dec/dec.sv index 717b22d..f06ca6d 100644 --- a/design/dec/dec.sv +++ b/design/dec/dec.sv @@ -28,6 +28,7 @@ //******************************************************************************** module dec + import swerv_types::*; ( input logic clk, input logic free_clk, diff --git a/design/dec/dec_decode_ctl.sv b/design/dec/dec_decode_ctl.sv index 7ce4b8f..02a8ef2 100644 --- a/design/dec/dec_decode_ctl.sv +++ b/design/dec/dec_decode_ctl.sv @@ -15,6 +15,7 @@ module dec_decode_ctl + import swerv_types::*; ( input logic [15:0] dec_i0_cinst_d, // 16b compressed instruction input logic [15:0] dec_i1_cinst_d, @@ -2430,6 +2431,7 @@ endmodule // 2) espresso -Dso -oeqntott legal.e | addassign -pre out. > legal_equation module dec_dec_ctl + import swerv_types::*; ( input logic [31:0] inst, diff --git a/design/dec/dec_ib_ctl.sv b/design/dec/dec_ib_ctl.sv index 6e36ef8..de4981b 100644 --- a/design/dec/dec_ib_ctl.sv +++ b/design/dec/dec_ib_ctl.sv @@ -14,6 +14,7 @@ // limitations under the License. module dec_ib_ctl + import swerv_types::*; ( input logic free_clk, // free clk input logic active_clk, // active clk if not halt / pause diff --git a/design/dec/dec_tlu_ctl.sv b/design/dec/dec_tlu_ctl.sv index 6ef2be1..9e77453 100644 --- a/design/dec/dec_tlu_ctl.sv +++ b/design/dec/dec_tlu_ctl.sv @@ -24,6 +24,7 @@ //******************************************************************************** module dec_tlu_ctl + import swerv_types::*; ( input logic clk, input logic active_clk, diff --git a/design/dec/dec_trigger.sv b/design/dec/dec_trigger.sv index db84804..eafb51c 100644 --- a/design/dec/dec_trigger.sv +++ b/design/dec/dec_trigger.sv @@ -22,9 +22,11 @@ // Comments: // //******************************************************************************** -module dec_trigger ( - input logic clk, - input logic rst_l, +module dec_trigger + import swerv_types::*; + ( + input logic clk, + input logic rst_l, input trigger_pkt_t [3:0] trigger_pkt_any, // Packet from tlu. 'select':0-pc,1-Opcode 'Execute' needs to be set for dec triggers to fire. 'match'-1 do mask, 0: full match input logic [31:1] dec_i0_pc_d, // i0 pc diff --git a/design/exu/exu.sv b/design/exu/exu.sv index 3bc6980..ff3b57d 100644 --- a/design/exu/exu.sv +++ b/design/exu/exu.sv @@ -15,6 +15,7 @@ module exu + import swerv_types::*; ( input logic clk, // Top level clock diff --git a/design/exu/exu_alu_ctl.sv b/design/exu/exu_alu_ctl.sv index c4a94a7..e8b2680 100644 --- a/design/exu/exu_alu_ctl.sv +++ b/design/exu/exu_alu_ctl.sv @@ -15,6 +15,7 @@ module exu_alu_ctl + import swerv_types::*; ( input logic clk, // Top level clock input logic active_clk, // Level 1 free clock diff --git a/design/exu/exu_div_ctl.sv b/design/exu/exu_div_ctl.sv index 7677273..4b1c01d 100644 --- a/design/exu/exu_div_ctl.sv +++ b/design/exu/exu_div_ctl.sv @@ -15,6 +15,7 @@ module exu_div_ctl + import swerv_types::*; ( input logic clk, // Top level clock input logic active_clk, // Level 1 active clock diff --git a/design/exu/exu_mul_ctl.sv b/design/exu/exu_mul_ctl.sv index 61e08c9..c63ea2e 100644 --- a/design/exu/exu_mul_ctl.sv +++ b/design/exu/exu_mul_ctl.sv @@ -15,6 +15,7 @@ module exu_mul_ctl + import swerv_types::*; ( input logic clk, // Top level clock input logic active_clk, // Level 1 active clock diff --git a/design/flist.spyglass b/design/flist.spyglass index 5dbb3e2..730371b 100644 --- a/design/flist.spyglass +++ b/design/flist.spyglass @@ -1,3 +1,4 @@ +$RV_ROOT/design/swerv_types.sv $RV_ROOT/design/swerv_wrapper.sv $RV_ROOT/design/mem.sv $RV_ROOT/design/pic_ctrl.sv diff --git a/design/flist.verilator b/design/flist.verilator index 0923b57..32eb49a 100644 --- a/design/flist.verilator +++ b/design/flist.verilator @@ -1,45 +1,46 @@ -$RV_ROOT/design/swerv_wrapper.sv -$RV_ROOT/design/mem.sv -$RV_ROOT/design/pic_ctrl.sv -$RV_ROOT/design/swerv.sv -$RV_ROOT/design/dma_ctrl.sv -$RV_ROOT/design/ifu/ifu_aln_ctl.sv -$RV_ROOT/design/ifu/ifu_compress_ctl.sv -$RV_ROOT/design/ifu/ifu_ifc_ctl.sv -$RV_ROOT/design/ifu/ifu_bp_ctl.sv -$RV_ROOT/design/ifu/ifu_ic_mem.sv -$RV_ROOT/design/ifu/ifu_mem_ctl.sv -$RV_ROOT/design/ifu/ifu_iccm_mem.sv -$RV_ROOT/design/ifu/ifu.sv -$RV_ROOT/design/dec/dec_decode_ctl.sv -$RV_ROOT/design/dec/dec_gpr_ctl.sv -$RV_ROOT/design/dec/dec_ib_ctl.sv +$RV_ROOT/design/lib/swerv_types.sv +$RV_ROOT/design/swerv_wrapper.sv +$RV_ROOT/design/mem.sv +$RV_ROOT/design/pic_ctrl.sv +$RV_ROOT/design/swerv.sv +$RV_ROOT/design/dma_ctrl.sv +$RV_ROOT/design/ifu/ifu_aln_ctl.sv +$RV_ROOT/design/ifu/ifu_compress_ctl.sv +$RV_ROOT/design/ifu/ifu_ifc_ctl.sv +$RV_ROOT/design/ifu/ifu_bp_ctl.sv +$RV_ROOT/design/ifu/ifu_ic_mem.sv +$RV_ROOT/design/ifu/ifu_mem_ctl.sv +$RV_ROOT/design/ifu/ifu_iccm_mem.sv +$RV_ROOT/design/ifu/ifu.sv +$RV_ROOT/design/dec/dec_decode_ctl.sv +$RV_ROOT/design/dec/dec_gpr_ctl.sv +$RV_ROOT/design/dec/dec_ib_ctl.sv $RV_ROOT/design/dec/dec_tlu_ctl.sv -$RV_ROOT/design/dec/dec_trigger.sv -$RV_ROOT/design/dec/dec.sv -$RV_ROOT/design/exu/exu_alu_ctl.sv -$RV_ROOT/design/exu/exu_mul_ctl.sv -$RV_ROOT/design/exu/exu_div_ctl.sv -$RV_ROOT/design/exu/exu.sv -$RV_ROOT/design/lsu/lsu.sv -$RV_ROOT/design/lsu/lsu_clkdomain.sv -$RV_ROOT/design/lsu/lsu_addrcheck.sv -$RV_ROOT/design/lsu/lsu_lsc_ctl.sv +$RV_ROOT/design/dec/dec_trigger.sv +$RV_ROOT/design/dec/dec.sv +$RV_ROOT/design/exu/exu_alu_ctl.sv +$RV_ROOT/design/exu/exu_mul_ctl.sv +$RV_ROOT/design/exu/exu_div_ctl.sv +$RV_ROOT/design/exu/exu.sv +$RV_ROOT/design/lsu/lsu.sv +$RV_ROOT/design/lsu/lsu_clkdomain.sv +$RV_ROOT/design/lsu/lsu_addrcheck.sv +$RV_ROOT/design/lsu/lsu_lsc_ctl.sv $RV_ROOT/design/lsu/lsu_stbuf.sv $RV_ROOT/design/lsu/lsu_bus_read_buffer.sv $RV_ROOT/design/lsu/lsu_bus_write_buffer.sv $RV_ROOT/design/lsu/lsu_bus_intf.sv $RV_ROOT/design/lsu/lsu_ecc.sv $RV_ROOT/design/lsu/lsu_dccm_mem.sv -$RV_ROOT/design/lsu/lsu_dccm_ctl.sv -$RV_ROOT/design/lsu/lsu_trigger.sv -$RV_ROOT/design/dbg/dbg.sv -$RV_ROOT/design/dmi/dmi_wrapper.v +$RV_ROOT/design/lsu/lsu_dccm_ctl.sv +$RV_ROOT/design/lsu/lsu_trigger.sv +$RV_ROOT/design/dbg/dbg.sv +$RV_ROOT/design/dmi/dmi_wrapper.v $RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v $RV_ROOT/design/dmi/rvjtag_tap.sv $RV_ROOT/design/dmi/double_flop_sync.v $RV_ROOT/design/dmi/toggle_sync.v -$RV_ROOT/design/lib/beh_lib.sv -$RV_ROOT/design/lib/mem_lib.sv -$RV_ROOT/design/lib/ahb_to_axi4.sv -$RV_ROOT/design/lib/axi4_to_ahb.sv +$RV_ROOT/design/lib/beh_lib.sv +$RV_ROOT/design/lib/mem_lib.sv +$RV_ROOT/design/lib/ahb_to_axi4.sv +$RV_ROOT/design/lib/axi4_to_ahb.sv diff --git a/design/ifu/ifu.sv b/design/ifu/ifu.sv index ed2e4e7..65d4265 100644 --- a/design/ifu/ifu.sv +++ b/design/ifu/ifu.sv @@ -20,6 +20,7 @@ //******************************************************************************** module ifu + import swerv_types::*; ( input logic free_clk, input logic active_clk, diff --git a/design/ifu/ifu_aln_ctl.sv b/design/ifu/ifu_aln_ctl.sv index 12a8ffe..4e211a9 100644 --- a/design/ifu/ifu_aln_ctl.sv +++ b/design/ifu/ifu_aln_ctl.sv @@ -19,6 +19,7 @@ // Function: Instruction aligner //******************************************************************************** module ifu_aln_ctl + import swerv_types::*; ( input logic active_clk, diff --git a/design/ifu/ifu_bp_ctl.sv b/design/ifu/ifu_bp_ctl.sv index 729df07..4bd8a22 100644 --- a/design/ifu/ifu_bp_ctl.sv +++ b/design/ifu/ifu_bp_ctl.sv @@ -17,14 +17,15 @@ //******************************************************************************** // Function: Branch predictor -// Comments: -// +// Comments: +// // // Bank3 : Bank2 : Bank1 : Bank0 // FA C 8 4 0 //******************************************************************************** module ifu_bp_ctl + import swerv_types::*; ( input logic clk, diff --git a/design/ifu/ifu_mem_ctl.sv b/design/ifu/ifu_mem_ctl.sv index 63757a2..8236745 100644 --- a/design/ifu/ifu_mem_ctl.sv +++ b/design/ifu/ifu_mem_ctl.sv @@ -21,7 +21,8 @@ // BFF -> F1 -> F2 -> A //******************************************************************************** -module ifu_mem_ctl +module ifu_mem_ctl + import swerv_types::*; ( input logic clk, input logic free_clk, // free clock always except during pause diff --git a/design/include/def.sv b/design/include/def.sv deleted file mode 100644 index de937ee..0000000 --- a/design/include/def.sv +++ /dev/null @@ -1,513 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright 2019 Western Digital Corporation or its affiliates. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// performance monitor stuff - -typedef struct packed { - logic [2:0] trace_rv_i_valid_ip; - logic [95:0] trace_rv_i_insn_ip; - logic [95:0] trace_rv_i_address_ip; - logic [2:0] trace_rv_i_exception_ip; - logic [4:0] trace_rv_i_ecause_ip; - logic [2:0] trace_rv_i_interrupt_ip; - logic [31:0] trace_rv_i_tval_ip; - } trace_pkt_t; - - -typedef enum logic [3:0] { - NULL = 4'b0000, - MUL = 4'b0001, - LOAD = 4'b0010, - STORE = 4'b0011, - ALU = 4'b0100, - CSRREAD = 4'b0101, - CSRWRITE = 4'b0110, - CSRRW = 4'b0111, - EBREAK = 4'b1000, - ECALL = 4'b1001, - FENCE = 4'b1010, - FENCEI = 4'b1011, - MRET = 4'b1100, - CONDBR = 4'b1101, - JAL = 4'b1110 - } inst_t; - -typedef struct packed { -`ifdef RV_ICACHE_ECC - logic [39:0] ecc; -`else - logic [7:0] parity; -`endif - } icache_err_pkt_t; - -typedef struct packed { - logic valid; - logic wb; - logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] tag; - logic [4:0] rd; - } load_cam_pkt_t; - -typedef struct packed { - logic pc0_call; - logic pc0_ret; - logic pc0_pc4; - logic pc1_call; - logic pc1_ret; - logic pc1_pc4; - } rets_pkt_t; -typedef struct packed { - logic valid; - logic [11:0] toffset; - logic [1:0] hist; - logic br_error; - logic br_start_error; - logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index; - logic [1:0] bank; - logic [31:1] prett; // predicted ret target - logic [`RV_BHT_GHR_RANGE] fghr; -`ifdef RV_BTB_48 - logic [1:0] way; -`else - logic way; -`endif - logic ret; - logic [`RV_BTB_BTAG_SIZE-1:0] btag; - } br_pkt_t; - -typedef struct packed { - logic valid; - logic [1:0] hist; - logic br_error; - logic br_start_error; - logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index; - logic [1:0] bank; - logic [`RV_BHT_GHR_RANGE] fghr; -`ifdef RV_BTB_48 - logic [1:0] way; -`else - logic way; -`endif - logic middle; - } br_tlu_pkt_t; - -typedef struct packed { - logic misp; - logic ataken; - logic boffset; - logic pc4; - logic [1:0] hist; - logic [11:0] toffset; - logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index; - logic [1:0] bank; - logic valid; - logic br_error; - logic br_start_error; - logic [31:1] prett; - logic pcall; - logic pret; - logic pja; - logic [`RV_BTB_BTAG_SIZE-1:0] btag; - logic [`RV_BHT_GHR_RANGE] fghr; -`ifdef RV_BTB_48 - logic [1:0] way; -`else - logic way; -`endif - } predict_pkt_t; - -typedef struct packed { - logic legal; - logic icaf; - logic icaf_f1; - logic perr; - logic sbecc; - logic fence_i; - logic [3:0] i0trigger; - logic [3:0] i1trigger; - inst_t pmu_i0_itype; // pmu - instruction type - inst_t pmu_i1_itype; // pmu - instruction type - logic pmu_i0_br_unpred; // pmu - logic pmu_i1_br_unpred; // pmu - logic pmu_divide; - logic pmu_lsu_misaligned; - } trap_pkt_t; - -typedef struct packed { - logic [4:0] i0rd; - logic i0mul; - logic i0load; - logic i0store; - logic i0div; - logic i0v; - logic i0valid; - logic i0secondary; - logic [1:0] i0rs1bype2; - logic [1:0] i0rs2bype2; - logic [3:0] i0rs1bype3; - logic [3:0] i0rs2bype3; - logic [4:0] i1rd; - logic i1mul; - logic i1load; - logic i1store; - logic i1v; - logic i1valid; - logic csrwen; - logic csrwonly; - logic [11:0] csrwaddr; - logic i1secondary; - logic [1:0] i1rs1bype2; - logic [1:0] i1rs2bype2; - logic [6:0] i1rs1bype3; - logic [6:0] i1rs2bype3; - } dest_pkt_t; - -typedef struct packed { - logic mul; - logic load; - logic sec; - logic alu; - } class_pkt_t; - -typedef struct packed { - logic [4:0] rs1; - logic [4:0] rs2; - logic [4:0] rd; - } reg_pkt_t; - - -typedef struct packed { - logic valid; - logic land; - logic lor; - logic lxor; - logic sll; - logic srl; - logic sra; - logic beq; - logic bne; - logic blt; - logic bge; - logic add; - logic sub; - logic slt; - logic unsign; - logic jal; - logic predict_t; - logic predict_nt; - logic csr_write; - logic csr_imm; - } alu_pkt_t; - -typedef struct packed { - logic by; - logic half; - logic word; - logic dword; // for dma - logic load; - logic store; - logic unsign; - logic dma; // dma pkt - logic store_data_bypass_c1; - logic load_ldst_bypass_c1; - logic store_data_bypass_c2; - logic store_data_bypass_i0_e2_c2; - logic [1:0] store_data_bypass_e4_c1; - logic [1:0] store_data_bypass_e4_c2; - logic [1:0] store_data_bypass_e4_c3; - logic valid; - } lsu_pkt_t; - -typedef struct packed { - logic exc_valid; - logic single_ecc_error; - logic inst_type; //0: Load, 1: Store - logic inst_pipe; //0: i0, 1: i1 - logic dma_valid; - logic exc_type; //0: MisAligned, 1: Access Fault - logic [31:0] addr; - } lsu_error_pkt_t; - -typedef struct packed { - logic alu; - logic rs1; - logic rs2; - logic imm12; - logic rd; - logic shimm5; - logic imm20; - logic pc; - logic load; - logic store; - logic lsu; - logic add; - logic sub; - logic land; - logic lor; - logic lxor; - logic sll; - logic sra; - logic srl; - logic slt; - logic unsign; - logic condbr; - logic beq; - logic bne; - logic bge; - logic blt; - logic jal; - logic by; - logic half; - logic word; - logic csr_read; - logic csr_clr; - logic csr_set; - logic csr_write; - logic csr_imm; - logic presync; - logic postsync; - logic ebreak; - logic ecall; - logic mret; - logic mul; - logic rs1_sign; - logic rs2_sign; - logic low; - logic div; - logic rem; - logic fence; - logic fence_i; - logic pm_alu; - logic legal; - } dec_pkt_t; - - -typedef struct packed { - logic valid; - logic rs1_sign; - logic rs2_sign; - logic low; - logic load_mul_rs1_bypass_e1; - logic load_mul_rs2_bypass_e1; - } mul_pkt_t; - -typedef struct packed { - logic valid; - logic unsign; - logic rem; - } div_pkt_t; - - -typedef struct packed { - logic clk_en; - } lsu_clken_pkt_t; - -typedef struct packed { - logic clk_en; - } ifu_clken_pkt_t; - - -typedef struct packed { - logic clk_en; - } dec_clken_pkt_t; - -typedef struct packed { - logic exu_mul_c1_e1_clken; - logic exu_mul_c2_e1_clken; - logic exu_mul_c1_e2_clken; - logic exu_mul_c2_e2_clken; - logic exu_mul_c1_e3_clken; - logic exu_mul_c2_e3_clken; - // AU clock enables - logic exu_au_i0_c1_e1_clken; - logic exu_au_i0_c1_e2_clken; - logic exu_au_i0_c1_e3_clken; - logic exu_au_i0_c1_e4_clken; - logic exu_au_i1_c1_e1_clken; - logic exu_au_i1_c1_e2_clken; - logic exu_au_i1_c1_e3_clken; - logic exu_au_i1_c1_e4_clken; - logic exu_au_i0_c2_e1_clken; - logic exu_au_i0_c2_e2_clken; - logic exu_au_i0_c2_e3_clken; - logic exu_au_i0_c2_e4_clken; - logic exu_au_i1_c2_e1_clken; - logic exu_au_i1_c2_e2_clken; - logic exu_au_i1_c2_e3_clken; - logic exu_au_i1_c2_e4_clken; - } exu_clken_pkt_t; - -typedef struct packed { - logic free_clk; - } lsu_clk_pkt_t; - -typedef struct packed { - logic free_clk; - } ifu_clk_pkt_t; - - -typedef struct packed { - logic free_clk; - } dec_clk_pkt_t; - -typedef struct packed { - // Mul clocks - logic exu_mul_c1_e1_clk; - logic exu_mul_c2_e1_clk; - logic exu_mul_c1_e2_clk; - logic exu_mul_c2_e2_clk; - logic exu_mul_c1_e3_clk; - logic exu_mul_c2_e3_clk; - // AU clocks - logic exu_au_i0_c1_e1_clk; - logic exu_au_i0_c1_e2_clk; - logic exu_au_i0_c1_e3_clk; - logic exu_au_i0_c1_e4_clk; - logic exu_au_i1_c1_e1_clk; - logic exu_au_i1_c1_e2_clk; - logic exu_au_i1_c1_e3_clk; - logic exu_au_i1_c1_e4_clk; - logic exu_au_i0_c2_e1_clk; - logic exu_au_i0_c2_e2_clk; - logic exu_au_i0_c2_e3_clk; - logic exu_au_i0_c2_e4_clk; - logic exu_au_i1_c2_e1_clk; - logic exu_au_i1_c2_e2_clk; - logic exu_au_i1_c2_e3_clk; - logic exu_au_i1_c2_e4_clk; - - } exu_clk_pkt_t; - - -typedef struct packed { - logic select; - logic match; - logic store; - logic load; - logic execute; - logic m; - logic [31:0] tdata2; - } trigger_pkt_t; - - -typedef struct packed { -`ifdef RV_ICACHE_ECC - logic [41:0] icache_wrdata; // {dicad0[31:0], dicad1[1:0]} -`else - logic [33:0] icache_wrdata; // {dicad0[31:0], dicad1[1:0]} -`endif - logic [18:2] icache_dicawics; - logic icache_rd_valid; - logic icache_wr_valid; - } cache_debug_pkt_t; - -typedef struct packed { - // AXI Write Channels - logic axi_awvalid; - logic [31:0] axi_awaddr; - logic [2:0] axi_awsize; - logic [2:0] axi_awprot; - logic [7:0] axi_awlen; - logic [1:0] axi_awburst; - - logic axi_wvalid; - logic [63:0] axi_wdata; - logic [7:0] axi_wstrb; - logic axi_wlast; - - logic axi_bready; - - // AXI Read Channels - logic axi_arvalid; - logic [31:0] axi_araddr; - logic [2:0] axi_arsize; - logic [2:0] axi_arprot; - - logic axi_rready; - } axi4_mstr_pkt_t; - -typedef struct packed { - // AXI Write Channels - logic axi_bvalid; - logic axi_bready; - logic [1:0] axi_bresp; - - logic axi_awready; - logic axi_wready; - - // AXI Read Channels - logic axi_rvalid; - logic [63:0] axi_rdata; - logic [1:0] axi_rresp; - - logic axi_arready; - - } axi4_slv_pkt_t; - - -typedef struct packed { - axi4_mstr_pkt_t axi4_pkt; - logic [`RV_LSU_BUS_TAG-1:0] axi_awid; - logic [`RV_LSU_BUS_TAG-1:0] axi_arid; - - } lsu_axi4_mstr_pkt_t; - -typedef struct packed { - axi4_mstr_pkt_t axi4_pkt; - logic [`RV_IFU_BUS_TAG-1:0] axi_awid; - logic [`RV_IFU_BUS_TAG-1:0] axi_arid; - - } ifu_axi4_mstr_pkt_t; - -typedef struct packed { - axi4_mstr_pkt_t axi4_pkt; - logic [`RV_SB_BUS_TAG-1:0] axi_awid; - logic [`RV_SB_BUS_TAG-1:0] axi_arid; - - } sb_axi4_mstr_pkt_t; - -typedef struct packed { - axi4_slv_pkt_t axi4_pkt; - logic [`RV_DMA_BUS_TAG-1:0] axi_awid; - logic [`RV_DMA_BUS_TAG-1:0] axi_arid; - - } dma_axi4_mstr_pkt_t; - -typedef struct packed { - axi4_slv_pkt_t axi4_pkt; - logic [`RV_LSU_BUS_TAG-1:0] axi_bid; - logic [`RV_LSU_BUS_TAG-1:0] axi_rid; - - } lsu_axi4_slv_pkt_t; - -typedef struct packed { - axi4_slv_pkt_t axi4_pkt; - logic [`RV_IFU_BUS_TAG-1:0] axi_bid; - logic [`RV_IFU_BUS_TAG-1:0] axi_rid; - - } ifu_axi4_slv_pkt_t; - -typedef struct packed { - axi4_slv_pkt_t axi4_pkt; - logic [`RV_SB_BUS_TAG-1:0] axi_bid; - logic [`RV_SB_BUS_TAG-1:0] axi_rid; - - } sb_axi4_slv_pkt_t; - -typedef struct packed { - axi4_slv_pkt_t axi4_pkt; - logic [`RV_DMA_BUS_TAG-1:0] axi_bid; - logic [`RV_DMA_BUS_TAG-1:0] axi_rid; - - } dma_axi4_slv_pkt_t; diff --git a/design/lib/swerv_types.sv b/design/lib/swerv_types.sv new file mode 100644 index 0000000..3aa4357 --- /dev/null +++ b/design/lib/swerv_types.sv @@ -0,0 +1,516 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// performance monitor stuff + +package swerv_types; + +typedef struct packed { + logic [2:0] trace_rv_i_valid_ip; + logic [95:0] trace_rv_i_insn_ip; + logic [95:0] trace_rv_i_address_ip; + logic [2:0] trace_rv_i_exception_ip; + logic [4:0] trace_rv_i_ecause_ip; + logic [2:0] trace_rv_i_interrupt_ip; + logic [31:0] trace_rv_i_tval_ip; + } trace_pkt_t; + + +typedef enum logic [3:0] { + NULL = 4'b0000, + MUL = 4'b0001, + LOAD = 4'b0010, + STORE = 4'b0011, + ALU = 4'b0100, + CSRREAD = 4'b0101, + CSRWRITE = 4'b0110, + CSRRW = 4'b0111, + EBREAK = 4'b1000, + ECALL = 4'b1001, + FENCE = 4'b1010, + FENCEI = 4'b1011, + MRET = 4'b1100, + CONDBR = 4'b1101, + JAL = 4'b1110 + } inst_t; + +typedef struct packed { +`ifdef RV_ICACHE_ECC + logic [39:0] ecc; +`else + logic [7:0] parity; +`endif + } icache_err_pkt_t; + +typedef struct packed { + logic valid; + logic wb; + logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] tag; + logic [4:0] rd; + } load_cam_pkt_t; + +typedef struct packed { + logic pc0_call; + logic pc0_ret; + logic pc0_pc4; + logic pc1_call; + logic pc1_ret; + logic pc1_pc4; + } rets_pkt_t; +typedef struct packed { + logic valid; + logic [11:0] toffset; + logic [1:0] hist; + logic br_error; + logic br_start_error; + logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index; + logic [1:0] bank; + logic [31:1] prett; // predicted ret target + logic [`RV_BHT_GHR_RANGE] fghr; +`ifdef RV_BTB_48 + logic [1:0] way; +`else + logic way; +`endif + logic ret; + logic [`RV_BTB_BTAG_SIZE-1:0] btag; + } br_pkt_t; + +typedef struct packed { + logic valid; + logic [1:0] hist; + logic br_error; + logic br_start_error; + logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index; + logic [1:0] bank; + logic [`RV_BHT_GHR_RANGE] fghr; +`ifdef RV_BTB_48 + logic [1:0] way; +`else + logic way; +`endif + logic middle; + } br_tlu_pkt_t; + +typedef struct packed { + logic misp; + logic ataken; + logic boffset; + logic pc4; + logic [1:0] hist; + logic [11:0] toffset; + logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] index; + logic [1:0] bank; + logic valid; + logic br_error; + logic br_start_error; + logic [31:1] prett; + logic pcall; + logic pret; + logic pja; + logic [`RV_BTB_BTAG_SIZE-1:0] btag; + logic [`RV_BHT_GHR_RANGE] fghr; +`ifdef RV_BTB_48 + logic [1:0] way; +`else + logic way; +`endif + } predict_pkt_t; + +typedef struct packed { + logic legal; + logic icaf; + logic icaf_f1; + logic perr; + logic sbecc; + logic fence_i; + logic [3:0] i0trigger; + logic [3:0] i1trigger; + inst_t pmu_i0_itype; // pmu - instruction type + inst_t pmu_i1_itype; // pmu - instruction type + logic pmu_i0_br_unpred; // pmu + logic pmu_i1_br_unpred; // pmu + logic pmu_divide; + logic pmu_lsu_misaligned; + } trap_pkt_t; + +typedef struct packed { + logic [4:0] i0rd; + logic i0mul; + logic i0load; + logic i0store; + logic i0div; + logic i0v; + logic i0valid; + logic i0secondary; + logic [1:0] i0rs1bype2; + logic [1:0] i0rs2bype2; + logic [3:0] i0rs1bype3; + logic [3:0] i0rs2bype3; + logic [4:0] i1rd; + logic i1mul; + logic i1load; + logic i1store; + logic i1v; + logic i1valid; + logic csrwen; + logic csrwonly; + logic [11:0] csrwaddr; + logic i1secondary; + logic [1:0] i1rs1bype2; + logic [1:0] i1rs2bype2; + logic [6:0] i1rs1bype3; + logic [6:0] i1rs2bype3; + } dest_pkt_t; + +typedef struct packed { + logic mul; + logic load; + logic sec; + logic alu; + } class_pkt_t; + +typedef struct packed { + logic [4:0] rs1; + logic [4:0] rs2; + logic [4:0] rd; + } reg_pkt_t; + + +typedef struct packed { + logic valid; + logic land; + logic lor; + logic lxor; + logic sll; + logic srl; + logic sra; + logic beq; + logic bne; + logic blt; + logic bge; + logic add; + logic sub; + logic slt; + logic unsign; + logic jal; + logic predict_t; + logic predict_nt; + logic csr_write; + logic csr_imm; + } alu_pkt_t; + +typedef struct packed { + logic by; + logic half; + logic word; + logic dword; // for dma + logic load; + logic store; + logic unsign; + logic dma; // dma pkt + logic store_data_bypass_c1; + logic load_ldst_bypass_c1; + logic store_data_bypass_c2; + logic store_data_bypass_i0_e2_c2; + logic [1:0] store_data_bypass_e4_c1; + logic [1:0] store_data_bypass_e4_c2; + logic [1:0] store_data_bypass_e4_c3; + logic valid; + } lsu_pkt_t; + +typedef struct packed { + logic exc_valid; + logic single_ecc_error; + logic inst_type; //0: Load, 1: Store + logic inst_pipe; //0: i0, 1: i1 + logic dma_valid; + logic exc_type; //0: MisAligned, 1: Access Fault + logic [31:0] addr; + } lsu_error_pkt_t; + +typedef struct packed { + logic alu; + logic rs1; + logic rs2; + logic imm12; + logic rd; + logic shimm5; + logic imm20; + logic pc; + logic load; + logic store; + logic lsu; + logic add; + logic sub; + logic land; + logic lor; + logic lxor; + logic sll; + logic sra; + logic srl; + logic slt; + logic unsign; + logic condbr; + logic beq; + logic bne; + logic bge; + logic blt; + logic jal; + logic by; + logic half; + logic word; + logic csr_read; + logic csr_clr; + logic csr_set; + logic csr_write; + logic csr_imm; + logic presync; + logic postsync; + logic ebreak; + logic ecall; + logic mret; + logic mul; + logic rs1_sign; + logic rs2_sign; + logic low; + logic div; + logic rem; + logic fence; + logic fence_i; + logic pm_alu; + logic legal; + } dec_pkt_t; + + +typedef struct packed { + logic valid; + logic rs1_sign; + logic rs2_sign; + logic low; + logic load_mul_rs1_bypass_e1; + logic load_mul_rs2_bypass_e1; + } mul_pkt_t; + +typedef struct packed { + logic valid; + logic unsign; + logic rem; + } div_pkt_t; + + +typedef struct packed { + logic clk_en; + } lsu_clken_pkt_t; + +typedef struct packed { + logic clk_en; + } ifu_clken_pkt_t; + + +typedef struct packed { + logic clk_en; + } dec_clken_pkt_t; + +typedef struct packed { + logic exu_mul_c1_e1_clken; + logic exu_mul_c2_e1_clken; + logic exu_mul_c1_e2_clken; + logic exu_mul_c2_e2_clken; + logic exu_mul_c1_e3_clken; + logic exu_mul_c2_e3_clken; + // AU clock enables + logic exu_au_i0_c1_e1_clken; + logic exu_au_i0_c1_e2_clken; + logic exu_au_i0_c1_e3_clken; + logic exu_au_i0_c1_e4_clken; + logic exu_au_i1_c1_e1_clken; + logic exu_au_i1_c1_e2_clken; + logic exu_au_i1_c1_e3_clken; + logic exu_au_i1_c1_e4_clken; + logic exu_au_i0_c2_e1_clken; + logic exu_au_i0_c2_e2_clken; + logic exu_au_i0_c2_e3_clken; + logic exu_au_i0_c2_e4_clken; + logic exu_au_i1_c2_e1_clken; + logic exu_au_i1_c2_e2_clken; + logic exu_au_i1_c2_e3_clken; + logic exu_au_i1_c2_e4_clken; + } exu_clken_pkt_t; + +typedef struct packed { + logic free_clk; + } lsu_clk_pkt_t; + +typedef struct packed { + logic free_clk; + } ifu_clk_pkt_t; + + +typedef struct packed { + logic free_clk; + } dec_clk_pkt_t; + +typedef struct packed { + // Mul clocks + logic exu_mul_c1_e1_clk; + logic exu_mul_c2_e1_clk; + logic exu_mul_c1_e2_clk; + logic exu_mul_c2_e2_clk; + logic exu_mul_c1_e3_clk; + logic exu_mul_c2_e3_clk; + // AU clocks + logic exu_au_i0_c1_e1_clk; + logic exu_au_i0_c1_e2_clk; + logic exu_au_i0_c1_e3_clk; + logic exu_au_i0_c1_e4_clk; + logic exu_au_i1_c1_e1_clk; + logic exu_au_i1_c1_e2_clk; + logic exu_au_i1_c1_e3_clk; + logic exu_au_i1_c1_e4_clk; + logic exu_au_i0_c2_e1_clk; + logic exu_au_i0_c2_e2_clk; + logic exu_au_i0_c2_e3_clk; + logic exu_au_i0_c2_e4_clk; + logic exu_au_i1_c2_e1_clk; + logic exu_au_i1_c2_e2_clk; + logic exu_au_i1_c2_e3_clk; + logic exu_au_i1_c2_e4_clk; + + } exu_clk_pkt_t; + + +typedef struct packed { + logic select; + logic match; + logic store; + logic load; + logic execute; + logic m; + logic [31:0] tdata2; + } trigger_pkt_t; + + +typedef struct packed { +`ifdef RV_ICACHE_ECC + logic [41:0] icache_wrdata; // {dicad0[31:0], dicad1[1:0]} +`else + logic [33:0] icache_wrdata; // {dicad0[31:0], dicad1[1:0]} +`endif + logic [18:2] icache_dicawics; + logic icache_rd_valid; + logic icache_wr_valid; + } cache_debug_pkt_t; + +typedef struct packed { + // AXI Write Channels + logic axi_awvalid; + logic [31:0] axi_awaddr; + logic [2:0] axi_awsize; + logic [2:0] axi_awprot; + logic [7:0] axi_awlen; + logic [1:0] axi_awburst; + + logic axi_wvalid; + logic [63:0] axi_wdata; + logic [7:0] axi_wstrb; + logic axi_wlast; + + logic axi_bready; + + // AXI Read Channels + logic axi_arvalid; + logic [31:0] axi_araddr; + logic [2:0] axi_arsize; + logic [2:0] axi_arprot; + + logic axi_rready; + } axi4_mstr_pkt_t; + +typedef struct packed { + // AXI Write Channels + logic axi_bvalid; + logic axi_bready; + logic [1:0] axi_bresp; + + logic axi_awready; + logic axi_wready; + + // AXI Read Channels + logic axi_rvalid; + logic [63:0] axi_rdata; + logic [1:0] axi_rresp; + + logic axi_arready; + + } axi4_slv_pkt_t; + + +typedef struct packed { + axi4_mstr_pkt_t axi4_pkt; + logic [`RV_LSU_BUS_TAG-1:0] axi_awid; + logic [`RV_LSU_BUS_TAG-1:0] axi_arid; + + } lsu_axi4_mstr_pkt_t; + +typedef struct packed { + axi4_mstr_pkt_t axi4_pkt; + logic [`RV_IFU_BUS_TAG-1:0] axi_awid; + logic [`RV_IFU_BUS_TAG-1:0] axi_arid; + + } ifu_axi4_mstr_pkt_t; + +typedef struct packed { + axi4_mstr_pkt_t axi4_pkt; + logic [`RV_SB_BUS_TAG-1:0] axi_awid; + logic [`RV_SB_BUS_TAG-1:0] axi_arid; + + } sb_axi4_mstr_pkt_t; + +typedef struct packed { + axi4_slv_pkt_t axi4_pkt; + logic [`RV_DMA_BUS_TAG-1:0] axi_awid; + logic [`RV_DMA_BUS_TAG-1:0] axi_arid; + + } dma_axi4_mstr_pkt_t; + +typedef struct packed { + axi4_slv_pkt_t axi4_pkt; + logic [`RV_LSU_BUS_TAG-1:0] axi_bid; + logic [`RV_LSU_BUS_TAG-1:0] axi_rid; + + } lsu_axi4_slv_pkt_t; + +typedef struct packed { + axi4_slv_pkt_t axi4_pkt; + logic [`RV_IFU_BUS_TAG-1:0] axi_bid; + logic [`RV_IFU_BUS_TAG-1:0] axi_rid; + + } ifu_axi4_slv_pkt_t; + +typedef struct packed { + axi4_slv_pkt_t axi4_pkt; + logic [`RV_SB_BUS_TAG-1:0] axi_bid; + logic [`RV_SB_BUS_TAG-1:0] axi_rid; + + } sb_axi4_slv_pkt_t; + +typedef struct packed { + axi4_slv_pkt_t axi4_pkt; + logic [`RV_DMA_BUS_TAG-1:0] axi_bid; + logic [`RV_DMA_BUS_TAG-1:0] axi_rid; + + } dma_axi4_slv_pkt_t; +endpackage // swerv_types diff --git a/design/lsu/lsu.sv b/design/lsu/lsu.sv index 61a9332..282be0c 100644 --- a/design/lsu/lsu.sv +++ b/design/lsu/lsu.sv @@ -25,7 +25,9 @@ // //******************************************************************************** -module lsu ( +module lsu + import swerv_types::*; + ( input logic [31:0] i0_result_e4_eff, // I0 e4 result for e4 -> dc3 store forwarding input logic [31:0] i1_result_e4_eff, // I1 e4 result for e4 -> dc3 store forwarding diff --git a/design/lsu/lsu_addrcheck.sv b/design/lsu/lsu_addrcheck.sv index c00581b..31c04bc 100644 --- a/design/lsu/lsu_addrcheck.sv +++ b/design/lsu/lsu_addrcheck.sv @@ -22,7 +22,9 @@ // Comments: // //******************************************************************************** -module lsu_addrcheck ( +module lsu_addrcheck + import swerv_types::*; + ( input logic lsu_freeze_c2_dc2_clk, // clock input logic lsu_freeze_c2_dc3_clk, input logic rst_l, // reset diff --git a/design/lsu/lsu_bus_intf.sv b/design/lsu/lsu_bus_intf.sv index d074140..6affff9 100644 --- a/design/lsu/lsu_bus_intf.sv +++ b/design/lsu/lsu_bus_intf.sv @@ -22,7 +22,9 @@ // Comments: // //******************************************************************************** -module lsu_bus_intf ( +module lsu_bus_intf + import swerv_types::*; + ( input logic clk, input logic rst_l, input logic scan_mode, diff --git a/design/lsu/lsu_bus_read_buffer.sv b/design/lsu/lsu_bus_read_buffer.sv index 5a9a038..33a0af0 100644 --- a/design/lsu/lsu_bus_read_buffer.sv +++ b/design/lsu/lsu_bus_read_buffer.sv @@ -47,7 +47,9 @@ function automatic logic [31:0] lsu_align; endfunction // lsu_bus_read_buffer -module lsu_bus_read_buffer ( +module lsu_bus_read_buffer + import swerv_types::*; + ( input logic lsu_freeze_c2_dc3_clk, input logic lsu_c2_dc3_clk, // per stage clock diff --git a/design/lsu/lsu_bus_write_buffer.sv b/design/lsu/lsu_bus_write_buffer.sv index d195b9d..5d8ad46 100644 --- a/design/lsu/lsu_bus_write_buffer.sv +++ b/design/lsu/lsu_bus_write_buffer.sv @@ -63,7 +63,9 @@ function automatic logic [2:0] get_wrbuf_addr; endfunction -module lsu_bus_write_buffer ( +module lsu_bus_write_buffer + import swerv_types::*; + ( input logic lsu_wrbuf_c1_clk, input logic lsu_freeze_c2_dc3_clk, input logic lsu_c2_dc4_clk, diff --git a/design/lsu/lsu_clkdomain.sv b/design/lsu/lsu_clkdomain.sv index 30c0ebb..0b92c63 100644 --- a/design/lsu/lsu_clkdomain.sv +++ b/design/lsu/lsu_clkdomain.sv @@ -24,7 +24,9 @@ // //******************************************************************************** -module lsu_clkdomain ( +module lsu_clkdomain + import swerv_types::*; + ( input logic clk, // clock input logic free_clk, // clock input logic rst_l, // reset diff --git a/design/lsu/lsu_dccm_ctl.sv b/design/lsu/lsu_dccm_ctl.sv index 57eb96c..382d757 100644 --- a/design/lsu/lsu_dccm_ctl.sv +++ b/design/lsu/lsu_dccm_ctl.sv @@ -26,7 +26,8 @@ // // //******************************************************************************** -module lsu_dccm_ctl +module lsu_dccm_ctl + import swerv_types::*; ( input logic lsu_freeze_c2_dc2_clk, // clocks input logic lsu_freeze_c2_dc3_clk, diff --git a/design/lsu/lsu_ecc.sv b/design/lsu/lsu_ecc.sv index 2559ab8..819acf3 100644 --- a/design/lsu/lsu_ecc.sv +++ b/design/lsu/lsu_ecc.sv @@ -25,7 +25,8 @@ // DC1 -> DC2 -> DC3 -> DC4 (Commit) // //******************************************************************************** -module lsu_ecc +module lsu_ecc + import swerv_types::*; ( input logic lsu_c2_dc4_clk, // clocks diff --git a/design/lsu/lsu_lsc_ctl.sv b/design/lsu/lsu_lsc_ctl.sv index 6c2acc9..19292c1 100644 --- a/design/lsu/lsu_lsc_ctl.sv +++ b/design/lsu/lsu_lsc_ctl.sv @@ -25,7 +25,9 @@ // DC1 -> DC2 -> DC3 -> DC4 (Commit) // //******************************************************************************** -module lsu_lsc_ctl ( +module lsu_lsc_ctl + import swerv_types::*; +( input logic rst_l, // clocks per pipe input logic lsu_c1_dc4_clk, diff --git a/design/lsu/lsu_stbuf.sv b/design/lsu/lsu_stbuf.sv index 072b2f1..86169fb 100644 --- a/design/lsu/lsu_stbuf.sv +++ b/design/lsu/lsu_stbuf.sv @@ -28,6 +28,7 @@ module lsu_stbuf + import swerv_types::*; ( input logic clk, // core clock input logic rst_l, // reset diff --git a/design/lsu/lsu_trigger.sv b/design/lsu/lsu_trigger.sv index 92c883f..30de1dc 100644 --- a/design/lsu/lsu_trigger.sv +++ b/design/lsu/lsu_trigger.sv @@ -22,10 +22,12 @@ // Comments: // //******************************************************************************** -module lsu_trigger ( - input logic clk, // clock - input logic lsu_free_c2_clk, // clock - input logic rst_l, // reset +module lsu_trigger + import swerv_types::*; +( + input logic clk, // clock + input logic lsu_free_c2_clk, // clock + input logic rst_l, // reset input trigger_pkt_t [3:0] trigger_pkt_any, // trigger packet from dec input lsu_pkt_t lsu_pkt_dc3, // lsu packet diff --git a/design/swerv.sv b/design/swerv.sv index 6e2811c..2e2c8a6 100644 --- a/design/swerv.sv +++ b/design/swerv.sv @@ -20,7 +20,8 @@ // Comments: // //******************************************************************************** -module swerv +module swerv + import swerv_types::*; ( input logic clk, input logic rst_l, diff --git a/design/swerv_wrapper.sv b/design/swerv_wrapper.sv index d66e01a..ec10542 100644 --- a/design/swerv_wrapper.sv +++ b/design/swerv_wrapper.sv @@ -21,11 +21,12 @@ // //******************************************************************************** `include "build.h" -//`include "def.sv" -module swerv_wrapper ( - input logic clk, - input logic rst_l, - input logic [31:1] rst_vec, +module swerv_wrapper + import swerv_types::*; + ( + input logic clk, + input logic rst_l, + input logic [31:1] rst_vec, input logic nmi_int, input logic [31:1] nmi_vec, diff --git a/tools/Makefile b/tools/Makefile index 9eb930b..966d5a4 100755 --- a/tools/Makefile +++ b/tools/Makefile @@ -24,7 +24,7 @@ ifeq ($(strip $(snapshot)),) snapshot = default endif -defines = ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh ${RV_ROOT}/design/include/def.sv +defines = ${RV_ROOT}/configs/snapshots/$(snapshot)/common_defines.vh includes = -I${RV_ROOT}/design/include -I${RV_ROOT}/design/lib -I${RV_ROOT}/design/dmi -I${RV_ROOT}/configs/snapshots/$(snapshot) all: clean verilator