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73 | 73 | #define FLASH_PAGE_SIZE (0x800) /* 2KB */ |
74 | 74 |
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75 | 75 | /* Register values */ |
| 76 | +#define FLASH_SR_CFGBSY (1 << 18) /* RM0444 - 3.7.4 - FLASH_SR */ |
| 77 | +#define FLASH_SR_BSY2 (1 << 17) /* RM0444 - 3.7.4 - FLASH_SR */ |
76 | 78 | #define FLASH_SR_BSY1 (1 << 16) /* RM0444 - 3.7.4 - FLASH_SR */ |
77 | 79 | #define FLASH_SR_SIZERR (1 << 6) /* RM0444 - 3.7.4 - FLASH_SR */ |
78 | 80 | #define FLASH_SR_PGAERR (1 << 5) /* RM0444 - 3.7.4 - FLASH_SR */ |
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90 | 92 | #define FLASH_CR_PNB_SHIFT 3 /* RM0444 - 3.7.5 - FLASH_CR - PNB bits 9:3 */ |
91 | 93 | #define FLASH_CR_PNB_MASK 0x7f /* RM0444 - 3.7.5 - FLASH_CR - PNB bits 9:3 - 7 bits */ |
92 | 94 |
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| 95 | +#define FLASH_CR_BKER (1 << 13) |
| 96 | +#define FLASH_CR_BKER_BITMASK 0x2000 |
| 97 | +#define BANK_SIZE (0x40000) |
| 98 | + |
| 99 | +#define FLASH_CR_PNB_SHIFT 3 /* RM0444 - 3.7.5 - FLASH_CR - PNB bits 9:3 */ |
| 100 | +#define FLASH_CR_PNB_MASK 0x7f /* RM0444 - 3.7.5 - FLASH_CR - PNB bits 9:3 - 7 bits */ |
| 101 | + |
93 | 102 | #define FLASH_SECR_SEC_SIZE_POS (0U) |
94 | 103 | #define FLASH_SECR_SEC_SIZE_MASK (0xFF) |
95 | 104 |
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@@ -128,7 +137,7 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) |
128 | 137 | if ((len - i > 3) && ((((address + i) & 0x07) == 0) && |
129 | 138 | ((((uint32_t)data) + i) & 0x07) == 0)) { |
130 | 139 | src = (uint32_t *)data; |
131 | | - dst = (uint32_t *)(address + FLASHMEM_ADDRESS_SPACE); |
| 140 | + dst = (uint32_t *)address; |
132 | 141 | flash_wait_complete(); |
133 | 142 | dst[i >> 2] = src[i >> 2]; |
134 | 143 | dst[(i >> 2) + 1] = src[(i >> 2) + 1]; |
@@ -183,10 +192,19 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len) |
183 | 192 | uint32_t p; |
184 | 193 | if (len == 0) |
185 | 194 | return -1; |
| 195 | + address -= FLASHMEM_ADDRESS_SPACE; |
186 | 196 | end_address = address + len - 1; |
187 | 197 | for (p = address; p < end_address; p += FLASH_PAGE_SIZE) { |
| 198 | + while (FLASH_SR & (FLASH_SR_BSY1 | FLASH_SR_BSY2)); |
| 199 | + flash_clear_errors(); |
| 200 | + while (FLASH_SR & FLASH_SR_CFGBSY); |
| 201 | + uint32_t page_number = (p >> 11) & FLASH_CR_PNB_MASK; |
188 | 202 | uint32_t reg = FLASH_CR & (~(FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT)); |
189 | | - FLASH_CR = reg | ((p >> 11) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER; |
| 203 | + reg &= ~(FLASH_CR_BKER_BITMASK); |
| 204 | + if (p >= BANK_SIZE) { |
| 205 | + reg |= FLASH_CR_BKER; |
| 206 | + } |
| 207 | + FLASH_CR = reg | (page_number << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER; |
190 | 208 | DMB(); |
191 | 209 | FLASH_CR |= FLASH_CR_STRT; |
192 | 210 | flash_wait_complete(); |
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