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Add wolfBoot support for STM32G4
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.github/workflows/test-configs.yml

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arch: arm
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config-file: ./config/examples/stm32g0.config
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stm32g4_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/stm32g4.config
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stm32h5_test:
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uses: ./.github/workflows/test-build.yml
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with:

arch.mk

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ARCH_FLASH_OFFSET=0x08000000
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endif
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ifeq ($(TARGET),stm32g4)
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ARCH_FLASH_OFFSET=0x08000000
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endif
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ifeq ($(TARGET),stm32f1)
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CORTEX_M3=1
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NO_ARM_ASM=1

config/examples/stm32g4.config

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ARCH?=ARM
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TARGET?=stm32g4
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SIGN?=ECC256
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HASH?=SHA256
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DEBUG?=0
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VTOR?=1
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NO_ASM?=0
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=1
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WOLFBOOT_VERSION?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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# Single-bank 512KB flash, 2KB pages.
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# Layout: 32K boot, 232K app, 232K update, 16K swap.
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WOLFBOOT_SECTOR_SIZE?=0x800
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WOLFBOOT_PARTITION_SIZE?=0x3A000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08008000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08042000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0807C000

docs/Targets.md

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* [STM32F4](#stm32f4)
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* [STM32F7](#stm32f7)
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* [STM32G0](#stm32g0)
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* [STM32G4](#stm32g4)
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* [STM32H5](#stm32h5)
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* [STM32N6](#stm32n6)
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* [STM32H7](#stm32h7)
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mon reset init
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```
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## STM32G4
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Supports STM32G4 single-bank Category 3 parts (verified on NUCLEO-G491RE,
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STM32G491RET6: 512KB flash, 96KB SRAM, Cortex-M4F).
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The HAL boots at 170 MHz using HSI16 + PLL with PWR Range 1 Boost mode
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(RM0440 6.1.4), 4 flash wait states, prefetch + I/D-cache enabled.
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Example 512KB partitioning on STM32G491RE:
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- Sector size: 2KB
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- wolfBoot partition size: 32KB
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- Application partition size: 232KB
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```C
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#define WOLFBOOT_SECTOR_SIZE 0x800 /* 2 KB */
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#define WOLFBOOT_PARTITION_BOOT_ADDRESS 0x08008000
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#define WOLFBOOT_PARTITION_SIZE 0x3A000 /* 232 KB */
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#define WOLFBOOT_PARTITION_UPDATE_ADDRESS 0x08042000
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#define WOLFBOOT_PARTITION_SWAP_ADDRESS 0x0807C000 /* 16 KB swap */
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```
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### Building STM32G4
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Reference configuration (see [/config/examples/stm32g4.config](/config/examples/stm32g4.config)).
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You can copy this to wolfBoot root as `.config`: `cp ./config/examples/stm32g4.config .config`.
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To build you can use `make`.
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The TARGET for this is `stm32g4`: `make TARGET=stm32g4`.
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Cortex-M4F is the default ARM core for this target.
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The option `NVM_FLASH_WRITEONCE=1` is mandatory: the IAP driver writes one
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64-bit doubleword per location and cannot rewrite without an erase first.
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The default signing scheme is ECC256 with SHA256.
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NUCLEO-G491RE has no HSE, so HSI16 is used as the PLL source. The ST-LINK
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virtual COM port is wired to LPUART1 on PA2 (TX) / PA3 (RX) via AF12.
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Optional boot logs over LPUART1 at 115200 8N1 are enabled with
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`CFLAGS_EXTRA+=-DDEBUG_UART`.
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This target is single-bank only -- keep `DUALBANK_SWAP=0`.
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### STM32G4 Programming
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Compile requirements: `make TARGET=stm32g4 NVM_FLASH_WRITEONCE=1`
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The output is a single `factory.bin` that includes `wolfboot.bin` and
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`test-app/image_v1_signed.bin` combined together. This should be programmed
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to the flash start address `0x08000000`.
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Flash using the STM32CubeProgrammer CLI:
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```
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STM32_Programmer_CLI -c port=swd -d factory.bin 0x08000000
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```
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### STM32G4 Debugging
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Use `make DEBUG=1` and program firmware again.
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Start GDB server on port 3333:
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```
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ST-LINK_gdbserver -d -e -r 1 -p 3333
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OR
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st-util -p 3333
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```
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```
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arm-none-eabi-gdb
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add-symbol-file test-app/image.elf 0x08008100
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mon reset init
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```
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## STM32C0
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Supports STM32C0x0/STM32C0x1. Instructions are for the STM Nucleo-C031C6 dev board.

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