Added SPI TPM support for STM32H5. Added non-secure callable TPM API's. Cleanup some of the STM32H5 register mappings.

Author: dgarske

arch.mk

@@ -250,7 +250,6 @@ ifeq ($(ARCH),ARM)
     WOLFBOOT_ORIGIN=0x10000000
     ifeq ($(TZEN),1)
       LSCRIPT_IN=hal/$(TARGET).ld
-      CFLAGS+=-DTZEN
     else
       LSCRIPT_IN=hal/$(TARGET)-ns.ld
     endif
@@ -400,10 +399,6 @@ endif
 endif
 endif
 
-ifeq ($(TZEN),1)
-  CFLAGS+=-DTZEN
-endif
-
 
 ## Renesas RX
 ifeq ($(ARCH),RENESAS_RX)

config/examples/stm32h5-tz-tpm.config

@@ -0,0 +1,32 @@
+ARCH?=ARM
+TZEN?=1
+TARGET?=stm32h5
+SIGN?=ECC256
+HASH?=SHA256
+DEBUG?=0
+VTOR?=1
+CORTEX_M0?=0
+CORTEX_M33?=1
+NO_ASM?=0
+NO_MPU=1
+EXT_FLASH?=0
+SPI_FLASH?=0
+ALLOW_DOWNGRADE?=0
+NVM_FLASH_WRITEONCE?=1
+WOLFBOOT_VERSION?=1
+V?=0
+SPMATH?=1
+RAM_CODE?=1
+DUALBANK_SWAP?=0
+WOLFBOOT_PARTITION_SIZE?=0xA0000
+WOLFBOOT_SECTOR_SIZE?=0x2000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0C100000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0C1A0000
+FLAGS_HOME=0
+DISABLE_BACKUP=0
+WOLFCRYPT_TZ=1
+WOLFCRYPT_TZ_PKCS11=1
+IMAGE_HEADER_SIZE?=1024
+ARMORED=1
+WOLFTPM=1

hal/spi/spi_drv_stm32.c

@@ -369,24 +369,23 @@ int qspi_transfer(uint8_t fmode, const uint8_t cmd,
 #if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
 uint8_t RAMFUNCTION spi_read(void)
 {
-    volatile uint32_t reg;
-    do {
-        reg = SPI1_SR;
-    } while(!(reg & SPI_SR_RX_NOTEMPTY));
-    return (uint8_t)SPI1_DR;
+    while ((SPI1_SR & SPI_SR_RX_NOTEMPTY) == 0);
+#ifdef SPI1_RXDR
+    return SPI1_RXDR;
+#else
+    return SPI1_DR
+#endif
 }
 
 void RAMFUNCTION spi_write(const char byte)
 {
     int i;
-    volatile uint32_t reg;
-    do {
-        reg = SPI1_SR;
-    } while ((reg & SPI_SR_TX_EMPTY) == 0);
+    while ((SPI1_SR & SPI_SR_TX_EMPTY) == 0);
+#ifdef SPI1_TXDR
+    SPI1_TXDR = byte;
+#else
     SPI1_DR = byte;
-    do {
-        reg = SPI1_SR;
-    } while ((reg & SPI_SR_TX_EMPTY) == 0);
+#endif
 }
 #endif /* SPI_FLASH || WOLFBOOT_TPM */
 
@@ -398,7 +397,6 @@ void RAMFUNCTION spi_init(int polarity, int phase)
 
 /* Setup clocks */
 #if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH)
-
     #ifdef TARGET_stm32u5
         /* Clock configuration for QSPI defaults to SYSCLK
          * (RM0456 section 11.8.47)
@@ -413,6 +411,10 @@ void RAMFUNCTION spi_init(int polarity, int phase)
 
 #if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
         APB2_CLOCK_ER |= SPI1_APB2_CLOCK_ER_VAL;
+        #ifdef TARGET_stm32h5
+        RCC_CCIPR3 &= ~ (RCC_CCIPR3_SPI1SEL_MASK << RCC_CCIPR3_SPI1SEL_SHIFT);
+        RCC_CCIPR3 |= (0 << RCC_CCIPR3_SPI1SEL_SHIFT); /* PLL1_Q */
+        #endif
 #endif
 
         /* reset peripheral before setting up GPIO pins */
@@ -486,14 +488,30 @@ void RAMFUNCTION spi_init(int polarity, int phase)
 #endif
 #if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
         /* Configure SPI1 for master mode */
-#   ifdef TARGET_stm32l0
-        SPI1_CR1 = SPI_CR1_MASTER | (polarity << 1) | (phase << 0);
-#   else
-        /* baud rate 5 (hclk/6) */
-        SPI1_CR1 = SPI_CR1_MASTER | (5 << 3) | (polarity << 1) | (phase << 0);
-#   endif
+        SPI1_CR1 &= ~SPI_CR1_SPI_EN;
+    #if defined(TARGET_stm32h5)
+        /* baud rate 2 (hclk/8), data size 8 bits, FIFO threshold level (8-data) */
+        SPI1_CFG1 = (
+            ((7 & SPI_CFG1_FTHLV_MASK) << SPI_CFG1_FTHLV_SHIFT) |
+            ((2 & SPI_CFG1_BAUDRATE_MASK) << SPI_CFG1_BAUDRATE_SHIFT) |
+            ((7 & SPI_CFG1_DSIZE_MASK) << SPI_CFG1_DSIZE_SHIFT));
+        SPI1_CFG2 = SPI_CRF2_MASTER | SPI_CFG2_SSOE |
+            (polarity << SPI_CFG2_CLOCK_POL_SHIFT) |
+            (phase << SPI_CFG2_CLOCK_PHASE_SHIFT);
+        SPI1_CR1 |= SPI_CR1_CSTART; /* use continuous start mode */
+    #else
+        #ifndef TARGET_stm32l0 /* use existing/default baud for L0 */
+        /* Baud rate 5 (hclk/6), data size 8 bits */
+        SPI1_CR1 |= ((5 & SPI_CR1_BAUDRATE_MASK) << SPI_CR1_BAUDRATE_SHIFT);
+        #endif
+        SPI1_CR1 &= ~((1 << SPI_CR1_CLOCK_POL_SHIFT) | (1 << SPI_CR1_CLOCK_PHASE_SHIFT));
+        SPI1_CR1 |= SPI_CR1_MASTER |
+            (polarity << SPI_CR1_CLOCK_POL_SHIFT) |
+            (phase << SPI_CR1_CLOCK_PHASE_SHIFT);
         SPI1_CR2 |= SPI_CR2_SSOE;
-        SPI1_CR1 |= SPI_CR1_SPI_EN;
+    #endif
+
+        SPI1_CR1 |= SPI_CR1_SPI_EN; /* Enable SPI */
 #endif /* SPI_FLASH || WOLFBOOOT_TPM */
     }
 }
@@ -505,8 +523,12 @@ void RAMFUNCTION spi_release(void)
     }
     if (initialized == 0) {
         spi_reset();
-    #if defined (SPI_FLASH) || defined(WOLFBOOT_TPM)
+    #if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
+        #if defined(TARGET_stm32h5)
+        SPI1_CFG2 &= ~SPI_CFG2_SSOE;
+        #else
         SPI1_CR2 &= ~SPI_CR2_SSOE;
+        #endif
         SPI1_CR1 = 0;
     #endif
         stm_pins_release();

hal/spi/spi_drv_stm32.h

@@ -40,6 +40,28 @@
 #define SPI_MOSI_PIN  5 /* SPI_MOSI PB5  */
 #endif /* TARGET_stm32f4 */
 
+
+#ifdef TARGET_stm32h5
+#include "hal/stm32h5.h"
+
+#define RCC_GPIO_CLOCK_ER  RCC_AHB2ENR_CLOCK_ER
+#define APB2_CLOCK_RST     RCC_APB2_CLOCK_RSTR
+#define APB2_CLOCK_ER      RCC_APB2_CLOCK_ER
+
+/* Nucleo STM32H573ZI SPI_A Port (SPI1) */
+#define SPI_CLOCK_PIO_BASE  GPIOA_BASE
+#define SPI_MISO_PIO_BASE   GPIOG_BASE
+#define SPI_MOSI_PIO_BASE   GPIOB_BASE
+#define SPI_CS_TPM_PIO_BASE GPIOD_BASE
+
+#define SPI_PIN_AF    5 /* Alternate function for SPI pins */
+#define SPI_CLOCK_PIN 5 /* SPI_SCK: PA5  */
+#define SPI_MISO_PIN  9 /* SPI_MISO PG9  */
+#define SPI_MOSI_PIN  5 /* SPI_MOSI PB5  */
+#define SPI_CS_TPM    14 /* TPM   CS connected to PD14 */
+#endif /* TARGET_stm32h5 */
+
+
 #ifdef TARGET_stm32u5
 
 #ifdef TZEN
@@ -405,15 +427,53 @@
 
 #define SPI1_APB2_CLOCK_ER_VAL     (1 << 12)
 
+#if defined(TARGET_stm32h5)
+/* newer SPI/I2S peripheral */
+#define SPI1_CR1      (*(volatile uint32_t *)(SPI1_BASE))
+#define SPI1_CR2      (*(volatile uint32_t *)(SPI1_BASE + 0x04))
+#define SPI1_CFG1     (*(volatile uint32_t *)(SPI1_BASE + 0x08))
+#define SPI1_CFG2     (*(volatile uint32_t *)(SPI1_BASE + 0x0C))
+#define SPI1_SR       (*(volatile uint32_t *)(SPI1_BASE + 0x14))
+#define SPI1_TXDR     (*(volatile uint8_t *)(SPI1_BASE + 0x20))
+#define SPI1_RXDR     (*(volatile uint8_t *)(SPI1_BASE + 0x30))
+
+#define SPI_CR1_SPI_EN              (1 << 6)
+#define SPI_CR1_CSTART              (1 << 9) /* Continous start */
+#define SPI_CFG1_DSIZE_MASK         (0x1F)
+#define SPI_CFG1_DSIZE_SHIFT        (0)
+
+#define SPI_CFG1_FTHLV_MASK         (0x1F)
+#define SPI_CFG1_FTHLV_SHIFT        (5)
+
+#define SPI_CFG1_BAUDRATE_MASK      (0x07)
+#define SPI_CFG1_BAUDRATE_SHIFT     (28)
+
+#define SPI_CRF2_MASTER             (1 << 22)
+#define SPI_CFG2_LSBFIRST           (1 << 23)
+#define SPI_CFG2_CLOCK_PHASE_SHIFT  (24)
+#define SPI_CFG2_CLOCK_POL_SHIFT    (25)
+#define SPI_CFG2_SSM                (1 << 26)
+#define SPI_CFG2_SSOE               (1 << 29)
+#define SPI_CFG2_HW_CRC_EN          (1 << 29)
+#define SPI_CFG2_COMM_MASK          (0x3) /* 0=full duplex, 1=simplex tx, 2=simplex rx, 3=half duplex */
+#define SPI_CFG2_COMM_SHIFT         (17)
+
+#define SPI_SR_RX_NOTEMPTY          (1 << 0)
+#define SPI_SR_TX_EMPTY             (1 << 1)
+
+#else
+
+/* older SPI peripheral */
 #define SPI1_CR1      (*(volatile uint32_t *)(SPI1_BASE))
 #define SPI1_CR2      (*(volatile uint32_t *)(SPI1_BASE + 0x04))
 #define SPI1_SR       (*(volatile uint32_t *)(SPI1_BASE + 0x08))
-#define SPI1_DR       (*(volatile uint32_t *)(SPI1_BASE + 0x0c))
+#define SPI1_DR       (*(volatile uint8_t *)(SPI1_BASE + 0x0c))
 
-#define SPI_CR1_CLOCK_PHASE         (1 << 0)
-#define SPI_CR1_CLOCK_POLARITY      (1 << 1)
+#define SPI_CR1_CLOCK_PHASE_SHIFT   (0)
+#define SPI_CR1_CLOCK_POL_SHIFT     (1)
 #define SPI_CR1_MASTER              (1 << 2)
-#define SPI_CR1_BAUDRATE            (0x07 << 3)
+#define SPI_CR1_BAUDRATE_MASK       (0x07)
+#define SPI_CR1_BAUDRATE_SHIFT      (3)
 #define SPI_CR1_SPI_EN              (1 << 6)
 #define SPI_CR1_LSBFIRST            (1 << 7)
 #define SPI_CR1_SSI                 (1 << 8)
@@ -428,6 +488,7 @@
 #define SPI_SR_TX_EMPTY             (1 << 1)
 #define SPI_SR_BUSY                 (1 << 7)
 
+#endif
 
 /* GPIO */
 #define GPIO_MODE(base)    (*(volatile uint32_t *)(base + 0x00)) /* GPIOx_MODER */

hal/stm32h5.c

@@ -279,7 +279,6 @@ static void clock_pll_on(void)
     uint32_t reg32;
     uint32_t plln, pllm, pllq, pllp, pllr, hpre, apb1pre, apb2pre, apb3pre, flash_waitstates;
 
-
 #if PLL_SRC_HSE
     pllm = 4;
     plln = 250;
@@ -348,16 +347,16 @@ static void clock_pll_on(void)
 #endif
     DMB();
 
-    RCC_PLL1DIVR = ((plln - 1) << RCC_PLLDIVR_DIVN_SHIFT) | ((pllp - 1) << RCC_PLLDIVR_DIVP_SHIFT) |
-        ((pllq - 1) << RCC_PLLDIVR_DIVQ_SHIFT) | ((pllr - 1) << RCC_PLLDIVR_DIVR_SHIFT);
+    RCC_PLL1DIVR = ((plln - 1) << RCC_PLLDIVR_DIVN_SHIFT) |
+                   ((pllp - 1) << RCC_PLLDIVR_DIVP_SHIFT) |
+                   ((pllq - 1) << RCC_PLLDIVR_DIVQ_SHIFT) |
+                   ((pllr - 1) << RCC_PLLDIVR_DIVR_SHIFT);
     DMB();
 
-
     /* Disable Fractional PLL */
     RCC_PLL1CFGR &= ~RCC_PLLCFGR_PLLFRACEN;
     DMB();
 
-
     /* Configure Fractional PLL factor */
     RCC_PLL1FRACR = 0x00000000;
     DMB();
@@ -373,8 +372,8 @@ static void clock_pll_on(void)
     RCC_PLL1CFGR &= ~RCC_PLLCFGR_PLLVCOSEL;
     DMB();
 
-    /* Enable PLL1 system clock out (DIV: P) */
-    RCC_PLL1CFGR |= RCC_PLLCFGR_PLL1PEN;
+    /* Enable PLL1 system clock out (DIV: P and Q) */
+    RCC_PLL1CFGR |= RCC_PLLCFGR_PLL1PEN | RCC_PLLCFGR_PLL1QEN;
 
     /* Enable PLL1 */
     RCC_CR |= RCC_CR_PLL1ON;
@@ -386,11 +385,13 @@ static void clock_pll_on(void)
     apb3pre = RCC_APB_PRESCALER_DIV_NONE;
     reg32 = RCC_CFGR2;
     reg32 &= ~( (0x0F << RCC_CFGR2_HPRE_SHIFT) |
-            (0x07 << RCC_CFGR2_PPRE1_SHIFT) |
-            (0x07 << RCC_CFGR2_PPRE2_SHIFT) |
-            (0x07 << RCC_CFGR2_PPRE3_SHIFT));
-    reg32 |= ((hpre) << RCC_CFGR2_HPRE_SHIFT) | ((apb1pre) << RCC_CFGR2_PPRE1_SHIFT) |
-        ((apb2pre) << RCC_CFGR2_PPRE2_SHIFT) | ((apb3pre) << RCC_CFGR2_PPRE3_SHIFT);
+                (0x07 << RCC_CFGR2_PPRE1_SHIFT) |
+                (0x07 << RCC_CFGR2_PPRE2_SHIFT) |
+                (0x07 << RCC_CFGR2_PPRE3_SHIFT));
+    reg32 |= (   (hpre) << RCC_CFGR2_HPRE_SHIFT) |
+             ((apb1pre) << RCC_CFGR2_PPRE1_SHIFT) |
+             ((apb2pre) << RCC_CFGR2_PPRE2_SHIFT) |
+             ((apb3pre) << RCC_CFGR2_PPRE3_SHIFT);
     RCC_CFGR2 = reg32;
     DMB();
 
@@ -595,8 +596,6 @@ void hal_init(void)
 #if defined(DUALBANK_SWAP) && defined(__WOLFBOOT)
     fork_bootloader();
 #endif
-
-
 }