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dgarskedgarske
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Support for building wolfBoot for the network core (make CORE=2).
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-113
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‎docs/Targets.md‎

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2127,11 +2127,18 @@ Example of flash memory layout and configuration on the nRF52:
21272127
21282128
## Nordic nRF5340
21292129
2130-
Tested with the Nordic nRF5340-DK.
2130+
Tested with the Nordic nRF5340-DK. This device has two cores:
2131+
1) Application core: Cortex-M33 at 128MHz, w/TrustZone, 1MB flash, 512KB RAM
2132+
2) Network core: Cortex-M33 at 64MHz, 256KB Flash and 64KB RAM
2133+
2134+
The cores communicate using the IPC peripheral.
2135+
2136+
### Building Nordic nRF5340
21312137
21322138
Setup the configuration to build: `cp config/examples/nrf5340.config .config`
21332139
2134-
Build using `make clean && make`
2140+
Build application core loading using: `make clean && make`
2141+
Build network core loader using: `make CORE=2`
21352142
21362143
Flashing with JLink:
21372144
@@ -2142,6 +2149,10 @@ loadbin factory.bin 0x0
21422149
rnh
21432150
```
21442151

2152+
Note: For network core use: `-device nRF5340_xxAA_NET`
2153+
2154+
### Debugging Nordic nRF5340
2155+
21452156
Debugging with JLink:
21462157

21472158
1) Start GDB Server:

‎hal/nrf5340.h‎

Lines changed: 162 additions & 111 deletions
Original file line numberDiff line numberDiff line change
@@ -22,11 +22,25 @@
2222
#ifndef _HAL_NRF5340_H_
2323
#define _HAL_NRF5340_H_
2424

25-
#ifndef TZEN
26-
#define TZEN
25+
/* Build-time gate for secure or non-secure peripherals.
26+
* At boot-time peripherals are secure */
27+
#if defined(CORE) && CORE == 2
28+
#define TARGET_nrf5340_NET /* core 2 */
29+
30+
#undef QSPI_FLASH /* not supported on network core */
31+
#else
32+
#define TARGET_nrf5340_APP /* core 1 */
33+
#ifndef TZEN
34+
#define TZEN
35+
#endif
2736
#endif
2837

38+
#ifdef TARGET_nrf5340_APP
2939
#define CPU_CLOCK 128000000UL /* 128MHz */
40+
#else
41+
#define CPU_CLOCK 64000000UL /* 64MHz */
42+
#endif
43+
3044

3145
/* Assembly helpers */
3246
#define DMB() __asm__ volatile ("dmb")
@@ -38,10 +52,14 @@ void sleep_us(unsigned int us);
3852
#define PSEL_PORT(n) (((n) & 0x1) << 5)
3953

4054
/* Non-volatile memory controller */
41-
#ifdef TZEN
42-
#define NVMC_BASE (0x50039000)
55+
#ifdef TARGET_nrf5340_APP
56+
#ifdef TZEN
57+
#define NVMC_BASE (0x50039000)
58+
#else
59+
#define NVMC_BASE (0x40039000)
60+
#endif
4361
#else
44-
#define NVMC_BASE (0x40039000)
62+
#define NVMC_BASE (0x41080000)
4563
#endif
4664
#define NVMC_READY *((volatile uint32_t *)(NVMC_BASE + 0x400))
4765
#define NVMC_READYNEXT *((volatile uint32_t *)(NVMC_BASE + 0x408))
@@ -60,48 +78,52 @@ void sleep_us(unsigned int us);
6078
#define FLASH_PAGE_SIZE (4096)
6179

6280
/* Clock control */
63-
#ifdef TZEN
64-
#define CLOCK_BASE_APP (0x50005000)
81+
#ifdef TARGET_nrf5340_APP
82+
#ifdef TZEN
83+
#define CLOCK_BASE (0x50005000)
84+
#else
85+
#define CLOCK_BASE (0x40005000)
86+
#endif
6587
#else
66-
#define CLOCK_BASE_APP (0x40005000)
88+
#define CLOCK_BASE (0x41005000) /* network core */
6789
#endif
68-
#define CLOCK_BASE_NET (0x41005000) /* network core */
69-
#define CLOCK_HFCLKSTART *((volatile uint32_t *)(CLOCK_BASE_APP + 0x000))
70-
#define CLOCK_HFCLKSTOP *((volatile uint32_t *)(CLOCK_BASE_APP + 0x004))
71-
#define CLOCK_HFCLKSTARTED *((volatile uint32_t *)(CLOCK_BASE_APP + 0x100))
72-
#define CLOCK_HFCLKSTAT *((volatile uint32_t *)(CLOCK_BASE_APP + 0x40C))
73-
#define CLOCK_HFCLKSRC *((volatile uint32_t *)(CLOCK_BASE_APP + 0x514))
90+
#define CLOCK_HFCLKSTART *((volatile uint32_t *)(CLOCK_BASE + 0x000))
91+
#define CLOCK_HFCLKSTOP *((volatile uint32_t *)(CLOCK_BASE + 0x004))
92+
#define CLOCK_HFCLKSTARTED *((volatile uint32_t *)(CLOCK_BASE + 0x100))
93+
#define CLOCK_HFCLKSTAT *((volatile uint32_t *)(CLOCK_BASE + 0x40C))
94+
#define CLOCK_HFCLKSRC *((volatile uint32_t *)(CLOCK_BASE + 0x514))
7495
#define CLOCK_HFCLKSRC_HFXO 1
75-
#define CLOCK_HFCLKCTRL *((volatile uint32_t *)(CLOCK_BASE_APP + 0x558))
96+
#define CLOCK_HFCLKCTRL *((volatile uint32_t *)(CLOCK_BASE + 0x558))
7697
#define CLOCK_HFCLKCTRL_DIV1 0
7798
#define CLOCK_HFCLKCTRL_DIV2 1
7899

79-
/* Used by QSPI */
80-
#define CLOCK_HFCLK192MSTART *((volatile uint32_t *)(CLOCK_BASE_APP + 0x020))
81-
#define CLOCK_HFCLK192MSTOP *((volatile uint32_t *)(CLOCK_BASE_APP + 0x024))
82-
#define CLOCK_HFCLK192MSTARTED *((volatile uint32_t *)(CLOCK_BASE_APP + 0x124))
83-
#define CLOCK_HFCLK192MSRC *((volatile uint32_t *)(CLOCK_BASE_APP + 0x580))
100+
#define CLOCK_HFCLK192MSTART *((volatile uint32_t *)(CLOCK_BASE + 0x020))
101+
#define CLOCK_HFCLK192MSTOP *((volatile uint32_t *)(CLOCK_BASE + 0x024))
102+
#define CLOCK_HFCLK192MSTARTED *((volatile uint32_t *)(CLOCK_BASE + 0x124))
103+
#define CLOCK_HFCLK192MSRC *((volatile uint32_t *)(CLOCK_BASE + 0x580))
84104
#define CLOCK_HFCLK192MSRC_HFXO 1
85-
#define CLOCK_HFCLK192MCTRL *((volatile uint32_t *)(CLOCK_BASE_APP + 0x5B8))
105+
#define CLOCK_HFCLK192MCTRL *((volatile uint32_t *)(CLOCK_BASE + 0x5B8))
86106
#define CLOCK_HFCLK192MCTRL_DIV1 0
87107
#define CLOCK_HFCLK192MCTRL_DIV2 1
88108
#define CLOCK_HFCLK192MCTRL_DIV4 2
89109

90110

91-
92111
/* GPIO Port (0-1) */
93-
#ifdef TZEN
94-
#define GPIO_BASE_APP(n) (0x50842500 + (((n) & 0x1) * 0x300))
112+
#ifdef TARGET_nrf5340_APP
113+
#ifdef TZEN
114+
#define GPIO_BASE(n) (0x50842500 + (((n) & 0x1) * 0x300))
115+
#else
116+
#define GPIO_BASE(n) (0x40842500 + (((n) & 0x1) * 0x300))
117+
#endif
95118
#else
96-
#define GPIO_BASE_APP(n) (0x40842500 + (((n) & 0x1) * 0x300))
119+
#define GPIO_BASE(n) (0x418C0500 + (((n) & 0x1) * 0x300))
97120
#endif
98-
#define GPIO_BASE_NET(n) (0x418C0500 + (((n) & 0x1) * 0x300))
99-
#define GPIO_OUT(n) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x004))
100-
#define GPIO_OUTSET(n) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x008))
101-
#define GPIO_OUTCLR(n) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x00C))
102-
#define GPIO_IN(n) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x010))
103-
#define GPIO_DIRSET(n) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x018))
104-
#define GPIO_PIN_CNF(n,p) *((volatile uint32_t *)(GPIO_BASE_APP(n) + 0x200 + ((p) * 0x4)))
121+
#define GPIO_OUT(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x004))
122+
#define GPIO_OUTSET(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x008))
123+
#define GPIO_OUTCLR(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x00C))
124+
#define GPIO_IN(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x010))
125+
#define GPIO_DIRSET(n) *((volatile uint32_t *)(GPIO_BASE(n) + 0x018))
126+
#define GPIO_PIN_CNF(n,p) *((volatile uint32_t *)(GPIO_BASE(n) + 0x200 + ((p) * 0x4)))
105127

106128
#define GPIO_CNF_IN 0
107129
#define GPIO_CNF_IN_DIS 2
@@ -115,10 +137,15 @@ void sleep_us(unsigned int us);
115137
#define GPIO_CNF_MCUSEL(n) (((n) & 0x7) << 28)
116138

117139
/* UART (0-1) */
118-
#ifdef TZEN
119-
#define UART_BASE(n) (0x50008000 + (((n) & 0x1) * 0x1000))
140+
#ifdef TARGET_nrf5340_APP
141+
#ifdef TZEN
142+
#define UART_BASE(n) (0x50008000 + (((n) & 0x1) * 0x1000))
143+
#else
144+
#define UART_BASE(n) (0x40008000 + (((n) & 0x1) * 0x1000))
145+
#endif
120146
#else
121-
#define UART_BASE(n) (0x40008000 + (((n) & 0x1) * 0x1000))
147+
#define UART_BASE(n) (0x41013000) /* only UARTE0 */
148+
122149
#endif
123150
#define UART_TASK_STARTTX(n) *((volatile uint32_t *)(UART_BASE(n) + 0x008))
124151
#define UART_TASK_STOPTX(n) *((volatile uint32_t *)(UART_BASE(n) + 0x00C))
@@ -136,10 +163,14 @@ void sleep_us(unsigned int us);
136163
void uart_write_sz(const char* c, unsigned int sz);
137164

138165
/* SPI (0-2) */
139-
#ifdef TZEN
140-
#define SPI_BASE(n) (0x50008000 + (((n) & 0x3) * 0x1000))
166+
#ifdef TARGET_nrf5340_APP
167+
#ifdef TZEN
168+
#define SPI_BASE(n) (0x50008000 + (((n) & 0x3) * 0x1000))
169+
#else
170+
#define SPI_BASE(n) (0x40008000 + (((n) & 0x3) * 0x1000))
171+
#endif
141172
#else
142-
#define SPI_BASE(n) (0x40008000 + (((n) & 0x3) * 0x1000))
173+
#define SPI_BASE(n) (0x41013000) /* SPIM0 only */
143174
#endif
144175
#define SPI_TASKS_START(n) *((volatile uint32_t *)(SPI_BASE(n) + 0x010))
145176
#define SPI_TASKS_STOP(n) *((volatile uint32_t *)(SPI_BASE(n) + 0x014))
@@ -169,80 +200,100 @@ void uart_write_sz(const char* c, unsigned int sz);
169200
#define SPI_FREQ_M32 0x14000000
170201

171202
/* QSPI */
172-
#ifdef TZEN
173-
#define QSPI_BASE (0x5002B000)
203+
#ifdef TARGET_nrf5340_APP
204+
#ifdef TZEN
205+
#define QSPI_BASE (0x5002B000)
206+
#else
207+
#define QSPI_BASE (0x4002B000)
208+
#endif
209+
#define QSPI_TASKS_ACTIVATE *((volatile uint32_t *)(QSPI_BASE + 0x000))
210+
#define QSPI_TASKS_READSTART *((volatile uint32_t *)(QSPI_BASE + 0x004))
211+
#define QSPI_TASKS_WRITESTART *((volatile uint32_t *)(QSPI_BASE + 0x008))
212+
#define QSPI_TASKS_ERASESTART *((volatile uint32_t *)(QSPI_BASE + 0x00C))
213+
#define QSPI_TASKS_DEACTIVATE *((volatile uint32_t *)(QSPI_BASE + 0x010))
214+
#define QSPI_EVENTS_READY *((volatile uint32_t *)(QSPI_BASE + 0x100))
215+
216+
#define QSPI_INTEN *((volatile uint32_t *)(QSPI_BASE + 0x300))
217+
#define QSPI_INTENSET *((volatile uint32_t *)(QSPI_BASE + 0x304))
218+
#define QSPI_INTENCLR *((volatile uint32_t *)(QSPI_BASE + 0x308))
219+
220+
#define QSPI_ENABLE *((volatile uint32_t *)(QSPI_BASE + 0x500))
221+
222+
#define QSPI_READ_SRC *((volatile uint32_t *)(QSPI_BASE + 0x504))
223+
#define QSPI_READ_DST *((volatile uint32_t *)(QSPI_BASE + 0x508))
224+
#define QSPI_READ_CNT *((volatile uint32_t *)(QSPI_BASE + 0x50C))
225+
#define QSPI_WRITE_DST *((volatile uint32_t *)(QSPI_BASE + 0x510))
226+
#define QSPI_WRITE_SRC *((volatile uint32_t *)(QSPI_BASE + 0x514))
227+
#define QSPI_WRITE_CNT *((volatile uint32_t *)(QSPI_BASE + 0x518))
228+
#define QSPI_ERASE_PTR *((volatile uint32_t *)(QSPI_BASE + 0x51C))
229+
#define QSPI_ERASE_LEN *((volatile uint32_t *)(QSPI_BASE + 0x520))
230+
231+
#define QSPI_PSEL_SCK *((volatile uint32_t *)(QSPI_BASE + 0x524))
232+
#define QSPI_PSEL_CSN *((volatile uint32_t *)(QSPI_BASE + 0x528))
233+
#define QSPI_PSEL_IO0 *((volatile uint32_t *)(QSPI_BASE + 0x530))
234+
#define QSPI_PSEL_IO1 *((volatile uint32_t *)(QSPI_BASE + 0x534))
235+
#define QSPI_PSEL_IO2 *((volatile uint32_t *)(QSPI_BASE + 0x538))
236+
#define QSPI_PSEL_IO3 *((volatile uint32_t *)(QSPI_BASE + 0x53C))
237+
238+
#define QSPI_IFCONFIG0 *((volatile uint32_t *)(QSPI_BASE + 0x544))
239+
#define QSPI_IFCONFIG1 *((volatile uint32_t *)(QSPI_BASE + 0x600))
240+
241+
#define QSPI_STATUS *((volatile uint32_t *)(QSPI_BASE + 0x604))
242+
#define QSPI_ADDRCONF *((volatile uint32_t *)(QSPI_BASE + 0x624))
243+
#define QSPI_CINSTRCONF *((volatile uint32_t *)(QSPI_BASE + 0x634))
244+
#define QSPI_CINSTRDAT0 *((volatile uint32_t *)(QSPI_BASE + 0x638))
245+
#define QSPI_CINSTRDAT1 *((volatile uint32_t *)(QSPI_BASE + 0x63C))
246+
#define QSPI_IFTIMING *((volatile uint32_t *)(QSPI_BASE + 0x640))
247+
248+
#define QSPI_IFCONFIG0_READOC_MASK 0x7
249+
#define QSPI_IFCONFIG0_READOC_FASTREAD (0) /* opcode 0x0B */
250+
#define QSPI_IFCONFIG0_READOC_READ2O (1) /* opcode 0x3B */
251+
#define QSPI_IFCONFIG0_READOC_READ2IO (2) /* opcode 0xBB */
252+
#define QSPI_IFCONFIG0_READOC_READ4O (3) /* opcode 0x6B */
253+
#define QSPI_IFCONFIG0_READOC_READ4IO (4) /* opcode 0xEB */
254+
#define QSPI_IFCONFIG0_WRITEOC_MASK ((0x7) << 3)
255+
#define QSPI_IFCONFIG0_WRITEOC_PP ((0) << 3) /* opcode 0x02 */
256+
#define QSPI_IFCONFIG0_WRITEOC_PP2O ((1) << 3) /* opcode 0xA2 */
257+
#define QSPI_IFCONFIG0_WRITEOC_PP4O ((2) << 3) /* opcode 0x32 */
258+
#define QSPI_IFCONFIG0_WRITEOC_PP4IO ((3) << 3) /* opcode 0x38 */
259+
#define QSPI_IFCONFIG0_ADDRMODE_24BIT ((0) << 6)
260+
#define QSPI_IFCONFIG0_ADDRMODE_32BIT ((1) << 6)
261+
#define QSPI_IFCONFIG0_DPMENABLE ((1) << 7)
262+
#define QSPI_IFCONFIG0_PPSIZE_256 ((0) << 12)
263+
#define QSPI_IFCONFIG0_PPSIZE_512 ((1) << 12)
264+
265+
#define QSPI_IFCONFIG1_SCKDELAY_MASK 0xFF
266+
#define QSPI_IFCONFIG1_SCKDELAY(n) ((n) & QSPI_IFCONFIG1_SCKDELAY_MASK)
267+
#define QSPI_IFCONFIG1_SPIMODE0 0
268+
#define QSPI_IFCONFIG1_SPIMODE3 (1UL << 25)
269+
#define QSPI_IFCONFIG1_SCKFREQ_MASK ((0xF) << 28)
270+
#define QSPI_IFCONFIG1_SCKFREQ(n) (((n) & 0xF) << 28)
271+
272+
#define QSPI_CINSTRCONF_OPCODE(n) ((n) & 0xFF)
273+
#define QSPI_CINSTRCONF_LENGTH(n) (((n) & 0xF) << 8)
274+
#define QSPI_CINSTRCONF_LIO2 (1 << 12)
275+
#define QSPI_CINSTRCONF_LIO3 (1 << 13)
276+
#define QSPI_CINSTRCONF_WREN (1 << 15) /* send WREN opcode 0x6 before */
277+
278+
#define QSPI_IFTIMING_RXDELAY(n) (((n) & 0x7) << 8)
279+
#endif
280+
281+
/* interprocessor communication (IPC) peripheral */
282+
#ifdef TARGET_nrf5340_APP
283+
#ifdef TZEN
284+
#define IPC_BASE (0x5002A000)
285+
#else
286+
#define IPC_BASE (0x4002A000)
287+
#endif
174288
#else
175-
#define QSPI_BASE (0x4002B000)
289+
#define IPC_BASE (0x4002A000) /* network core */
176290
#endif
177-
#define QSPI_TASKS_ACTIVATE *((volatile uint32_t *)(QSPI_BASE + 0x000))
178-
#define QSPI_TASKS_READSTART *((volatile uint32_t *)(QSPI_BASE + 0x004))
179-
#define QSPI_TASKS_WRITESTART *((volatile uint32_t *)(QSPI_BASE + 0x008))
180-
#define QSPI_TASKS_ERASESTART *((volatile uint32_t *)(QSPI_BASE + 0x00C))
181-
#define QSPI_TASKS_DEACTIVATE *((volatile uint32_t *)(QSPI_BASE + 0x010))
182-
#define QSPI_EVENTS_READY *((volatile uint32_t *)(QSPI_BASE + 0x100))
183-
184-
#define QSPI_INTEN *((volatile uint32_t *)(QSPI_BASE + 0x300))
185-
#define QSPI_INTENSET *((volatile uint32_t *)(QSPI_BASE + 0x304))
186-
#define QSPI_INTENCLR *((volatile uint32_t *)(QSPI_BASE + 0x308))
187-
188-
#define QSPI_ENABLE *((volatile uint32_t *)(QSPI_BASE + 0x500))
189-
190-
#define QSPI_READ_SRC *((volatile uint32_t *)(QSPI_BASE + 0x504))
191-
#define QSPI_READ_DST *((volatile uint32_t *)(QSPI_BASE + 0x508))
192-
#define QSPI_READ_CNT *((volatile uint32_t *)(QSPI_BASE + 0x50C))
193-
#define QSPI_WRITE_DST *((volatile uint32_t *)(QSPI_BASE + 0x510))
194-
#define QSPI_WRITE_SRC *((volatile uint32_t *)(QSPI_BASE + 0x514))
195-
#define QSPI_WRITE_CNT *((volatile uint32_t *)(QSPI_BASE + 0x518))
196-
#define QSPI_ERASE_PTR *((volatile uint32_t *)(QSPI_BASE + 0x51C))
197-
#define QSPI_ERASE_LEN *((volatile uint32_t *)(QSPI_BASE + 0x520))
198-
199-
#define QSPI_PSEL_SCK *((volatile uint32_t *)(QSPI_BASE + 0x524))
200-
#define QSPI_PSEL_CSN *((volatile uint32_t *)(QSPI_BASE + 0x528))
201-
#define QSPI_PSEL_IO0 *((volatile uint32_t *)(QSPI_BASE + 0x530))
202-
#define QSPI_PSEL_IO1 *((volatile uint32_t *)(QSPI_BASE + 0x534))
203-
#define QSPI_PSEL_IO2 *((volatile uint32_t *)(QSPI_BASE + 0x538))
204-
#define QSPI_PSEL_IO3 *((volatile uint32_t *)(QSPI_BASE + 0x53C))
205-
206-
#define QSPI_IFCONFIG0 *((volatile uint32_t *)(QSPI_BASE + 0x544))
207-
#define QSPI_IFCONFIG1 *((volatile uint32_t *)(QSPI_BASE + 0x600))
208-
209-
#define QSPI_STATUS *((volatile uint32_t *)(QSPI_BASE + 0x604))
210-
#define QSPI_ADDRCONF *((volatile uint32_t *)(QSPI_BASE + 0x624))
211-
#define QSPI_CINSTRCONF *((volatile uint32_t *)(QSPI_BASE + 0x634))
212-
#define QSPI_CINSTRDAT0 *((volatile uint32_t *)(QSPI_BASE + 0x638))
213-
#define QSPI_CINSTRDAT1 *((volatile uint32_t *)(QSPI_BASE + 0x63C))
214-
#define QSPI_IFTIMING *((volatile uint32_t *)(QSPI_BASE + 0x640))
215-
216-
#define QSPI_IFCONFIG0_READOC_MASK 0x7
217-
#define QSPI_IFCONFIG0_READOC_FASTREAD (0) /* opcode 0x0B */
218-
#define QSPI_IFCONFIG0_READOC_READ2O (1) /* opcode 0x3B */
219-
#define QSPI_IFCONFIG0_READOC_READ2IO (2) /* opcode 0xBB */
220-
#define QSPI_IFCONFIG0_READOC_READ4O (3) /* opcode 0x6B */
221-
#define QSPI_IFCONFIG0_READOC_READ4IO (4) /* opcode 0xEB */
222-
#define QSPI_IFCONFIG0_WRITEOC_MASK ((0x7) << 3)
223-
#define QSPI_IFCONFIG0_WRITEOC_PP ((0) << 3) /* opcode 0x02 */
224-
#define QSPI_IFCONFIG0_WRITEOC_PP2O ((1) << 3) /* opcode 0xA2 */
225-
#define QSPI_IFCONFIG0_WRITEOC_PP4O ((2) << 3) /* opcode 0x32 */
226-
#define QSPI_IFCONFIG0_WRITEOC_PP4IO ((3) << 3) /* opcode 0x38 */
227-
#define QSPI_IFCONFIG0_ADDRMODE_24BIT ((0) << 6)
228-
#define QSPI_IFCONFIG0_ADDRMODE_32BIT ((1) << 6)
229-
#define QSPI_IFCONFIG0_DPMENABLE ((1) << 7)
230-
#define QSPI_IFCONFIG0_PPSIZE_256 ((0) << 12)
231-
#define QSPI_IFCONFIG0_PPSIZE_512 ((1) << 12)
232-
233-
#define QSPI_IFCONFIG1_SCKDELAY_MASK 0xFF
234-
#define QSPI_IFCONFIG1_SCKDELAY(n) ((n) & QSPI_IFCONFIG1_SCKDELAY_MASK)
235-
#define QSPI_IFCONFIG1_SPIMODE0 0
236-
#define QSPI_IFCONFIG1_SPIMODE3 (1UL << 25)
237-
#define QSPI_IFCONFIG1_SCKFREQ_MASK ((0xF) << 28)
238-
#define QSPI_IFCONFIG1_SCKFREQ(n) (((n) & 0xF) << 28)
239-
240-
#define QSPI_CINSTRCONF_OPCODE(n) ((n) & 0xFF)
241-
#define QSPI_CINSTRCONF_LENGTH(n) (((n) & 0xF) << 8)
242-
#define QSPI_CINSTRCONF_LIO2 (1 << 12)
243-
#define QSPI_CINSTRCONF_LIO3 (1 << 13)
244-
#define QSPI_CINSTRCONF_WREN (1 << 15) /* send WREN opcode 0x6 before */
245-
246-
#define QSPI_IFTIMING_RXDELAY(n) (((n) & 0x7) << 8)
291+
#define IPC_TASKS_SEND(n) *((volatile uint32_t *)(IPC_BASE + 0x000 + (((n) & 0xF) * 0x4)))
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#define IPC_SUBSCRIBE_SEND(n) *((volatile uint32_t *)(IPC_BASE + 0x080 + (((n) & 0xF) * 0x4)))
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#define IPC_EVENTS_RECEIVE(n) *((volatile uint32_t *)(IPC_BASE + 0x100 + (((n) & 0xF) * 0x4)))
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#define IPC_PUBLISH_RECEIVE(n) *((volatile uint32_t *)(IPC_BASE + 0x180 + (((n) & 0xF) * 0x4)))
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#define IPC_SEND_CNF(n) *((volatile uint32_t *)(IPC_BASE + 0x510 + (((n) & 0xF) * 0x4)))
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#define IPC_RECEIVE_CNF(n) *((volatile uint32_t *)(IPC_BASE + 0x590 + (((n) & 0xF) * 0x4)))
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#define IPC_GPMEM(n) *((volatile uint32_t *)(IPC_BASE + 0x610 + (((n) & 0x1) * 0x4)))
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#endif /* !_HAL_NRF5340_H_ */

‎options.mk‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -852,3 +852,7 @@ ifneq ($(KEYVAULT_MAX_ITEMS),)
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CFLAGS+=-DKEYVAULT_MAX_ITEMS=$(KEYVAULT_MAX_ITEMS)
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endif
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ifneq ($(CORE),)
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CFLAGS+=-DCORE=$(CORE)
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endif

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