SAMA5D3: Hal fixes, add DBGU, enable ARM_ASM

Author: danielinux

config/examples/sama5d3.config

@@ -5,17 +5,16 @@ HASH?=SHA256
 DEBUG?=0
 VTOR?=1
 CORTEX_M0?=0
-NO_ASM?=0
 EXT_FLASH?=1
 NAND_FLASH?=1
 SPI_FLASH?=0
 V?=0
 SPMATH?=1
-WOLFBOOT_PARTITION_SIZE?=0x1000000
+WOLFBOOT_PARTITION_SIZE?=0x8000000
 WOLFBOOT_NO_PARTITIONS=0
 WOLFBOOT_SECTOR_SIZE?=0x1000
-WOLFBOOT_LOAD_ADDRESS=0x20100800
-WOLFBOOT_LOAD_DTS_ADDRESS=0x21100800
+WOLFBOOT_LOAD_ADDRESS=0x20100000
+WOLFBOOT_LOAD_DTS_ADDRESS=0x21100000
 WOLFBOOT_PARTITION_BOOT_ADDRESS=0x400000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS=0x800000
 WOLFBOOT_PARTITION_SWAP_ADDRESS=0x0

hal/sama5d3.c

@@ -666,7 +666,7 @@ int ext_flash_read(uintptr_t address, uint8_t *data, int len)
     return len;
 }
 
-void pit_init(void)
+static void pit_init(void)
 {
     uint32_t pmc_pcr;
 
@@ -697,6 +697,29 @@ void sleep_us(uint32_t usec)
     } while (current < delay);
 }
 
+/* Set up DBGU.
+ * Assume baud rate is correcly set by RomBoot
+ */
+static void dbgu_init(void) {
+    /* Set up pins */
+    PMC_CLOCK_EN(GPIOB_PMCID);
+
+    /* Disable Pull */
+    GPIO_PPUDR(DBGU_GPIO) = (1 << DBGU_PIN_TX) | (1 << DBGU_PIN_RX);
+    GPIO_PPDDR(DBGU_GPIO) = (1 << DBGU_PIN_TX) | (1 << DBGU_PIN_RX);
+
+    /* Set "Peripheral A" */
+    GPIO_ASR(DBGU_GPIO) = (1 << DBGU_PIN_TX) | (1 << DBGU_PIN_RX);
+
+    /* Enable the peripheral clock for the DBGU */
+    PMC_CLOCK_EN(DBGU_PMCID);
+
+    /* Enable the transmitter and receiver */
+    DBGU_CR = DBGU_CR_TXEN | DBGU_CR_RXEN;
+}
+
+
+
 int ext_flash_write(uintptr_t address, const uint8_t *data, int len)
 {
     /* TODO */
@@ -742,6 +765,7 @@ void hal_init(void)
     pit_init();
     watchdog_disable();
     ddr_init();
+    dbgu_init();
     nand_read_info();
 }
 

hal/sama5d3.h

@@ -93,8 +93,6 @@
 #define PMC_PCR_DIV_SHIFT     13
 #define PMC_PCR_DIV_MASK      (0x3 << PMC_PCR_DIV_SHIFT)
 
-
-
 /* Specific configuration for 264/132/12 MHz */
 
 #define PLL_PCK		         (((CRYSTAL_FREQ * (PLLA_MULA + 1)) / 2))
@@ -110,23 +108,33 @@
 
 #define PLLICPR_CONFIG      (0x0 << PMC_PLLICPR_ICPPLLA_SHIFT | 0x3 << PMC_PLLICPR_IPLLA_SHIFT)
 
+/* DBGU
+ *
+ */
+#define DBGU_BASE 0xFFFFEE00
+#define DBGU_CR   *(volatile uint32_t *)(DBGU_BASE + 0x00)
+#define DBGU_BRGR *(volatile uint32_t *)(DBGU_BASE + 0x20)
+#define DBGU_CR_RXEN (1 << 4)
+#define DBGU_CR_TXEN (1 << 6)
+#define DBGU_PMCID 0x02 /* dec: 2 for SAMA5D3 */
+
+/* Associated pins : GPIOB 30 - 31*/
+#define DBGU_PIN_RX 30
+#define DBGU_PIN_TX 31
+#define DBGU_GPIO   GPIOB
 
 /* PIT
  *
  */
-
 #define PIT_BASE 0xFFFFFE30
 #define PIT_MR   *(volatile uint32_t *)(PIT_BASE + 0x00)
 #define PIT_SR   *(volatile uint32_t *)(PIT_BASE + 0x04)
 #define PIT_PIVR *(volatile uint32_t *)(PIT_BASE + 0x08)
 #define PIT_PIIR *(volatile uint32_t *)(PIT_BASE + 0x0C)
 
-
-
-
 /* DRAM setup
+ *
  */
-
 #define MPDDRC_BASE 0xFFFFEA00
 #define MPDDRC_MR *(volatile uint32_t *)(MPDDRC_BASE + 0x00) /* Mode Register */
 #define MPDDRC_RTR *(volatile uint32_t *)(MPDDRC_BASE + 0x04) /* Refresh Timer Register */
@@ -159,7 +167,6 @@
 #define MPDDRC_WPMR *(volatile uint32_t *)(MPDDRC_BASE + 0xE4) /* Write Protection Mode Register */
 #define MPDDRC_WPSR *(volatile uint32_t *)(MPDDRC_BASE + 0xE8) /* Write Protection Status Register */
 
-
 /* MPDDRC_CR: shift, mask, values */
 #define MPDDRC_NC_SHIFT 0  /* Number of Column Bits */
 #define MPDDRC_NC_MASK (0x3 << MPDDRC_NC_SHIFT)
@@ -285,8 +292,6 @@
 #define GPIOD_PMCID 0x09
 #define GPIOE_PMCID 0x0A
 
-
-
 struct dram {
     struct dram_timing {
         uint32_t tras;
@@ -310,6 +315,7 @@ struct dram {
 };
 
 /* Watchdog
+ *
  */
 #define WDT_BASE 0xFFFFFD40
 #define WDT_CR   *(volatile uint32_t *)(WDT_BASE + 0x00)
@@ -435,7 +441,6 @@ extern void *kernel_addr, *update_addr, *dts_addr;
 #define MAX_ECC_BYTES 8
 #endif
 
-
 #define GPIOB   0xFFFFF400
 #define GPIOC   0xFFFFF600
 #define GPIOE   0xFFFFFA00
@@ -454,6 +459,7 @@ extern void *kernel_addr, *update_addr, *dts_addr;
 #define GPIO_MDDR(base)     *(volatile uint32_t *)(base + 0x54)
 #define GPIO_PPUDR(base)    *(volatile uint32_t *)(base + 0x60)
 #define GPIO_PPUER(base)    *(volatile uint32_t *)(base + 0x64)
+#define GPIO_ASR(base)      *(volatile uint32_t *)(base + 0x70)
 #define GPIO_PPDDR(base)    *(volatile uint32_t *)(base + 0x90)
 
 

lib/wolfssl

@@ -3,7 +3,7 @@ OUTPUT_ARCH(arm)
 
 MEMORY
 {
-    DDR_MEM(rwx): ORIGIN = 0x20100800, LENGTH = 0x100000
+    DDR_MEM(rwx): ORIGIN = 0x20100000, LENGTH = 0x100000
     STACK_MEM(rw): ORIGIN = 0x20000000, LENGTH = 0x00100000
 }