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dgarskedgarske
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Merge pull request #460 from danielinux/stm32u5_spi
[QSPI] Fixed registers and pin config on STM32U5
2 parents d11accc + 7b5012b commit f493526

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4 files changed

+96
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‎config/examples/stm32u5.config‎

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Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@ NO_ASM?=0
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NO_MPU=1
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EXT_FLASH?=0
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SPI_FLASH?=0
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QSPI_FLASH?=0
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OCTOSPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=1
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WOLFBOOT_VERSION?=1

‎docs/Targets.md‎

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@@ -358,9 +358,7 @@ ST-LINK_gdbserver -d -cp /opt/st/stm32cubeide_1.3.0/plugins/com.st.stm32cube.ide
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Max OS/X:
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```sh
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sudo ln -s /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.macos64_1.6.0.202101291314/tools/bin/native/mac_x64/libSTLinkUSBDriver.dylib /usr/local/lib/libSTLinkUSBDriver.dylib
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/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.macos64_1.6.0.202101291314/tools/bin/ST-LINK_gdbserver -d -cp ./Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.macos64_1.6.0.202101291314/tools/bin -e -r 1 -p 3333
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/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.macos64_2.1.300.202403291623/tools/bin/ST-LINK_gdbserver -d -cp /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.macos64_2.1.201.202404072231/tools/bin -e -r 1 -p 3333
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```
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Win:
@@ -375,6 +373,7 @@ wolfBoot has a .gdbinit to configure
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add-symbol-file test-app/image.elf
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```
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## STM32L0
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Example 192KB partitioning on STM32-L073

‎hal/spi/spi_drv_stm32.c‎

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -185,8 +185,13 @@ static void stm_pins_release(void)
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static void RAMFUNCTION spi_reset(void)
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{
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#if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH)
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AHB3_CLOCK_RST |= RCC_AHB3ENR_QSPIEN;
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AHB3_CLOCK_RST &= ~RCC_AHB3ENR_QSPIEN;
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#ifndef TARGET_stm32u5
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AHB3_CLOCK_RST |= RCC_AHB3ENR_QSPIEN;
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AHB3_CLOCK_RST &= ~RCC_AHB3ENR_QSPIEN;
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#else
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AHB2_CLOCK_RST |= RCC_AHB2ENR_QSPIEN;
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AHB2_CLOCK_RST &= ~RCC_AHB2ENR_QSPIEN;
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#endif
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#endif
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#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
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APB2_CLOCK_RST |= SPI1_APB2_CLOCK_ER_VAL;
@@ -390,13 +395,21 @@ void RAMFUNCTION spi_init(int polarity, int phase)
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if (!initialized) {
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initialized++;
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/* Setup clocks */
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/* Setup clocks */
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#if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH)
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#ifdef PLATFORM_stm32u5
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/* Clock configuration for QSPI defaults to SYSCLK
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* (RM0456 section 11.8.47)
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*/
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#else
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/* Select QUADSPI clock source */
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RCC_D1CCIPR &= ~RCC_D1CCIPR_QSPISEL_MASK;
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RCC_D1CCIPR |= RCC_D1CCIPR_QSPISEL(QSPI_CLOCK_SEL);
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AHB3_CLOCK_EN |= RCC_AHB3ENR_QSPIEN;
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#endif
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#endif
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400413
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
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APB2_CLOCK_ER |= SPI1_APB2_CLOCK_ER_VAL;
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#endif

‎hal/spi/spi_drv_stm32.h‎

Lines changed: 76 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -40,25 +40,37 @@
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#define SPI_MOSI_PIN 5 /* SPI_MOSI PB5 */
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#endif /* PLATFORM_stm32f4 */
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43-
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#ifdef PLATFORM_stm32u5
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#ifdef TZEN
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#define PERIPH_BASE (0x50000000UL)
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#else
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#define PERIPH_BASE (0x40000000UL)
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#endif
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51-
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL)
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#define OCTOSPI1_BASE (PERIPH_BASE + 0x020D1400UL)
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#define OCTOSPI2_BASE (PERIPH_BASE + 0x020D2400UL)
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54-
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
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#ifndef OCTOSPI_BASE
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#define OCTOSPI_BASE OCTOSPI2_BASE
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#endif
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56-
#define RCC_BASE (APB2PERIPH_BASE + 0x0C00UL)
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/* Registers mapping */
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x00012C00UL)
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#define RCC_BASE (PERIPH_BASE + 0x06020C00UL)
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#define GPIO_BASE (PERIPH_BASE + 0x02020000UL)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL)
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#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0xA4))
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#define APB2_CLOCK_RST (*(volatile uint32_t *)(RCC_BASE + 0x7C))
66+
#define AHB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x90))
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#define AHB2_CLOCK_RST (*(volatile uint32_t *)(RCC_BASE + 0x68))
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#define RCC_GPIO_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C))
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61-
#define GPIO_BASE (APB2PERIPH_BASE + 0x02020000UL)
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72+
#define RCC_AHB2ENR_QSPIEN (1 << 8) /* OCTOSPI2 = bit 8, OCTOSPI1 = bit 4 */
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#define GPIOA_BASE (GPIO_BASE + 0x00000UL)
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#define GPIOB_BASE (GPIO_BASE + 0x00400UL)
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#define GPIOC_BASE (GPIO_BASE + 0x00800UL)
@@ -69,6 +81,64 @@
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#define GPIOH_BASE (GPIO_BASE + 0x01C00UL)
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#define GPIOI_BASE (GPIO_BASE + 0x02000UL)
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84+
/** QSPI **/
85+
/* Default Base (H) and AF (alternate function=5) for QSPI */
86+
#define QSPI_GPIO GPIOH_BASE
87+
#define QSPI_PIN_AF 5
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89+
#ifndef QSPI_CLOCK_BASE
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#define QSPI_CLOCK_BASE 160000000
91+
#endif
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93+
#ifndef QSPI_CLOCK_MHZ
94+
#define QSPI_CLOCK_MHZ 10000000
95+
#endif
96+
97+
/* Default to flash bank 1 */
98+
#ifndef QSPI_FLASH_BANK
99+
#define QSPI_FLASH_BANK 1
100+
#endif
101+
102+
/* Default flash size to 16MB */
103+
#ifndef QSPI_FLASH_SIZE
104+
#define QSPI_FLASH_SIZE 23 /* 2^24 = 16 MB */
105+
#endif
106+
107+
/* QSPI CLK PB2 (alt OCTOSPIM_P1_CLK)*/
108+
#define QSPI_CLOCK_PIO_BASE GPIOH_BASE
109+
#define QSPI_CLOCK_PIN 6
110+
#define QSPI_CLOCK_PIN_AF 5
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112+
/* nQSPI_CS PG6 (alt PB6 -> OCTOSPIM_P1_NCS) */
113+
#ifndef QSPI_ALT_CONFIGURATION
114+
#define QSPI_CS_PIO_BASE GPIOH_BASE
115+
#define QSPI_CS_FLASH_PIN 5
116+
#else
117+
#define QSPI_CS_PIO_BASE GPIOH_BASE
118+
#define QSPI_CS_FLASH_PIN 6
119+
#endif
120+
121+
/* QSPI_IO0 */
122+
#define QSPI_IO0_PIO_BASE GPIOH_BASE
123+
#define QSPI_IO0_PIN 9
124+
#define QSPI_IO0_PIN_AF 5
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126+
/* QSPI_IO1 */
127+
#define QSPI_IO1_PIO_BASE GPIOH_BASE
128+
#define QSPI_IO1_PIN 10
129+
#define QSPI_IO1_PIN_AF 5
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131+
/* QSPI_IO2 */
132+
#define QSPI_IO2_PIO_BASE GPIOH_BASE
133+
#define QSPI_IO2_PIN 11
134+
#define QSPI_IO2_PIN_AF 5
135+
136+
/* QSPI_IO3 */
137+
#define QSPI_IO3_PIO_BASE GPIOH_BASE
138+
#define QSPI_IO3_PIN 12
139+
#define QSPI_IO3_PIN_AF 5
140+
141+
72142
/* STMOD+ Port */
73143
#define SPI_GPIO GPIOE_BASE
74144
#define SPI_CS_GPIO GPIOE_BASE

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