diff --git a/.gitignore b/.gitignore index 0f214e3..4cbbc17 100644 --- a/.gitignore +++ b/.gitignore @@ -23,6 +23,7 @@ transcript # Quartus temporary files .qsys_edit/ +subsystemHMI/ db/ HPSPlatform/ incremental_db/ diff --git a/hdl/HPSPlatform.qsys b/hdl/HPSPlatform.qsys index 0643f77..3237d7e 100644 --- a/hdl/HPSPlatform.qsys +++ b/hdl/HPSPlatform.qsys @@ -177,6 +177,19 @@ type = "int"; } } + element hmi.infrared_s0 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "2048"; + type = "String"; + } + } element hmi.leds_s1 { datum _lockedAddress @@ -184,6 +197,11 @@ value = "1"; type = "boolean"; } + datum _tags + { + value = ""; + type = "String"; + } datum baseAddress { value = "1040"; @@ -279,6 +297,22 @@ + + + + - + @@ -378,6 +412,9 @@ + + + @@ -398,9 +435,9 @@ - + - + @@ -932,7 +969,16 @@ + + + + + @@ -941,7 +987,7 @@ @@ -950,7 +996,7 @@ @@ -959,7 +1005,7 @@ @@ -968,7 +1014,7 @@ @@ -977,7 +1023,7 @@ @@ -986,76 +1032,93 @@ - + + - + + + + + diff --git a/hdl/components/infrared/comp.do b/hdl/components/infrared/comp.do new file mode 100644 index 0000000..41abef2 --- /dev/null +++ b/hdl/components/infrared/comp.do @@ -0,0 +1,21 @@ + +#----------------------------------*-tcl-*- + +#------------------------------------------- +proc myvcom {filename} { + if {[file exists ${filename}] == 1} { + puts "## vcom $filename" + vcom -93 -novopt -quiet ${filename} -work work + } else { + puts "## WARNING: File not found: ${filename}" + } +} + +#------------------------------------------- +vlib work +myvcom counter.vhd +myvcom sync.vhd +myvcom sync_single.vhd +myvcom infrared.vhd + +quit diff --git a/hdl/components/infrared/counter.vhd b/hdl/components/infrared/counter.vhd new file mode 100644 index 0000000..c2d6677 --- /dev/null +++ b/hdl/components/infrared/counter.vhd @@ -0,0 +1,104 @@ +------------------------------------------------------------------------------- +--! @file counter.vhd +--! @author Michael Wurm +--! @copyright 2020 Michael Wurm +--! @brief Entity implementation of counter. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +--! @brief Entity declaration of counter +--! @details +--! Provides a counter value of clock ticks of clk_i. +--! The counter is free-running, and thus overflows at its maximum. + +entity counter is + generic ( + counter_width_g : natural := 31); + port ( + --! @name Clocks and resets + --! @{ + + --! System clock + clk_i : in std_logic; + --! Asynchronous reset + rst_n_i : in std_logic; + + --! @} + --! @name Control and status signals + --! @{ + + --! Enable + enable_i : in std_ulogic; + --! Overflow + overflow_o : out std_ulogic; + --! Generated strobe + count_o : out unsigned(counter_width_g-1 downto 0)); + + --! @} + +end entity counter; + +--! RTL implementation of counter +architecture rtl of counter is + ----------------------------------------------------------------------------- + --! @name Internal Registers + ----------------------------------------------------------------------------- + --! @{ + + signal count : unsigned(count_o'range); + signal overflow : std_ulogic := '0'; + + --! @} + ----------------------------------------------------------------------------- + --! @name Internal Wires + ----------------------------------------------------------------------------- + --! @{ + + + --! @} + +begin -- architecture rtl + + ------------------------------------------------------------------------------ + -- Outputs + ------------------------------------------------------------------------------ + + count_o <= count; + overflow_o <= overflow; + + ----------------------------------------------------------------------------- + -- Signal Assignments + ----------------------------------------------------------------------------- + + ------------------------------------------------------------------------------ + -- Registers + ------------------------------------------------------------------------------ + + regs : process (clk_i, rst_n_i) is + procedure reset is + begin + count <= to_unsigned(0, count'length); + overflow <= '0'; + end procedure reset; + begin -- process regs + if rst_n_i = '0' then + reset; + elsif rising_edge(clk_i) then + -- Defaults + overflow <= '0'; + + if enable_i = '0' then + reset; + else + count <= count + 1; + if count = 2**count'length-1 then + overflow <= '1'; + end if; + end if; + end if; + end process regs; + +end architecture rtl; diff --git a/hdl/components/infrared/infrared.vhd b/hdl/components/infrared/infrared.vhd new file mode 100644 index 0000000..59f566c --- /dev/null +++ b/hdl/components/infrared/infrared.vhd @@ -0,0 +1,236 @@ +------------------------------------------------------------------------------- +--! @file infrared.vhd +--! @author Michael Wurm +--! @copyright 2020 Michael Wurm +--! @brief Entity implementation of infrared. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +--! @brief Entity declaration of infrared +--! @details +--! Stores timestamps on every change of the IR LED input. +--! In that way, a sequence can be recorded and reproduced afterwards. + +entity infrared is + port ( + --! @name Clocks and resets + --! @{ + + --! System clock + clk_i : in std_logic; + --! Asynchronous reset + rst_n_i : in std_logic; + + --! @} + --! @name Avalon MM Bus + --! @{ + avs_s0_address : in std_logic_vector(10 downto 0); + avs_s0_read : in std_logic; + avs_s0_readdata : out std_logic_vector(31 downto 0); + avs_s0_write : in std_logic; + avs_s0_writedata : in std_logic_vector(31 downto 0); + avs_s0_waitrequest : out std_logic; + + --! @} + --! @name Infrared transceiver signals + --! @{ + + --! IR Receive + ir_rx_i : in std_logic; + --! IR Transmit + ir_tx_o : out std_logic; + + --! @} + --! @name Status signals + --! @{ + + --! Done recording interrupt + done_recording_irq_o : out std_logic; + --! IR Receive Mirror + ir_rx_o : out std_logic); + + --! @} + +end entity infrared; + +--! RTL implementation of infrared +architecture rtl of infrared is + ----------------------------------------------------------------------------- + --! @name Types and Constants + ----------------------------------------------------------------------------- + --! @{ + + --! @} + ----------------------------------------------------------------------------- + --! @name Internal Registers + ----------------------------------------------------------------------------- + --! @{ + + subtype timestamp_t is unsigned(31 downto 0); + type ram_t is array(0 to 255) of timestamp_t; + + signal ram_data : ram_t := (others => (others => '0')); + signal ram_readdata : timestamp_t := (others => '0'); + signal ctrl_readdata : timestamp_t := (others => '0'); + + signal addr : unsigned(7 downto 0) := (others => '0'); + signal ir_rx : std_ulogic_vector(1 downto 0) := (others => '0'); + signal store_timestamp : std_ulogic := '0'; + signal irq_active : std_ulogic := '0'; + signal irq_reset : std_ulogic := '0'; + + --! @} + ----------------------------------------------------------------------------- + --! @name Internal Wires + ----------------------------------------------------------------------------- + --! @{ + + signal ir_rx_sync : std_ulogic; + signal next_ir_rx : std_ulogic_vector(1 downto 0); + signal rising : std_ulogic; + signal falling : std_ulogic; + signal recording_stopped : std_ulogic; + signal timestamp : timestamp_t; + signal ctrl_access : std_ulogic; + + --! @} + +begin -- architecture rtl + + ------------------------------------------------------------------------------ + -- Outputs + ------------------------------------------------------------------------------ + + ir_rx_o <= ir_rx(ir_rx'high); -- mirror rx signal (for debug only) + ir_tx_o <= ir_rx(ir_rx'high); -- mirror rx signal (until tx is implemented) + avs_s0_readdata <= std_logic_vector(ram_readdata) when ctrl_access = '0' + else std_logic_vector(ctrl_readdata); + done_recording_irq_o <= recording_stopped; + + ----------------------------------------------------------------------------- + -- Signal Assignments + ----------------------------------------------------------------------------- + + next_ir_rx <= ir_rx(ir_rx'high-1 downto ir_rx'low) & ir_rx_sync; + rising <= '1' when ir_rx(1)='0' and ir_rx(0)='1' else '0'; + falling <= '1' when ir_rx(1)='1' and ir_rx(0)='0' else '0'; + ctrl_access <= '1' when to_integer(unsigned(avs_s0_address)) > ram_t'length-1 else '0'; + + ----------------------------------------------------------------------------- + -- Instantiations + ----------------------------------------------------------------------------- + + sync_inst : entity work.sync_single + generic map ( + init_value_g => '0', + num_delays_g => 2) + port map ( + clk_i => clk_i, + rst_n_i => rst_n_i, + async_i => ir_rx_i, + sync_o => ir_rx_sync); + + timestamp_counter_inst : entity work.counter + generic map ( + counter_width_g => 32) + port map ( + clk_i => clk_i, + rst_n_i => rst_n_i, + enable_i => '1', + overflow_o => open, + count_o => timestamp); + + stop_counter_inst : entity work.counter + generic map ( + counter_width_g => 25) -- 2^25 steps @ 100MHz => 0.3355 sec + port map ( + clk_i => clk_i, + rst_n_i => rst_n_i, + enable_i => falling, + overflow_o => recording_stopped, + count_o => open); + + ------------------------------------------------------------------------------ + -- Registers + ------------------------------------------------------------------------------ + + regs : process (clk_i, rst_n_i) is + procedure reset is + begin + addr <= to_unsigned(0, addr'length); + store_timestamp <= '0'; + irq_active <= '0'; + end procedure reset; + begin -- process strobe + if rst_n_i = '0' then + reset; + elsif rising_edge(clk_i) then + -- Defaults + ir_rx <= next_ir_rx; + store_timestamp <= '0'; + + if rising = '1' or falling = '1' then + addr <= addr + 1; + store_timestamp <= '1'; + elsif recording_stopped = '1' then + irq_active <= '1'; + addr <= (others => '0'); + end if; + if irq_reset = '1' then + irq_active <= '0'; + end if; + end if; + end process regs; + + ram : process (clk_i) is + begin + if rising_edge(clk_i) then + if store_timestamp = '1' then + ram_data(to_integer(addr)) <= timestamp; + end if; + + if avs_s0_read = '1' then + ram_readdata <= ram_data(to_integer(unsigned(avs_s0_address(addr'range)))); + end if; + end if; + end process ram; + + ctrl_interface : process (clk_i) is + procedure reset is + begin + ctrl_readdata <= (others => '0'); + irq_reset <= '0'; + end procedure reset; + begin -- process ctrl_interface + if rst_n_i = '0' then + reset; + elsif rising_edge(clk_i) then + if avs_s0_read = '1' then + -- Defaults + ctrl_readdata <= (others => '0'); + irq_reset <= '0'; + + -- addresses higher 255 + case (to_integer(unsigned(avs_s0_address(avs_s0_address'high downto addr'high+1)))) is + when 0 => -- magic number + ctrl_readdata <= x"ABCD1234"; + when 1 => -- magic number + ctrl_readdata <= x"11111111"; + when 2 => -- magic number + ctrl_readdata <= x"22222222"; + when 3 => -- magic number + ctrl_readdata <= x"33333333"; + when 4 => -- read and clear irq status + ctrl_readdata(0) <= irq_active; + irq_reset <= '1'; + when others => + ctrl_readdata <= x"DEADBEEF"; + end case; + end if; + end if; + end process ctrl_interface; + +end architecture rtl; diff --git a/hdl/components/infrared/infrared_hw.tcl b/hdl/components/infrared/infrared_hw.tcl new file mode 100644 index 0000000..085076d --- /dev/null +++ b/hdl/components/infrared/infrared_hw.tcl @@ -0,0 +1,194 @@ +# TCL File Generated by Component Editor 19.1 +# Wed Feb 19 11:57:18 CET 2020 +# DO NOT MODIFY + + +# +# infrared "infrared" v1.0 +# Michael Wurm 2020.02.19.11:57:18 +# Infrared Recorder/Transmitter +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module infrared +# +set_module_property DESCRIPTION "Infrared Recorder/Transmitter" +set_module_property NAME infrared +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "Michael Wurm" +set_module_property DISPLAY_NAME infrared +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL infrared +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file counter.vhd VHDL PATH counter.vhd +add_fileset_file sync_single.vhd VHDL PATH sync_single.vhd +add_fileset_file infrared.vhd VHDL PATH infrared.vhd TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# module assignments +# +set_module_assignment embeddedsw.dts.group sensor +set_module_assignment embeddedsw.dts.name infrared +set_module_assignment embeddedsw.dts.vendor wur + + +# +# display items +# + + +# +# connection point s0 +# +add_interface s0 avalon end +set_interface_property s0 addressUnits WORDS +set_interface_property s0 associatedClock clk_i +set_interface_property s0 associatedReset rst_n_i +set_interface_property s0 bitsPerSymbol 8 +set_interface_property s0 burstOnBurstBoundariesOnly false +set_interface_property s0 burstcountUnits WORDS +set_interface_property s0 explicitAddressSpan 0 +set_interface_property s0 holdTime 0 +set_interface_property s0 linewrapBursts false +set_interface_property s0 maximumPendingReadTransactions 0 +set_interface_property s0 maximumPendingWriteTransactions 0 +set_interface_property s0 readLatency 0 +set_interface_property s0 readWaitTime 1 +set_interface_property s0 setupTime 0 +set_interface_property s0 timingUnits Cycles +set_interface_property s0 writeWaitTime 0 +set_interface_property s0 ENABLED true +set_interface_property s0 EXPORT_OF "" +set_interface_property s0 PORT_NAME_MAP "" +set_interface_property s0 CMSIS_SVD_VARIABLES "" +set_interface_property s0 SVD_ADDRESS_GROUP "" + +add_interface_port s0 avs_s0_address address Input 8 +add_interface_port s0 avs_s0_read read Input 1 +add_interface_port s0 avs_s0_readdata readdata Output 32 +add_interface_port s0 avs_s0_write write Input 1 +add_interface_port s0 avs_s0_writedata writedata Input 32 +add_interface_port s0 avs_s0_waitrequest waitrequest Output 1 +set_interface_assignment s0 embeddedsw.configuration.isFlash 0 +set_interface_assignment s0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment s0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment s0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point clk_i +# +add_interface clk_i clock end +set_interface_property clk_i clockRate 0 +set_interface_property clk_i ENABLED true +set_interface_property clk_i EXPORT_OF "" +set_interface_property clk_i PORT_NAME_MAP "" +set_interface_property clk_i CMSIS_SVD_VARIABLES "" +set_interface_property clk_i SVD_ADDRESS_GROUP "" + +add_interface_port clk_i clk_i clk Input 1 + + +# +# connection point rst_n_i +# +add_interface rst_n_i reset end +set_interface_property rst_n_i associatedClock clk_i +set_interface_property rst_n_i synchronousEdges DEASSERT +set_interface_property rst_n_i ENABLED true +set_interface_property rst_n_i EXPORT_OF "" +set_interface_property rst_n_i PORT_NAME_MAP "" +set_interface_property rst_n_i CMSIS_SVD_VARIABLES "" +set_interface_property rst_n_i SVD_ADDRESS_GROUP "" + +add_interface_port rst_n_i rst_n_i reset_n Input 1 + + +# +# connection point done_recording_irq +# +add_interface done_recording_irq interrupt end +set_interface_property done_recording_irq associatedAddressablePoint "" +set_interface_property done_recording_irq associatedClock clk_i +set_interface_property done_recording_irq associatedReset rst_n_i +set_interface_property done_recording_irq bridgedReceiverOffset "" +set_interface_property done_recording_irq bridgesToReceiver "" +set_interface_property done_recording_irq ENABLED true +set_interface_property done_recording_irq EXPORT_OF "" +set_interface_property done_recording_irq PORT_NAME_MAP "" +set_interface_property done_recording_irq CMSIS_SVD_VARIABLES "" +set_interface_property done_recording_irq SVD_ADDRESS_GROUP "" + +add_interface_port done_recording_irq done_recording_irq_o irq Output 1 + + + +# +# connection point ir_rx_i +# +add_interface ir_rx_i conduit end +set_interface_property ir_rx_i associatedClock clk_i +set_interface_property ir_rx_i associatedReset "" +set_interface_property ir_rx_i ENABLED true +set_interface_property ir_rx_i EXPORT_OF "" +set_interface_property ir_rx_i PORT_NAME_MAP "" +set_interface_property ir_rx_i CMSIS_SVD_VARIABLES "" +set_interface_property ir_rx_i SVD_ADDRESS_GROUP "" + +add_interface_port ir_rx_i ir_rx_i conduit Input 1 + + +# +# connection point ir_rx_o +# +add_interface ir_rx_o conduit end +set_interface_property ir_rx_o associatedClock clk_i +set_interface_property ir_rx_o associatedReset "" +set_interface_property ir_rx_o ENABLED true +set_interface_property ir_rx_o EXPORT_OF "" +set_interface_property ir_rx_o PORT_NAME_MAP "" +set_interface_property ir_rx_o CMSIS_SVD_VARIABLES "" +set_interface_property ir_rx_o SVD_ADDRESS_GROUP "" + +add_interface_port ir_rx_o ir_rx_o conduit Output 1 + + +# +# connection point ir_tx_o +# +add_interface ir_tx_o conduit end +set_interface_property ir_tx_o associatedClock clk_i +set_interface_property ir_tx_o associatedReset "" +set_interface_property ir_tx_o ENABLED true +set_interface_property ir_tx_o EXPORT_OF "" +set_interface_property ir_tx_o PORT_NAME_MAP "" +set_interface_property ir_tx_o CMSIS_SVD_VARIABLES "" +set_interface_property ir_tx_o SVD_ADDRESS_GROUP "" + +add_interface_port ir_tx_o ir_tx_o conduit Output 1 + diff --git a/hdl/components/infrared/modelsim_compile.sh b/hdl/components/infrared/modelsim_compile.sh new file mode 100755 index 0000000..9be7554 --- /dev/null +++ b/hdl/components/infrared/modelsim_compile.sh @@ -0,0 +1,3 @@ +#!/usr/bin/env bash + +vsim -do comp.do -c diff --git a/hdl/components/infrared/strobe_gen.vhd b/hdl/components/infrared/strobe_gen.vhd new file mode 100644 index 0000000..8c26822 --- /dev/null +++ b/hdl/components/infrared/strobe_gen.vhd @@ -0,0 +1,119 @@ +------------------------------------------------------------------------------- +--! @file strobe_gen.vhd +--! @author Michael Wurm +--! @copyright 2020 Michael Wurm +--! @brief Entity implementation of strobe_gen. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +--! @brief Entity declaration of strobe_gen +--! @details +--! Generates a strobe signal that will be '1' for one clock cycle +--! of clk_i. The strobe comes every period_g. If this cycle time +--! cannot be generated exactly it will be truncated with the +--! accuracy of one clk_i cycle. + +entity strobe_gen is + generic ( + --! System clock frequency + clk_freq_g : natural := clk_freq_c; + --! Period between two strobes + period_g : time := 100 us); + port ( + --! @name Clocks and resets + --! @{ + + --! System clock + clk_i : in std_logic; + --! Asynchronous reset + rst_n_i : in std_logic; + + --! @} + --! @name Strobe signals + --! @{ + + --! Enable + enable_i : in std_ulogic; + --! Generated strobe + strobe_o : out std_ulogic); + + --! @} + +begin + + -- pragma translate_off + assert ((1 sec / clk_freq_g) <= period_g) + report "strobe_gen: The Clk frequency is to low to generate such a short strobe cycle." + severity error; + -- pragma translate_on + +end entity strobe_gen; + +--! RTL implementation of strobe_gen +architecture rtl of strobe_gen is + ----------------------------------------------------------------------------- + --! @name Types and Constants + ----------------------------------------------------------------------------- + --! @{ + + constant clks_per_strobe_c : natural := clk_freq_g / (1 sec / period_g); + + --! @} + ----------------------------------------------------------------------------- + --! @name Internal Registers + ----------------------------------------------------------------------------- + --! @{ + + signal count : unsigned(log_dualis(clks_per_strobe_c) downto 0); + + --! @} + ----------------------------------------------------------------------------- + --! @name Internal Wires + ----------------------------------------------------------------------------- + --! @{ + + signal strobe : std_ulogic; + + --! @} + +begin -- architecture rtl + + ------------------------------------------------------------------------------ + -- Outputs + ------------------------------------------------------------------------------ + + strobe_o <= strobe; + + ------------------------------------------------------------------------------ + -- Registers + ------------------------------------------------------------------------------ + + -- Count the number of clk_i cycles from strobe pulse to strobe pulse. + regs : process (clk_i, rst_n_i) is + procedure reset is + begin + count <= to_unsigned(0, count'length); + strobe <= '0'; + end procedure reset; + begin -- process strobe + if rst_n_i = '0' then + reset; + elsif rising_edge(clk_i) then + if enable_i = '0' then + reset; + else + if count = clks_per_strobe_c-1 then + count <= (others => '0'); + strobe <= '1'; + else + count <= count + 1; + strobe <= '0'; + end if; + end if; + end if; + end process regs; + +end architecture rtl; diff --git a/hdl/components/infrared/sync.vhd b/hdl/components/infrared/sync.vhd new file mode 100644 index 0000000..2caec00 --- /dev/null +++ b/hdl/components/infrared/sync.vhd @@ -0,0 +1,101 @@ +------------------------------------------------------------------------------- +--! @file sync.vhd +--! @author Michael Wurm +--! @copyright 2020 Michael Wurm +--! @brief Implementation of sync. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +--! @brief Entity declaration of sync +--! @details +--! The sync implementation. + +entity sync is + generic ( + init_value_g : std_ulogic := '0'; + num_delays_g : natural := 2; + sig_width_g : natural := 1); + port ( + --! @name Clocks and resets + --! @{ + + --! System clock + clk_i : in std_logic; + --! Asynchronous reset + rst_n_i : in std_logic; + + --! @} + --! @name Sync signals + --! @{ + + --! Asynchronous input + async_i : in std_ulogic_vector(sig_width_g-1 downto 0); + --! Synchronous output + sync_o : out std_ulogic_vector(sig_width_g-1 downto 0)); + + --! @} + +end entity sync; + +--! RTL implementation of sync +architecture rtl of sync is + ----------------------------------------------------------------------------- + --! @name Types and Constants + ----------------------------------------------------------------------------- + --! @{ + + type delay_t is array(num_delays_g-1 downto 0) of + std_ulogic_vector(sig_width_g-1 downto 0); + + --! @} + ----------------------------------------------------------------------------- + --! @name Internal Registers + ----------------------------------------------------------------------------- + --! @{ + + signal delay : delay_t := (others => (others => init_value_g)); + + --! @} + ----------------------------------------------------------------------------- + --! @name Internal Wires + ----------------------------------------------------------------------------- + --! @{ + + signal next_delay : delay_t := (others => (others => init_value_g)); + + --! @} + +begin -- architecture rtl + + ------------------------------------------------------------------------------ + -- Outputs + ------------------------------------------------------------------------------ + + sync_o <= delay(delay'high); + + ----------------------------------------------------------------------------- + -- Signal Assignments + ----------------------------------------------------------------------------- + + next_delay <= delay(delay'high-1 downto delay'low) & async_i; + + ------------------------------------------------------------------------------ + -- Registers + ------------------------------------------------------------------------------ + + regs : process(clk_i, rst_n_i) + procedure reset is + begin + delay <= (others => (others => init_value_g)); + end procedure reset; + begin -- process regs + if rst_n_i = '0' then + reset; + elsif rising_edge(clk_i) then + delay <= next_delay; + end if; + end process regs; + +end architecture rtl; diff --git a/hdl/components/infrared/sync_single.vhd b/hdl/components/infrared/sync_single.vhd new file mode 100644 index 0000000..d43a07a --- /dev/null +++ b/hdl/components/infrared/sync_single.vhd @@ -0,0 +1,91 @@ +------------------------------------------------------------------------------- +--! @file sync_single.vhd +--! @author Michael Wurm +--! @copyright 2020 Michael Wurm +--! @brief Implementation of sync_single. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +--! @brief Entity declaration of sync_single +--! @details +--! The sync_single implementation. + +entity sync_single is + generic ( + init_value_g : std_ulogic := '0'; + num_delays_g : natural := 2); + port ( + --! @name Clocks and resets + --! @{ + + --! System clock + clk_i : in std_logic; + --! Asynchronous reset + rst_n_i : in std_logic; + + --! @} + --! @name Sync signals + --! @{ + + --! Asynchronous input + async_i : in std_ulogic; + --! Synchronous output + sync_o : out std_ulogic); + + --! @} + +end entity sync_single; + +--! RTL implementation of sync_single +architecture rtl of sync_single is + ----------------------------------------------------------------------------- + --! @name Internal Registers + ----------------------------------------------------------------------------- + --! @{ + + signal delay : std_ulogic_vector(num_delays_g-1 downto 0) := (others => '0'); + + --! @} + ----------------------------------------------------------------------------- + --! @name Internal Wires + ----------------------------------------------------------------------------- + --! @{ + + signal next_delay : std_ulogic_vector(delay'range); + + --! @} + +begin -- architecture rtl + + ------------------------------------------------------------------------------ + -- Outputs + ------------------------------------------------------------------------------ + + sync_o <= delay(delay'high); + + ----------------------------------------------------------------------------- + -- Signal Assignments + ----------------------------------------------------------------------------- + + next_delay <= delay(delay'high-1 downto delay'low) & async_i; + + ------------------------------------------------------------------------------ + -- Registers + ------------------------------------------------------------------------------ + + regs : process(clk_i, rst_n_i) + procedure reset is + begin + delay <= (others => init_value_g); + end procedure reset; + begin -- process regs + if rst_n_i = '0' then + reset; + elsif rising_edge(clk_i) then + delay <= next_delay; + end if; + end process regs; + +end architecture rtl; diff --git a/hdl/ip/subsystemHMI.qsys b/hdl/ip/subsystemHMI.qsys index 2f0333a..bcdf834 100644 --- a/hdl/ip/subsystemHMI.qsys +++ b/hdl/ip/subsystemHMI.qsys @@ -9,6 +9,14 @@ categories="System" /> + + + + + + + + - + + @@ -219,45 +260,45 @@ version="1.0" enabled="1"> - + - + - $${FILENAME}_subsystemApds9301 + subsystemHMI_subsystemApds9301 - + - + - $${FILENAME}_subsystemHdc1000 + subsystemHMI_subsystemHdc1000 - + - + - $${FILENAME}_subsystemMpu9250 + subsystemHMI_subsystemMpu9250 - + diff --git a/hdl/top.vhd b/hdl/top.vhd index e8b54f5..98848be 100644 --- a/hdl/top.vhd +++ b/hdl/top.vhd @@ -1,399 +1,412 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -ENTITY top IS - -PORT( - ---------FPGA Connections------------- - CLOCK_50 : in std_logic; - SW : in std_logic_vector(9 downto 0); - LEDR : out std_logic_vector(9 downto 0); - - - -- //////////// SEG7 ////////// - HEX0 : out std_logic_vector(6 downto 0); - HEX1 : out std_logic_vector(6 downto 0); - HEX2 : out std_logic_vector(6 downto 0); - HEX3 : out std_logic_vector(6 downto 0); - HEX4 : out std_logic_vector(6 downto 0); - HEX5 : out std_logic_vector(6 downto 0); - - - ---------HPS Connections--------------- - HPS_CONV_USB_N : inout std_logic; - HPS_DDR3_ADDR : out std_logic_vector(14 downto 0); - HPS_DDR3_BA : out std_logic_vector(2 downto 0); - HPS_DDR3_CAS_N : out std_logic; - HPS_DDR3_CKE : out std_logic; - HPS_DDR3_CK_N : out std_logic; - HPS_DDR3_CK_P : out std_logic; - HPS_DDR3_CS_N : out std_logic; - HPS_DDR3_DM : out std_logic_vector(3 downto 0); - HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); - HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0); - HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0); - HPS_DDR3_ODT : out std_logic; - HPS_DDR3_RAS_N : out std_logic; - HPS_DDR3_RESET_N : out std_logic; - HPS_DDR3_RZQ : in std_logic; - HPS_DDR3_WE_N : out std_logic; - - HPS_ENET_GTX_CLK : out std_logic; - HPS_ENET_INT_N : inout std_logic; - HPS_ENET_MDC : out std_logic; - HPS_ENET_MDIO : inout std_logic; - HPS_ENET_RX_CLK : in std_logic; - HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); - HPS_ENET_RX_DV : in std_logic; - HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); - HPS_ENET_TX_EN : out std_logic; - - HPS_KEY : inout std_logic; - HPS_LED : inout std_logic; - - HPS_SD_CLK : out std_logic; - HPS_SD_CMD : inout std_logic; - HPS_SD_DATA : inout std_logic_vector(3 downto 0); - - HPS_UART_RX : in std_logic; - HPS_UART_TX : out std_logic; - - HPS_USB_CLKOUT : in std_logic; - HPS_USB_DATA : inout std_logic_vector(7 downto 0); - HPS_USB_DIR : in std_logic; - HPS_USB_NXT : in std_logic; - HPS_USB_STP : out std_logic; - - HPS_I2C1_SCLK : inout std_logic; - HPS_I2C1_SDAT : inout std_logic; - HPS_I2C2_SCLK : inout std_logic; - HPS_I2C2_SDAT : inout std_logic; - HPS_I2C_CONTROL : inout std_logic; - - HPS_LTC_GPIO : inout std_logic; - HPS_GSENSOR_INT : inout std_logic; - - HPS_SPIM_CLK : out std_logic; - HPS_SPIM_MISO : in std_logic; - HPS_SPIM_MOSI : out std_logic; - HPS_SPIM_SS : inout std_logic; - - --////////// GPIO, GPIO connect to RFS - RF and Sensor ////////// - --BT_KEY : inout std_logic; - --BT_UART_RX : in std_logic; - --BT_UART_TX : out std_logic; - LSENSOR_INT : in std_logic; - LSENSOR_SCL : inout std_logic; - LSENSOR_SDA : inout std_logic; - MPU_AD0_SDO : in std_logic; - MPU_CS_n : inout std_logic; - MPU_FSYNC : out std_logic; - MPU_INT : in std_logic; - MPU_SCL_SCLK : inout std_logic; - MPU_SDA_SDI : inout std_logic; - RH_TEMP_DRDY_n : in std_ulogic; - RH_TEMP_I2C_SCL : inout std_logic; - RH_TEMP_I2C_SDA : inout std_logic; - TMD_D : out std_logic_vector(7 downto 0); - --UART2USB_CTS : in std_logic; - --UART2USB_RTS : out std_logic; - --UART2USB_RX : in std_logic; - --UART2USB_TX : out std_logic; - --WIFI_EN : out std_logic; - --WIFI_RST_n : out std_logic; - --WIFI_UART0_CTS : in std_logic; - --WIFI_UART0_RTS : out std_logic; - --WIFI_UART0_RX : in std_logic; - --WIFI_UART0_TX : out std_logic; - --WIFI_UART1_RX : in std_logic - GPIO_0 : out std_logic_vector(35 downto 0) -); - -END ENTITY; - -ARCHITECTURE MAIN OF top IS - component HPSPlatform is - port ( - clk_clk : in std_logic := 'X'; -- clk - hps_0_h2f_reset_reset_n : out std_logic; -- reset_n - hps_0_f2h_cold_reset_req_reset_n : in std_logic := 'X'; -- reset_n - hps_0_f2h_debug_reset_req_reset_n : in std_logic := 'X'; -- reset_n - hps_0_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents - hps_0_f2h_warm_reset_req_reset_n : in std_logic := 'X'; -- reset_n - hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK - hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0 - hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1 - hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2 - hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3 - hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0 - hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO - hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC - hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL - hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL - hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK - hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1 - hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2 - hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3 - hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD - hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0 - hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1 - hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK - hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2 - hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3 - hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0 - hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1 - hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2 - hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3 - hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4 - hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5 - hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6 - hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7 - hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK - hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP - hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR - hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT - hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK - hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI - hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO - hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0 - hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX - hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX - hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA - hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL - hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA - hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL - hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09 - hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35 - hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40 - hps_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48 - hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53 - hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54 - hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61 - memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a - memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba - memory_mem_ck : out std_logic; -- mem_ck - memory_mem_ck_n : out std_logic; -- mem_ck_n - memory_mem_cke : out std_logic; -- mem_cke - memory_mem_cs_n : out std_logic; -- mem_cs_n - memory_mem_ras_n : out std_logic; -- mem_ras_n - memory_mem_cas_n : out std_logic; -- mem_cas_n - memory_mem_we_n : out std_logic; -- mem_we_n - memory_mem_reset_n : out std_logic; -- mem_reset_n - memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq - memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs - memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n - memory_mem_odt : out std_logic; -- mem_odt - memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm - memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin - reset_reset_n : in std_logic := 'X'; -- reset_n - leds_external_connection_export : out std_logic_vector(9 downto 0); -- export - seven_segment_conduit_end_export : out std_logic_vector(41 downto 0); -- export - switches_external_connection_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export - hmi_subsystemapds9301_apdsinterrupt_irq_n : in std_logic := 'X'; -- irq_n - hmi_subsystemapds9301_i2c_scl_in : in std_logic := 'X'; -- scl_in - hmi_subsystemapds9301_i2c_scl_oe : out std_logic; -- scl_oe - hmi_subsystemapds9301_i2c_sda_in : in std_logic := 'X'; -- sda_in - hmi_subsystemapds9301_i2c_sda_oe : out std_logic; -- sda_oe - hmi_subsystemhdc1000_hdcrdy_interrupt : in std_logic := 'X'; -- interrupt - hmi_subsystemhdc1000_i2c_0_i2c_serial_sda_in : in std_logic := 'X'; -- sda_in - hmi_subsystemhdc1000_i2c_0_i2c_serial_scl_in : in std_logic := 'X'; -- scl_in - hmi_subsystemhdc1000_i2c_0_i2c_serial_sda_oe : out std_logic; -- sda_oe - hmi_subsystemhdc1000_i2c_0_i2c_serial_scl_oe : out std_logic; -- scl_oe - hmi_subsystemmpu9250_spi_MISO : in std_logic := 'X'; -- MISO - hmi_subsystemmpu9250_spi_MOSI : out std_logic; -- MOSI - hmi_subsystemmpu9250_spi_SCLK : out std_logic; -- SCLK - hmi_subsystemmpu9250_spi_SS_n : out std_logic; -- SS_n - hmi_subsystemmpu9250_mpuint_irq_n : in std_logic := 'X' -- irq_n - ); - end component HPSPlatform; - - component i2c_io_buf - PORT - ( - datain : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - oe : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - dataio : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0); - dataout : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - end component; - - - signal HPS_H2F_RST : std_logic; - - constant hps_cold_reset : std_logic := '0'; - constant hps_warm_reset : std_logic := '0'; - constant hps_debug_reset : std_logic := '0'; - constant sync_levels : natural := 100; - - signal stm_hw_events : std_logic_vector(27 downto 0); - signal test : std_logic; - signal key_reset_sync : std_logic_vector(sync_levels downto 0); - - signal hdc1000_i2c_serial_sda_in : std_logic; - signal hdc1000_i2c_serial_scl_in : std_logic; - signal hdc1000_i2c_serial_sda_oe : std_logic; - signal hdc1000_i2c_serial_scl_oe : std_logic; - - signal apds9301_i2c_serial_sda_in : std_logic; - signal apds9301_i2c_serial_scl_in : std_logic; - signal apds9301_i2c_serial_sda_oe : std_logic; - signal apds9301_i2c_serial_scl_oe : std_logic; - -BEGIN - - -u0 : component HPSPlatform - port map ( - clk_clk => CLOCK_50, -- clk.clk - reset_reset_n => key_reset_sync(0), -- reset.reset_n - memory_mem_a => HPS_DDR3_ADDR, -- memory.mem_a - memory_mem_ba => HPS_DDR3_BA, -- .mem_ba - memory_mem_ck => HPS_DDR3_CK_P, -- .mem_ck - memory_mem_ck_n => HPS_DDR3_CK_N, -- .mem_ck_n - memory_mem_cke => HPS_DDR3_CKE, -- .mem_cke - memory_mem_cs_n => HPS_DDR3_CS_N, -- .mem_cs_n - memory_mem_ras_n => HPS_DDR3_RAS_N, -- .mem_ras_n - memory_mem_cas_n => HPS_DDR3_CAS_N, -- .mem_cas_n - memory_mem_we_n => HPS_DDR3_WE_N, -- .mem_we_n - memory_mem_reset_n => HPS_DDR3_RESET_N, -- .mem_reset_n - memory_mem_dq => HPS_DDR3_DQ, -- .mem_dq - memory_mem_dqs => HPS_DDR3_DQS_P, -- .mem_dqs - memory_mem_dqs_n => HPS_DDR3_DQS_N, -- .mem_dqs_n - memory_mem_odt => HPS_DDR3_ODT, -- .mem_odt - memory_mem_dm => HPS_DDR3_DM, -- .mem_dm - memory_oct_rzqin => HPS_DDR3_RZQ, -- .oct_rzqin - hps_0_h2f_reset_reset_n => HPS_H2F_RST, -- hps_0_h2f_reset.reset_n - hps_0_f2h_cold_reset_req_reset_n => not(hps_cold_reset), -- hps_0_f2h_cold_reset_req.reset_n - hps_0_f2h_debug_reset_req_reset_n => not(hps_debug_reset), -- hps_0_f2h_debug_reset_req.reset_n - hps_0_f2h_stm_hw_events_stm_hwevents => stm_hw_events, -- hps_0_f2h_stm_hw_events.stm_hwevents - hps_0_f2h_warm_reset_req_reset_n => not(hps_warm_reset), -- hps_0_f2h_warm_reset_req.reset_n - hps_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK - hps_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0), -- .hps_io_emac1_inst_TXD0 - hps_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1), -- .hps_io_emac1_inst_TXD1 - hps_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2), -- .hps_io_emac1_inst_TXD2 - hps_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3), -- .hps_io_emac1_inst_TXD3 - hps_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0), -- .hps_io_emac1_inst_RXD0 - hps_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO, -- .hps_io_emac1_inst_MDIO - hps_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC, -- .hps_io_emac1_inst_MDC - hps_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV, -- .hps_io_emac1_inst_RX_CTL - hps_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN, -- .hps_io_emac1_inst_TX_CTL - hps_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK, -- .hps_io_emac1_inst_RX_CLK - hps_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1), -- .hps_io_emac1_inst_RXD1 - hps_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2), -- .hps_io_emac1_inst_RXD2 - hps_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3), -- .hps_io_emac1_inst_RXD3 - hps_io_hps_io_sdio_inst_CMD => HPS_SD_CMD, -- .hps_io_sdio_inst_CMD - hps_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0), -- .hps_io_sdio_inst_D0 - hps_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1), -- .hps_io_sdio_inst_D1 - hps_io_hps_io_sdio_inst_CLK => HPS_SD_CLK, -- .hps_io_sdio_inst_CLK - hps_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2), -- .hps_io_sdio_inst_D2 - hps_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3), -- .hps_io_sdio_inst_D3 - hps_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0), -- .hps_io_usb1_inst_D0 - hps_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1), -- .hps_io_usb1_inst_D1 - hps_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2), -- .hps_io_usb1_inst_D2 - hps_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3), -- .hps_io_usb1_inst_D3 - hps_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4), -- .hps_io_usb1_inst_D4 - hps_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5), -- .hps_io_usb1_inst_D5 - hps_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6), -- .hps_io_usb1_inst_D6 - hps_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7), -- .hps_io_usb1_inst_D7 - hps_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT, -- .hps_io_usb1_inst_CLK - hps_io_hps_io_usb1_inst_STP => HPS_USB_STP, -- .hps_io_usb1_inst_STP - hps_io_hps_io_usb1_inst_DIR => HPS_USB_DIR, -- .hps_io_usb1_inst_DIR - hps_io_hps_io_usb1_inst_NXT => HPS_USB_NXT, -- .hps_io_usb1_inst_NXT - hps_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK, -- .hps_io_spim1_inst_CLK - hps_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI, -- .hps_io_spim1_inst_MOSI - hps_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO, -- .hps_io_spim1_inst_MISO - hps_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS, -- .hps_io_spim1_inst_SS0 - hps_io_hps_io_uart0_inst_RX => HPS_UART_RX, -- .hps_io_uart0_inst_RX - hps_io_hps_io_uart0_inst_TX => HPS_UART_TX, -- .hps_io_uart0_inst_TX - hps_io_hps_io_i2c0_inst_SDA => HPS_I2C1_SDAT, -- .hps_io_i2c0_inst_SDA - hps_io_hps_io_i2c0_inst_SCL => HPS_I2C1_SCLK, -- .hps_io_i2c0_inst_SCL - hps_io_hps_io_i2c1_inst_SDA => HPS_I2C2_SDAT, -- .hps_io_i2c1_inst_SDA - hps_io_hps_io_i2c1_inst_SCL => HPS_I2C2_SCLK, -- .hps_io_i2c1_inst_SCL - hps_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N, -- hps_io_gpio_inst_GPIO09 - hps_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N, -- .hps_io_gpio_inst_GPIO35 - hps_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO, -- .hps_io_gpio_inst_GPIO40 - hps_io_hps_io_gpio_inst_GPIO48 => HPS_I2C_CONTROL, -- .hps_io_gpio_inst_GPIO48 - hps_io_hps_io_gpio_inst_GPIO53 => HPS_LED, -- hps_io_gpio_inst_GPIO53 - hps_io_hps_io_gpio_inst_GPIO54 => HPS_KEY, -- hps_io_gpio_inst_GPIO54 - hps_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT, -- .hps_io_gpio_inst_GPIO61 - - - -- periph --- leds_external_connection_export => LEDR, -- led_external_connection.export - switches_external_connection_export => SW, -- sw_external_connection.export - - seven_segment_conduit_end_export(6+7*0 downto 7*0) => HEX0, - seven_segment_conduit_end_export(6+7*1 downto 7*1) => HEX1, - seven_segment_conduit_end_export(6+7*2 downto 7*2) => HEX2, - seven_segment_conduit_end_export(6+7*3 downto 7*3) => HEX3, - seven_segment_conduit_end_export(6+7*4 downto 7*4) => HEX4, - seven_segment_conduit_end_export(6+7*5 downto 7*5) => HEX5, - - hmi_subsystemhdc1000_hdcrdy_interrupt => RH_TEMP_DRDY_n, -- hdc1000_0_hdcrdy.interrupt - hmi_subsystemhdc1000_i2c_0_i2c_serial_sda_in => hdc1000_i2c_serial_sda_in, -- hdc1000_i2c_0_i2c_serial.sda_in - hmi_subsystemhdc1000_i2c_0_i2c_serial_scl_in => hdc1000_i2c_serial_scl_in, -- .scl_in - hmi_subsystemhdc1000_i2c_0_i2c_serial_sda_oe => hdc1000_i2c_serial_sda_oe, -- .sda_oe - hmi_subsystemhdc1000_i2c_0_i2c_serial_scl_oe => hdc1000_i2c_serial_scl_oe, -- .scl_oe - - hmi_subsystemapds9301_apdsinterrupt_irq_n => LSENSOR_INT, -- hmi_subsystemapds9301_apdsinterrupt.irq_n - hmi_subsystemapds9301_i2c_sda_in => apds9301_i2c_serial_sda_in, -- hmi_subsystemapds9301_i2c_0_i2c_serial.scl_in - hmi_subsystemapds9301_i2c_scl_in => apds9301_i2c_serial_scl_in, -- .scl_oe - hmi_subsystemapds9301_i2c_sda_oe => apds9301_i2c_serial_sda_oe, -- .sda_in - hmi_subsystemapds9301_i2c_scl_oe => apds9301_i2c_serial_scl_oe, - - hmi_subsystemmpu9250_spi_MISO => MPU_AD0_SDO, -- hmi_subsystemmpu9250_spi_0_external.MISO - hmi_subsystemmpu9250_spi_MOSI => MPU_SDA_SDI, -- .MOSI - hmi_subsystemmpu9250_spi_SCLK => MPU_SCL_SCLK, -- .SCLK - hmi_subsystemmpu9250_spi_SS_n => MPU_CS_n, -- .SS_n - hmi_subsystemmpu9250_mpuint_irq_n => MPU_INT -- hmi_subsystemmpu9250_mpuint.irq_n - ); - - key_sync : process( CLOCK_50, HPS_H2F_RST, SW(0) ) - begin - if (HPS_H2F_RST AND SW(0)) = '0' then - key_reset_sync <= (others => '0'); - elsif rising_edge(CLOCK_50) then - key_reset_sync(sync_levels) <= '1'; - key_reset_sync(sync_levels-1 downto 0) <= key_reset_sync(sync_levels downto 1); - end if; - end process; -- key_sync - - hdc1000_i2c_io : component i2c_io_buf - port map ( - datain => (others => '0'), - oe(1) => hdc1000_i2c_serial_scl_oe, - oe(0) => hdc1000_i2c_serial_sda_oe, - dataout(1) => hdc1000_i2c_serial_scl_in, - dataout(0) => hdc1000_i2c_serial_sda_in, - dataio(1) => RH_TEMP_I2C_SCL, - dataio(0) => RH_TEMP_I2C_SDA); - - apds9301_i2c_io : component i2c_io_buf - port map ( - datain => (others => '0'), - oe(1) => apds9301_i2c_serial_scl_oe, - oe(0) => apds9301_i2c_serial_sda_oe, - dataout(1) => apds9301_i2c_serial_scl_in, - dataout(0) => apds9301_i2c_serial_sda_in, - dataio(1) => LSENSOR_SCL, - dataio(0) => LSENSOR_SDA); - - LEDR(0) <= HPS_H2F_RST AND key_reset_sync(0); - LEDR(LEDR'high downto 1) <= (others => '0'); - - GPIO_0( 0) <= RH_TEMP_DRDY_n; - GPIO_0( 1) <= RH_TEMP_I2C_SCL; - GPIO_0( 2) <= RH_TEMP_I2C_SDA; - - GPIO_0( 4) <= LSENSOR_INT; - GPIO_0( 5) <= LSENSOR_SCL; - GPIO_0( 6) <= LSENSOR_SDA; - - GPIO_0(10) <= MPU_SCL_SCLK; - GPIO_0(11) <= MPU_CS_n; - GPIO_0(12) <= MPU_INT; - GPIO_0(14) <= MPU_AD0_SDO; - GPIO_0(15) <= MPU_SDA_SDI; - -END ARCHITECTURE; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +ENTITY top IS + +PORT( + ---------FPGA Connections------------- + CLOCK_50 : in std_logic; + SW : in std_logic_vector(9 downto 0); + LEDR : out std_logic_vector(9 downto 0); + + + -- //////////// SEG7 ////////// + HEX0 : out std_logic_vector(6 downto 0); + HEX1 : out std_logic_vector(6 downto 0); + HEX2 : out std_logic_vector(6 downto 0); + HEX3 : out std_logic_vector(6 downto 0); + HEX4 : out std_logic_vector(6 downto 0); + HEX5 : out std_logic_vector(6 downto 0); + + -- //////////// Infrared Interface ////////// + IRDA_RXD : in std_logic; + IRDA_TXD : out std_logic; + + ---------HPS Connections--------------- + HPS_CONV_USB_N : inout std_logic; + HPS_DDR3_ADDR : out std_logic_vector(14 downto 0); + HPS_DDR3_BA : out std_logic_vector(2 downto 0); + HPS_DDR3_CAS_N : out std_logic; + HPS_DDR3_CKE : out std_logic; + HPS_DDR3_CK_N : out std_logic; + HPS_DDR3_CK_P : out std_logic; + HPS_DDR3_CS_N : out std_logic; + HPS_DDR3_DM : out std_logic_vector(3 downto 0); + HPS_DDR3_DQ : inout std_logic_vector(31 downto 0); + HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0); + HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0); + HPS_DDR3_ODT : out std_logic; + HPS_DDR3_RAS_N : out std_logic; + HPS_DDR3_RESET_N : out std_logic; + HPS_DDR3_RZQ : in std_logic; + HPS_DDR3_WE_N : out std_logic; + + HPS_ENET_GTX_CLK : out std_logic; + HPS_ENET_INT_N : inout std_logic; + HPS_ENET_MDC : out std_logic; + HPS_ENET_MDIO : inout std_logic; + HPS_ENET_RX_CLK : in std_logic; + HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); + HPS_ENET_RX_DV : in std_logic; + HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); + HPS_ENET_TX_EN : out std_logic; + + HPS_KEY : inout std_logic; + HPS_LED : inout std_logic; + + HPS_SD_CLK : out std_logic; + HPS_SD_CMD : inout std_logic; + HPS_SD_DATA : inout std_logic_vector(3 downto 0); + + HPS_UART_RX : in std_logic; + HPS_UART_TX : out std_logic; + + HPS_USB_CLKOUT : in std_logic; + HPS_USB_DATA : inout std_logic_vector(7 downto 0); + HPS_USB_DIR : in std_logic; + HPS_USB_NXT : in std_logic; + HPS_USB_STP : out std_logic; + + HPS_I2C1_SCLK : inout std_logic; + HPS_I2C1_SDAT : inout std_logic; + HPS_I2C2_SCLK : inout std_logic; + HPS_I2C2_SDAT : inout std_logic; + HPS_I2C_CONTROL : inout std_logic; + + HPS_LTC_GPIO : inout std_logic; + HPS_GSENSOR_INT : inout std_logic; + + HPS_SPIM_CLK : out std_logic; + HPS_SPIM_MISO : in std_logic; + HPS_SPIM_MOSI : out std_logic; + HPS_SPIM_SS : inout std_logic; + + --////////// GPIO, GPIO connect to RFS - RF and Sensor ////////// + --BT_KEY : inout std_logic; + --BT_UART_RX : in std_logic; + --BT_UART_TX : out std_logic; + LSENSOR_INT : in std_logic; + LSENSOR_SCL : inout std_logic; + LSENSOR_SDA : inout std_logic; + MPU_AD0_SDO : in std_logic; + MPU_CS_n : inout std_logic; + MPU_FSYNC : out std_logic; + MPU_INT : in std_logic; + MPU_SCL_SCLK : inout std_logic; + MPU_SDA_SDI : inout std_logic; + RH_TEMP_DRDY_n : in std_ulogic; + RH_TEMP_I2C_SCL : inout std_logic; + RH_TEMP_I2C_SDA : inout std_logic; + TMD_D : out std_logic_vector(7 downto 0); + --UART2USB_CTS : in std_logic; + --UART2USB_RTS : out std_logic; + --UART2USB_RX : in std_logic; + --UART2USB_TX : out std_logic; + --WIFI_EN : out std_logic; + --WIFI_RST_n : out std_logic; + --WIFI_UART0_CTS : in std_logic; + --WIFI_UART0_RTS : out std_logic; + --WIFI_UART0_RX : in std_logic; + --WIFI_UART0_TX : out std_logic; + --WIFI_UART1_RX : in std_logic + GPIO_0 : out std_logic_vector(35 downto 0) +); + +END ENTITY; + +ARCHITECTURE MAIN OF top IS + component HPSPlatform is + port ( + clk_clk : in std_logic := 'X'; -- clk + hmi_subsystemapds9301_apdsinterrupt_irq_n : in std_logic := 'X'; -- irq_n + hmi_subsystemapds9301_i2c_sda_in : in std_logic := 'X'; -- sda_in + hmi_subsystemapds9301_i2c_scl_in : in std_logic := 'X'; -- scl_in + hmi_subsystemapds9301_i2c_sda_oe : out std_logic; -- sda_oe + hmi_subsystemapds9301_i2c_scl_oe : out std_logic; -- scl_oe + hmi_subsystemhdc1000_hdcrdy_interrupt : in std_logic := 'X'; -- interrupt + hmi_subsystemhdc1000_i2c_0_i2c_serial_sda_in : in std_logic := 'X'; -- sda_in + hmi_subsystemhdc1000_i2c_0_i2c_serial_scl_in : in std_logic := 'X'; -- scl_in + hmi_subsystemhdc1000_i2c_0_i2c_serial_sda_oe : out std_logic; -- sda_oe + hmi_subsystemhdc1000_i2c_0_i2c_serial_scl_oe : out std_logic; -- scl_oe + hmi_subsystemmpu9250_mpuint_irq_n : in std_logic := 'X'; -- irq_n + hmi_subsystemmpu9250_spi_sclk : out std_logic; -- sclk + hmi_subsystemmpu9250_spi_mosi : out std_logic; -- mosi + hmi_subsystemmpu9250_spi_miso : in std_logic := 'X'; -- miso + hmi_subsystemmpu9250_spi_ss_n : out std_logic; -- ss_n + hps_0_f2h_cold_reset_req_reset_n : in std_logic := 'X'; -- reset_n + hps_0_f2h_debug_reset_req_reset_n : in std_logic := 'X'; -- reset_n + hps_0_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents + hps_0_f2h_warm_reset_req_reset_n : in std_logic := 'X'; -- reset_n + hps_0_h2f_reset_reset_n : out std_logic; -- reset_n + hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK + hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0 + hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1 + hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2 + hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3 + hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0 + hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO + hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC + hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL + hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL + hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK + hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1 + hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2 + hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3 + hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD + hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0 + hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1 + hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK + hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2 + hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3 + hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0 + hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1 + hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2 + hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3 + hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4 + hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5 + hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6 + hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7 + hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK + hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP + hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR + hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT + hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK + hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI + hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO + hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0 + hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX + hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX + hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA + hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL + hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA + hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL + hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09 + hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35 + hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40 + hps_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48 + hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53 + hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54 + hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61 + leds_external_connection_export : out std_logic_vector(9 downto 0); -- export + memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a + memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba + memory_mem_ck : out std_logic; -- mem_ck + memory_mem_ck_n : out std_logic; -- mem_ck_n + memory_mem_cke : out std_logic; -- mem_cke + memory_mem_cs_n : out std_logic; -- mem_cs_n + memory_mem_ras_n : out std_logic; -- mem_ras_n + memory_mem_cas_n : out std_logic; -- mem_cas_n + memory_mem_we_n : out std_logic; -- mem_we_n + memory_mem_reset_n : out std_logic; -- mem_reset_n + memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq + memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs + memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n + memory_mem_odt : out std_logic; -- mem_odt + memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm + memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin + reset_reset_n : in std_logic := 'X'; -- reset_n + seven_segment_conduit_end_export : out std_logic_vector(41 downto 0); -- export + switches_external_connection_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export + hmi_infrared_ir_tx_o_conduit : out std_logic; -- conduit + hmi_infrared_ir_rx_o_conduit : out std_logic; -- conduit + hmi_infrared_ir_rx_i_conduit : in std_logic := 'X' -- conduit + ); + end component HPSPlatform; + + component i2c_io_buf + PORT + ( + datain : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + oe : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + dataio : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0); + dataout : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + end component; + + + signal HPS_H2F_RST : std_logic; + + constant hps_cold_reset : std_logic := '0'; + constant hps_warm_reset : std_logic := '0'; + constant hps_debug_reset : std_logic := '0'; + constant sync_levels : natural := 100; + + signal stm_hw_events : std_logic_vector(27 downto 0); + signal test : std_logic; + signal key_reset_sync : std_logic_vector(sync_levels downto 0); + + signal hdc1000_i2c_serial_sda_in : std_logic; + signal hdc1000_i2c_serial_scl_in : std_logic; + signal hdc1000_i2c_serial_sda_oe : std_logic; + signal hdc1000_i2c_serial_scl_oe : std_logic; + + signal apds9301_i2c_serial_sda_in : std_logic; + signal apds9301_i2c_serial_scl_in : std_logic; + signal apds9301_i2c_serial_sda_oe : std_logic; + signal apds9301_i2c_serial_scl_oe : std_logic; + + signal ir_rx_mirror : std_logic; + +BEGIN + + +u0 : component HPSPlatform + port map ( + clk_clk => CLOCK_50, -- clk.clk + reset_reset_n => key_reset_sync(0), -- reset.reset_n + memory_mem_a => HPS_DDR3_ADDR, -- memory.mem_a + memory_mem_ba => HPS_DDR3_BA, -- .mem_ba + memory_mem_ck => HPS_DDR3_CK_P, -- .mem_ck + memory_mem_ck_n => HPS_DDR3_CK_N, -- .mem_ck_n + memory_mem_cke => HPS_DDR3_CKE, -- .mem_cke + memory_mem_cs_n => HPS_DDR3_CS_N, -- .mem_cs_n + memory_mem_ras_n => HPS_DDR3_RAS_N, -- .mem_ras_n + memory_mem_cas_n => HPS_DDR3_CAS_N, -- .mem_cas_n + memory_mem_we_n => HPS_DDR3_WE_N, -- .mem_we_n + memory_mem_reset_n => HPS_DDR3_RESET_N, -- .mem_reset_n + memory_mem_dq => HPS_DDR3_DQ, -- .mem_dq + memory_mem_dqs => HPS_DDR3_DQS_P, -- .mem_dqs + memory_mem_dqs_n => HPS_DDR3_DQS_N, -- .mem_dqs_n + memory_mem_odt => HPS_DDR3_ODT, -- .mem_odt + memory_mem_dm => HPS_DDR3_DM, -- .mem_dm + memory_oct_rzqin => HPS_DDR3_RZQ, -- .oct_rzqin + hps_0_h2f_reset_reset_n => HPS_H2F_RST, -- hps_0_h2f_reset.reset_n + hps_0_f2h_cold_reset_req_reset_n => not(hps_cold_reset), -- hps_0_f2h_cold_reset_req.reset_n + hps_0_f2h_debug_reset_req_reset_n => not(hps_debug_reset), -- hps_0_f2h_debug_reset_req.reset_n + hps_0_f2h_stm_hw_events_stm_hwevents => stm_hw_events, -- hps_0_f2h_stm_hw_events.stm_hwevents + hps_0_f2h_warm_reset_req_reset_n => not(hps_warm_reset), -- hps_0_f2h_warm_reset_req.reset_n + hps_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK + hps_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0), -- .hps_io_emac1_inst_TXD0 + hps_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1), -- .hps_io_emac1_inst_TXD1 + hps_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2), -- .hps_io_emac1_inst_TXD2 + hps_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3), -- .hps_io_emac1_inst_TXD3 + hps_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0), -- .hps_io_emac1_inst_RXD0 + hps_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO, -- .hps_io_emac1_inst_MDIO + hps_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC, -- .hps_io_emac1_inst_MDC + hps_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV, -- .hps_io_emac1_inst_RX_CTL + hps_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN, -- .hps_io_emac1_inst_TX_CTL + hps_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK, -- .hps_io_emac1_inst_RX_CLK + hps_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1), -- .hps_io_emac1_inst_RXD1 + hps_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2), -- .hps_io_emac1_inst_RXD2 + hps_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3), -- .hps_io_emac1_inst_RXD3 + hps_io_hps_io_sdio_inst_CMD => HPS_SD_CMD, -- .hps_io_sdio_inst_CMD + hps_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0), -- .hps_io_sdio_inst_D0 + hps_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1), -- .hps_io_sdio_inst_D1 + hps_io_hps_io_sdio_inst_CLK => HPS_SD_CLK, -- .hps_io_sdio_inst_CLK + hps_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2), -- .hps_io_sdio_inst_D2 + hps_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3), -- .hps_io_sdio_inst_D3 + hps_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0), -- .hps_io_usb1_inst_D0 + hps_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1), -- .hps_io_usb1_inst_D1 + hps_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2), -- .hps_io_usb1_inst_D2 + hps_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3), -- .hps_io_usb1_inst_D3 + hps_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4), -- .hps_io_usb1_inst_D4 + hps_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5), -- .hps_io_usb1_inst_D5 + hps_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6), -- .hps_io_usb1_inst_D6 + hps_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7), -- .hps_io_usb1_inst_D7 + hps_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT, -- .hps_io_usb1_inst_CLK + hps_io_hps_io_usb1_inst_STP => HPS_USB_STP, -- .hps_io_usb1_inst_STP + hps_io_hps_io_usb1_inst_DIR => HPS_USB_DIR, -- .hps_io_usb1_inst_DIR + hps_io_hps_io_usb1_inst_NXT => HPS_USB_NXT, -- .hps_io_usb1_inst_NXT + hps_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK, -- .hps_io_spim1_inst_CLK + hps_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI, -- .hps_io_spim1_inst_MOSI + hps_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO, -- .hps_io_spim1_inst_MISO + hps_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS, -- .hps_io_spim1_inst_SS0 + hps_io_hps_io_uart0_inst_RX => HPS_UART_RX, -- .hps_io_uart0_inst_RX + hps_io_hps_io_uart0_inst_TX => HPS_UART_TX, -- .hps_io_uart0_inst_TX + hps_io_hps_io_i2c0_inst_SDA => HPS_I2C1_SDAT, -- .hps_io_i2c0_inst_SDA + hps_io_hps_io_i2c0_inst_SCL => HPS_I2C1_SCLK, -- .hps_io_i2c0_inst_SCL + hps_io_hps_io_i2c1_inst_SDA => HPS_I2C2_SDAT, -- .hps_io_i2c1_inst_SDA + hps_io_hps_io_i2c1_inst_SCL => HPS_I2C2_SCLK, -- .hps_io_i2c1_inst_SCL + hps_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N, -- hps_io_gpio_inst_GPIO09 + hps_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N, -- .hps_io_gpio_inst_GPIO35 + hps_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO, -- .hps_io_gpio_inst_GPIO40 + hps_io_hps_io_gpio_inst_GPIO48 => HPS_I2C_CONTROL, -- .hps_io_gpio_inst_GPIO48 + hps_io_hps_io_gpio_inst_GPIO53 => HPS_LED, -- hps_io_gpio_inst_GPIO53 + hps_io_hps_io_gpio_inst_GPIO54 => HPS_KEY, -- hps_io_gpio_inst_GPIO54 + hps_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT, -- .hps_io_gpio_inst_GPIO61 + + + -- periph +-- leds_external_connection_export => LEDR, -- led_external_connection.export + switches_external_connection_export => SW, -- sw_external_connection.export + + seven_segment_conduit_end_export(6+7*0 downto 7*0) => HEX0, + seven_segment_conduit_end_export(6+7*1 downto 7*1) => HEX1, + seven_segment_conduit_end_export(6+7*2 downto 7*2) => HEX2, + seven_segment_conduit_end_export(6+7*3 downto 7*3) => HEX3, + seven_segment_conduit_end_export(6+7*4 downto 7*4) => HEX4, + seven_segment_conduit_end_export(6+7*5 downto 7*5) => HEX5, + + hmi_subsystemhdc1000_hdcrdy_interrupt => RH_TEMP_DRDY_n, -- hdc1000_0_hdcrdy.interrupt + hmi_subsystemhdc1000_i2c_0_i2c_serial_sda_in => hdc1000_i2c_serial_sda_in, -- hdc1000_i2c_0_i2c_serial.sda_in + hmi_subsystemhdc1000_i2c_0_i2c_serial_scl_in => hdc1000_i2c_serial_scl_in, -- .scl_in + hmi_subsystemhdc1000_i2c_0_i2c_serial_sda_oe => hdc1000_i2c_serial_sda_oe, -- .sda_oe + hmi_subsystemhdc1000_i2c_0_i2c_serial_scl_oe => hdc1000_i2c_serial_scl_oe, -- .scl_oe + + hmi_subsystemapds9301_apdsinterrupt_irq_n => LSENSOR_INT, -- hmi_subsystemapds9301_apdsinterrupt.irq_n + hmi_subsystemapds9301_i2c_sda_in => apds9301_i2c_serial_sda_in, -- hmi_subsystemapds9301_i2c_0_i2c_serial.scl_in + hmi_subsystemapds9301_i2c_scl_in => apds9301_i2c_serial_scl_in, -- .scl_oe + hmi_subsystemapds9301_i2c_sda_oe => apds9301_i2c_serial_sda_oe, -- .sda_in + hmi_subsystemapds9301_i2c_scl_oe => apds9301_i2c_serial_scl_oe, + + hmi_subsystemmpu9250_spi_miso => MPU_AD0_SDO, -- hmi_subsystemmpu9250_spi_0_external.MISO + hmi_subsystemmpu9250_spi_mosi => MPU_SDA_SDI, -- .MOSI + hmi_subsystemmpu9250_spi_sclk => MPU_SCL_SCLK, -- .SCLK + hmi_subsystemmpu9250_spi_ss_n => MPU_CS_n, -- .SS_n + hmi_subsystemmpu9250_mpuint_irq_n => MPU_INT, -- hmi_subsystemmpu9250_mpuint.irq_n + + hmi_infrared_ir_tx_o_conduit => IRDA_TXD, + hmi_infrared_ir_rx_o_conduit => ir_rx_mirror, + hmi_infrared_ir_rx_i_conduit => IRDA_RXD + ); + + key_sync : process( CLOCK_50, HPS_H2F_RST, SW(0) ) + begin + if (HPS_H2F_RST AND SW(0)) = '0' then + key_reset_sync <= (others => '0'); + elsif rising_edge(CLOCK_50) then + key_reset_sync(sync_levels) <= '1'; + key_reset_sync(sync_levels-1 downto 0) <= key_reset_sync(sync_levels downto 1); + end if; + end process; -- key_sync + + hdc1000_i2c_io : component i2c_io_buf + port map ( + datain => (others => '0'), + oe(1) => hdc1000_i2c_serial_scl_oe, + oe(0) => hdc1000_i2c_serial_sda_oe, + dataout(1) => hdc1000_i2c_serial_scl_in, + dataout(0) => hdc1000_i2c_serial_sda_in, + dataio(1) => RH_TEMP_I2C_SCL, + dataio(0) => RH_TEMP_I2C_SDA); + + apds9301_i2c_io : component i2c_io_buf + port map ( + datain => (others => '0'), + oe(1) => apds9301_i2c_serial_scl_oe, + oe(0) => apds9301_i2c_serial_sda_oe, + dataout(1) => apds9301_i2c_serial_scl_in, + dataout(0) => apds9301_i2c_serial_sda_in, + dataio(1) => LSENSOR_SCL, + dataio(0) => LSENSOR_SDA); + + LEDR(0) <= HPS_H2F_RST AND key_reset_sync(0); + LEDR(1) <= ir_rx_mirror; + LEDR(LEDR'high downto 2) <= (others => '0'); + + GPIO_0( 0) <= RH_TEMP_DRDY_n; + GPIO_0( 1) <= RH_TEMP_I2C_SCL; + GPIO_0( 2) <= RH_TEMP_I2C_SDA; + + GPIO_0( 4) <= LSENSOR_INT; + GPIO_0( 5) <= LSENSOR_SCL; + GPIO_0( 6) <= LSENSOR_SDA; + + GPIO_0(10) <= MPU_SCL_SCLK; + GPIO_0(11) <= MPU_CS_n; + GPIO_0(12) <= MPU_INT; + GPIO_0(14) <= MPU_AD0_SDO; + GPIO_0(15) <= MPU_SDA_SDI; + +END ARCHITECTURE; diff --git a/vhdltool-config.yaml b/vhdltool-config.yaml new file mode 100644 index 0000000..8f4db44 --- /dev/null +++ b/vhdltool-config.yaml @@ -0,0 +1,44 @@ +#Define your project's libraries and source files here. +#This section is compulsory. +Libraries: + #The name of the library. + - name: work + #The paths where the source files for this library can be found. Use "**" to match arbitrarily nested directories. + paths: + - "**/infrared/*.vhd" + +#Enable/disable typechecking +TypeCheck: True + +#Enable/disable check-as-you-type +CheckOnChange: True + +#Linter rule configuration. +#Rules can be enabled or disabled. +#Rules also have a severity. It may be one of Info, Warning, Critical or Error. +Lint: + #Threshold, below which messages are not displayed. + Threshold: Warning + + #Long form rule configuration. Both enabled/disabled status and severity can be configured this way. + DeclaredNotAssigned: + enabled: True + severity: Warning #Default severity Warning + + #Short form. Only enabled/disabled status can be specified. Severity is the default for the rule. + DeclaredNotRead: True #Default severity Warning + ReadNotAssigned: True #Default severity Critical + SensitivityListCheck: True #Default severity Warning + ExtraSensitivityListCheck: True #Default severity Warning + DuplicateSensitivity: True #Default severity Warning + LatchCheck: True #Default severity Critical + VariableNotRead: True #Default severity Warning + VariableNotWritten: True #Default severity Warning + PortNotRead: True #Default severity Warning + PortNotWritten: True #Default severity Critical + NoPrimaryUnit: True #Default severity Warning + DuplicateLibraryImport: True #Default severity Warning + DuplicatePackageUsage: True #Default severity Warning + DeprecatedPackages: True #Default severity Warning + ImplicitLibraries: True #Default severity Warning + DisconnectedPorts: True #Default severity Critical