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src/basic/verilog/pmod_leds Expand file tree Collapse file tree Original file line number Diff line number Diff line change 1+ filename = led
2+ pcf_file = led.pcf
3+
4+ ICELINK_DIR =$(shell df | grep iCELink | awk '{print $$6}')
5+ ${warning iCELink path : $(ICELINK_DIR ) }
6+
7+ build :
8+ yosys -p " synth_ice40 -blif $( filename) .blif" $(filename ) .v
9+ arachne-pnr -d 5k -P sg48 -p $(pcf_file ) $(filename ) .blif -o $(filename ) .asc
10+ icepack $(filename ) .asc $(filename ) .bin
11+
12+ prog_flash :
13+ @if [ -d ' $(ICELINK_DIR)' ]; \
14+ then \
15+ cp $(filename).bin $(ICELINK_DIR); \
16+ else \
17+ echo "iCELink not found"; \
18+ exit 1; \
19+ fi
20+
21+
22+ clean :
23+ rm -rf $(filename ) .blif $(filename ) .asc $(filename ) .bin
Original file line number Diff line number Diff line change 1+ set_io CLK 35
2+
3+ set_io LED[0] 45
4+ set_io LED[1] 43
5+ set_io LED[2] 38
6+ set_io LED[3] 36
7+ set_io LED[4] 46
8+ set_io LED[5] 44
9+ set_io LED[6] 42
10+ set_io LED[7] 37
11+
Original file line number Diff line number Diff line change 1+ // plug pmod-led on PMOD2
2+
3+ module switch (input CLK, output [7 :0 ] LED);
4+
5+ reg [25 :0 ] counter;
6+ wire lclk = counter[22 ];
7+
8+ initial begin
9+ LED = 8'b11111110 ;
10+ end
11+
12+ always @(posedge CLK)
13+ begin
14+ counter <= counter + 1 ;
15+ end
16+
17+ always @(posedge lclk)
18+ begin
19+ LED <= {LED[6 :0 ], LED[7 ]};
20+ end
21+
22+
23+ endmodule
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