Question about running on systems without nested paging support

[DuckKe-chen]

Hi @xlab-uiuc team,

I'm interested in testing the performance of this project in a non-nested paging environment (e.g., without Intel EPT/AMD NPT support). Could you please clarify:

1. Does DMT currently require hardware-assisted nested paging to function?

2. If nested paging is not mandatory, are there any specific configurations needed to run it on systems without this feature (e.g., BIOS-level settings or software workarounds)?

3. Are there known limitations when running without nested paging?

My research focuses specifically on evaluating address translation acceleration mechanisms. Any guidance would be greatly appreciated!

Thank you for your work on this project!

[tianyin]

@DuckKe-chen DMT assumes hardware-assisted translation.

non-nested paging environment (e.g., without Intel EPT/AMD NPT support)

Could you let us know what is the environment you are targeting?

[DuckKe-chen]

@DuckKe-chen DMT assumes hardware-assisted translation.

non-nested paging environment (e.g., without Intel EPT/AMD NPT support)

Could you let us know what is the environment you are targeting?

I would like to propose implementing a non-nested DMT on the BOOM(Berkeley Out-of-Order Machine) RISC-V processor.

[tianyin]

That sounds awesome. Is it for fun or a serious investment?

You are right that DMT directly applies to the native case (without virtualization). I was confused by "non-nested" DMT which seems that you are basically referring to the native case. Let me know if I'm wrong.

[DuckKe-chen]

Yes, I mean the direct application of DMT to native scenarios (non-virtualized environments). This idea is still in the experimental phase, not for a serious investment.