WAV_reader.syr

Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Reading design: WAV_reader.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "WAV_reader.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "WAV_reader"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320

---- Source Options
Top Module Name                    : WAV_reader
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/XilinxPrj/UCISW2-main-newer/UCISW2-main-newer/register.vhd" in Library work.
Entity <naszregister> compiled.
Entity <naszregister> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/XilinxPrj/UCISW2-main-newer/UCISW2-main-newer/WAV_reader.vhf" in Library work.
Architecture behavioral of Entity ifd_mxilinx_wav_reader is up to date.
Architecture behavioral of Entity wav_reader is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <WAV_reader> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <IFD_MXILINX_WAV_reader> in library <work> (architecture <behavioral>) with generics.
	INIT = '0'

Analyzing hierarchy for entity <naszregister> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <WAV_reader> in library <work> (Architecture <behavioral>).
WARNING:Xst:2211 - "C:/XilinxPrj/UCISW2-main-newer/UCISW2-main-newer/WAV_reader.vhf" line 251: Instantiating black box module <LCD1x64>.
WARNING:Xst:2211 - "C:/XilinxPrj/UCISW2-main-newer/UCISW2-main-newer/WAV_reader.vhf" line 262: Instantiating black box module <SDC_FileReader>.
    Set user-defined property "HU_SET =  XLXI_20_0" for instance <XLXI_20> in unit <WAV_reader>.
WARNING:Xst:2211 - "C:/XilinxPrj/UCISW2-main-newer/UCISW2-main-newer/WAV_reader.vhf" line 319: Instantiating black box module <DACWrite>.
Entity <WAV_reader> analyzed. Unit <WAV_reader> generated.

Analyzing generic Entity <IFD_MXILINX_WAV_reader> in library <work> (Architecture <behavioral>).
	INIT = '0'
    Set user-defined property "INIT =  0" for instance <I_36_15> in unit <IFD_MXILINX_WAV_reader>.
    Set user-defined property "IOB =  TRUE" for instance <I_36_15> in unit <IFD_MXILINX_WAV_reader>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <I_36_24> in unit <IFD_MXILINX_WAV_reader>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <I_36_24> in unit <IFD_MXILINX_WAV_reader>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <I_36_24> in unit <IFD_MXILINX_WAV_reader>.
Entity <IFD_MXILINX_WAV_reader> analyzed. Unit <IFD_MXILINX_WAV_reader> generated.

Analyzing Entity <naszregister> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/XilinxPrj/UCISW2-main-newer/UCISW2-main-newer/register.vhd" line 107: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <readState>, <freq>, <data_size_vec>
Entity <naszregister> analyzed. Unit <naszregister> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <naszregister>.
    Related source file is "C:/XilinxPrj/UCISW2-main-newer/UCISW2-main-newer/register.vhd".
    Register <Line<16>> equivalent to <freq<0>> has been removed
    Register <Line<26>> equivalent to <freq<10>> has been removed
    Register <Line<27>> equivalent to <freq<11>> has been removed
    Register <Line<28>> equivalent to <freq<12>> has been removed
    Register <Line<29>> equivalent to <freq<13>> has been removed
    Register <Line<30>> equivalent to <freq<14>> has been removed
    Register <Line<31>> equivalent to <freq<15>> has been removed
    Register <Line<32>> equivalent to <freq<16>> has been removed
    Register <Line<33>> equivalent to <freq<17>> has been removed
    Register <Line<34>> equivalent to <freq<18>> has been removed
    Register <Line<35>> equivalent to <freq<19>> has been removed
    Register <Line<17>> equivalent to <freq<1>> has been removed
    Register <Line<36>> equivalent to <freq<20>> has been removed
    Register <Line<37>> equivalent to <freq<21>> has been removed
    Register <Line<38>> equivalent to <freq<22>> has been removed
    Register <Line<39>> equivalent to <freq<23>> has been removed
    Register <Line<40>> equivalent to <freq<24>> has been removed
    Register <Line<41>> equivalent to <freq<25>> has been removed
    Register <Line<42>> equivalent to <freq<26>> has been removed
    Register <Line<43>> equivalent to <freq<27>> has been removed
    Register <Line<44>> equivalent to <freq<28>> has been removed
    Register <Line<45>> equivalent to <freq<29>> has been removed
    Register <Line<18>> equivalent to <freq<2>> has been removed
    Register <Line<46>> equivalent to <freq<30>> has been removed
    Register <Line<47>> equivalent to <freq<31>> has been removed
    Register <Line<19>> equivalent to <freq<3>> has been removed
    Register <Line<20>> equivalent to <freq<4>> has been removed
    Register <Line<21>> equivalent to <freq<5>> has been removed
    Register <Line<22>> equivalent to <freq<6>> has been removed
    Register <Line<23>> equivalent to <freq<7>> has been removed
    Register <Line<24>> equivalent to <freq<8>> has been removed
    Register <Line<25>> equivalent to <freq<9>> has been removed
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 82                                             |
    | Inputs             | 18                                             |
    | Outputs            | 21                                             |
    | Clock              | Clk_50MHz                 (rising_edge)        |
    | Clock enable       | Start                     (positive)           |
    | Reset              | Reset                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <readState>.
    Found 4-bit register for signal <Cmd>.
    Found 16-bit register for signal <Line<63:48>>.
    Found 16-bit register for signal <Line<15:0>>.
    Found 4-bit register for signal <Addr>.
    Found 12-bit register for signal <Data>.
    Found 16-bit register for signal <conversion>.
    Found 16-bit adder for signal <conversion$addsub0000> created at line 349.
    Found 64-bit up counter for signal <counter>.
    Found 12-bit adder for signal <Data_11$add0000> created at line 343.
    Found 32-bit register for signal <data_counter>.
    Found 32-bit adder for signal <data_counter$addsub0000> created at line 356.
    Found 32-bit register for signal <data_size_vec>.
    Found 64-bit comparator not equal for signal <data_size_vec_0$cmp_ne0000> created at line 300.
    Found 64-bit comparator not equal for signal <data_size_vec_10$cmp_ne0000> created at line 301.
    Found 64-bit comparator not equal for signal <data_size_vec_19$cmp_ne0000> created at line 303.
    Found 64-bit comparator not equal for signal <data_size_vec_24$cmp_ne0000> created at line 305.
    Found 32-bit register for signal <freq>.
    Found 64-bit comparator not equal for signal <freq_0$cmp_ne0000> created at line 275.
    Found 64-bit comparator not equal for signal <freq_10$cmp_ne0000> created at line 277.
    Found 64-bit comparator not equal for signal <freq_20$cmp_ne0000> created at line 280.
    Found 64-bit comparator not equal for signal <freq_24$cmp_ne0000> created at line 283.
    Found 64-bit up counter for signal <freqCounter>.
    Found 1-bit register for signal <incremented>.
    Found 64-bit comparator not equal for signal <Line_2$cmp_ne0000> created at line 290.
    Found 64-bit comparator equal for signal <Line_60$cmp_eq0000> created at line 265.
    Found 64-bit comparator not equal for signal <Line_8$cmp_ne0000> created at line 293.
    Found 6-bit register for signal <nextReadState>.
    Found 6-bit register for signal <readState>.
    Found 1-bit register for signal <sixteen>.
    Found 64-bit comparator equal for signal <state$cmp_eq0000> created at line 129.
    Found 64-bit comparator equal for signal <state$cmp_eq0001> created at line 134.
    Found 64-bit comparator equal for signal <state$cmp_eq0002> created at line 139.
    Found 64-bit comparator equal for signal <state$cmp_eq0003> created at line 144.
    Found 64-bit comparator greatequal for signal <state$cmp_ge0000> created at line 120.
    Found 64-bit comparator greatequal for signal <state$cmp_ge0001> created at line 175.
    Found 64-bit comparator greatequal for signal <state$cmp_ge0002> created at line 176.
    Found 64-bit comparator greatequal for signal <state$cmp_ge0003> created at line 178.
    Found 64-bit comparator greatequal for signal <state$cmp_ge0004> created at line 180.
    Found 64-bit comparator greatequal for signal <state$cmp_ge0005> created at line 182.
    Found 32-bit comparator greatequal for signal <state$cmp_ge0006> created at line 190.
    Found 1-bit register for signal <stereo>.
    Found 64-bit comparator not equal for signal <stereo$cmp_ne0000> created at line 265.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred 179 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred  23 Comparator(s).
Unit <naszregister> synthesized.


Synthesizing Unit <IFD_MXILINX_WAV_reader>.
    Related source file is "C:/XilinxPrj/UCISW2-main-newer/UCISW2-main-newer/WAV_reader.vhf".
Unit <IFD_MXILINX_WAV_reader> synthesized.


Synthesizing Unit <WAV_reader>.
    Related source file is "C:/XilinxPrj/UCISW2-main-newer/UCISW2-main-newer/WAV_reader.vhf".
WARNING:Xst:646 - Signal <XLXN_104> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <WAV_reader> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 3
 12-bit adder                                          : 1
 16-bit adder                                          : 1
 32-bit adder                                          : 1
# Counters                                             : 2
 64-bit up counter                                     : 2
# Registers                                            : 117
 1-bit register                                        : 111
 16-bit register                                       : 1
 32-bit register                                       : 1
 4-bit register                                        : 2
 6-bit register                                        : 2
# Comparators                                          : 23
 32-bit comparator greatequal                          : 1
 64-bit comparator equal                               : 5
 64-bit comparator greatequal                          : 6
 64-bit comparator not equal                           : 11

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <XLXI_24/state/FSM> on signal <state[1:10]> with one-hot encoding.
--------------------------
 State      | Encoding
--------------------------
 idle       | 0000000001
 start_read | 0000000010
 canal      | 0000000100
 sample     | 0000001000
 bits       | 0000010000
 data_size  | 0000100000
 load       | 0001000000
 loaded     | 0010000000
 play       | 1000000000
 play_end   | 0100000000
--------------------------
Reading core <LCD1x64.ngc>.
Reading core <SDC_FileReader.ngc>.
Reading core <DACWrite.ngc>.
Loading core <LCD1x64> for timing and area information for instance <XLXI_1>.
Loading core <SDC_FileReader> for timing and area information for instance <XLXI_3>.
Loading core <DACWrite> for timing and area information for instance <XLXI_21>.
INFO:Xst:2261 - The FF/Latch <Cmd_2> in Unit <XLXI_24> is equivalent to the following 3 FFs/Latches, which will be removed : <Cmd_3> <Addr_2> <Addr_3> 
INFO:Xst:2261 - The FF/Latch <Cmd_1> in Unit <XLXI_24> is equivalent to the following FF/Latch, which will be removed : <Addr_1> 
WARNING:Xst:1426 - The value init of the FF/Latch Cmd_1 hinder the constant cleaning in the block XLXI_24.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1293 - FF/Latch <Cmd_2> has a constant value of 0 in block <XLXI_24>. This FF/Latch will be trimmed during the optimization process.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# Adders/Subtractors                                   : 3
 12-bit adder                                          : 1
 16-bit adder                                          : 1
 32-bit adder                                          : 1
# Counters                                             : 2
 64-bit up counter                                     : 2
# Registers                                            : 180
 Flip-Flops                                            : 180
# Comparators                                          : 23
 32-bit comparator greatequal                          : 1
 64-bit comparator equal                               : 5
 64-bit comparator greatequal                          : 6
 64-bit comparator not equal                           : 11

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch Cmd_1 hinder the constant cleaning in the block naszregister.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch Addr_1 hinder the constant cleaning in the block naszregister.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1293 - FF/Latch <Cmd_2> has a constant value of 0 in block <naszregister>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Cmd_3> has a constant value of 0 in block <naszregister>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Addr_2> has a constant value of 0 in block <naszregister>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Addr_3> has a constant value of 0 in block <naszregister>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <Cmd_1> in Unit <naszregister> is equivalent to the following FF/Latch, which will be removed : <Addr_1> 
WARNING:Xst:2677 - Node <conversion_12> of sequential type is unconnected in block <naszregister>.
WARNING:Xst:2677 - Node <conversion_13> of sequential type is unconnected in block <naszregister>.
WARNING:Xst:2677 - Node <conversion_14> of sequential type is unconnected in block <naszregister>.
WARNING:Xst:2677 - Node <conversion_15> of sequential type is unconnected in block <naszregister>.

Optimizing unit <WAV_reader> ...

Optimizing unit <naszregister> ...

Optimizing unit <IFD_MXILINX_WAV_reader> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block WAV_reader, actual ratio is 29.
INFO:Xst:2260 - The FF/Latch <cntDigit_0> in Unit <XLXI_1> is equivalent to the following 4 FFs/Latches : <cntDigit_0_1> <cntDigit_0_2> <cntDigit_0_3> <cntDigit_0_4> 
INFO:Xst:2260 - The FF/Latch <cntDigit_1> in Unit <XLXI_1> is equivalent to the following 2 FFs/Latches : <cntDigit_1_1> <cntDigit_1_2> 
INFO:Xst:2260 - The FF/Latch <State_16> in Unit <XLXI_1> is equivalent to the following FF/Latch : <State_16_1> 
INFO:Xst:2260 - The FF/Latch <XLXI_94/State_11> in Unit <XLXI_3> is equivalent to the following FF/Latch : <XLXI_94/State_11_1> 
INFO:Xst:2260 - The FF/Latch <XLXI_94/State_15> in Unit <XLXI_3> is equivalent to the following FF/Latch : <XLXI_94/State_15_1> 
INFO:Xst:2260 - The FF/Latch <XLXI_94/SpC_1> in Unit <XLXI_3> is equivalent to the following FF/Latch : <XLXI_94/SpC_1_1> 
INFO:Xst:2260 - The FF/Latch <cntDigit_0> in Unit <XLXI_1> is equivalent to the following 4 FFs/Latches : <cntDigit_0_1> <cntDigit_0_2> <cntDigit_0_3> <cntDigit_0_4> 
INFO:Xst:2260 - The FF/Latch <cntDigit_1> in Unit <XLXI_1> is equivalent to the following 2 FFs/Latches : <cntDigit_1_1> <cntDigit_1_2> 
INFO:Xst:2260 - The FF/Latch <State_16> in Unit <XLXI_1> is equivalent to the following FF/Latch : <State_16_1> 
INFO:Xst:2260 - The FF/Latch <XLXI_94/State_11> in Unit <XLXI_3> is equivalent to the following FF/Latch : <XLXI_94/State_11_1> 
INFO:Xst:2260 - The FF/Latch <XLXI_94/State_15> in Unit <XLXI_3> is equivalent to the following FF/Latch : <XLXI_94/State_15_1> 
INFO:Xst:2260 - The FF/Latch <XLXI_94/SpC_1> in Unit <XLXI_3> is equivalent to the following FF/Latch : <XLXI_94/SpC_1_1> 

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 309
 Flip-Flops                                            : 309

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : WAV_reader.ngr
Top Level Output File Name         : WAV_reader
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 34

Cell Usage :
# BELS                             : 3808
#      BUF                         : 4
#      GND                         : 5
#      INV                         : 77
#      LUT1                        : 288
#      LUT2                        : 304
#      LUT2_D                      : 11
#      LUT2_L                      : 28
#      LUT3                        : 381
#      LUT3_D                      : 12
#      LUT3_L                      : 11
#      LUT4                        : 1080
#      LUT4_D                      : 74
#      LUT4_L                      : 102
#      MULT_AND                    : 10
#      MUXCY                       : 861
#      MUXF5                       : 80
#      MUXF6                       : 19
#      MUXF7                       : 5
#      OR2                         : 2
#      VCC                         : 5
#      XORCY                       : 449
# FlipFlops/Latches                : 915
#      FD                          : 74
#      FDCE                        : 1
#      FDE                         : 350
#      FDR                         : 77
#      FDRE                        : 245
#      FDRS                        : 15
#      FDRSE                       : 8
#      FDS                         : 141
#      FDSE                        : 4
# RAMS                             : 1
#      RAMB16_S9_S9                : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 33
#      IBUF                        : 9
#      IOBUF                       : 4
#      OBUF                        : 20
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500efg320-4 

 Number of Slices:                     1362  out of   4656    29%  
 Number of Slice Flip Flops:            914  out of   9312     9%  
 Number of 4 input LUTs:               2368  out of   9312    25%  
 Number of IOs:                          34
 Number of bonded IOBs:                  34  out of    232    14%  
    IOB Flip Flops:                       1
 Number of BRAMs:                         1  out of     20     5%  
 Number of GCLKs:                         1  out of     24     4%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clk_50MHz                          | BUFGP                  | 916   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
XLXI_20/XLXN_1(XLXI_20/I_36_29:G)  | NONE(XLXI_20/I_36_15)  | 1     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 12.738ns (Maximum Frequency: 78.508MHz)
   Minimum input arrival time before clock: 10.170ns
   Maximum output required time after clock: 7.533ns
   Maximum combinational path delay: 7.263ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'Clk_50MHz'
  Clock period: 12.738ns (frequency: 78.508MHz)
  Total number of paths / destination ports: 85631 / 2029
-------------------------------------------------------------------------
Delay:               12.738ns (Levels of Logic = 20)
  Source:            XLXI_3/XLXI_89/cntBytes_5 (FF)
  Destination:       XLXI_3/XLXI_89/cntBytes_11 (FF)
  Source Clock:      Clk_50MHz rising
  Destination Clock: Clk_50MHz rising

  Data Path: XLXI_3/XLXI_89/cntBytes_5 to XLXI_3/XLXI_89/cntBytes_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             3   0.591   0.706  XLXI_89/cntBytes_5 (XLXI_89/cntBytes<5>)
     LUT2_L:I0->LO         1   0.704   0.104  XLXI_89/Full512_mux0000212 (XLXI_89/Full512_mux0000212)
     LUT4:I3->O            2   0.704   0.451  XLXI_89/Full512_mux0000217 (XLXI_89/Full512_mux0000217)
     LUT4_D:I3->O          5   0.704   0.712  XLXI_89/NextState_0_cmp_eq000011 (XLXI_89/N3)
     LUT3:I1->O           84   0.704   1.283  XLXI_89/iDO_Rdy1 (DO_Rdy)
     end scope: 'XLXI_3'
     LUT4:I3->O            4   0.704   0.762  XLXI_24/Pop_and000129 (XLXN_87)
     begin scope: 'XLXI_3'
     LUT4:I0->O           14   0.704   1.035  XLXI_89/DoPOP_and00001 (XLXI_89/DoPOP)
     LUT3:I2->O            1   0.704   0.000  XLXI_89/Mcount_cntBytes_lut<0> (XLXI_89/Mcount_cntBytes_lut<0>)
     MUXCY:S->O            1   0.464   0.000  XLXI_89/Mcount_cntBytes_cy<0> (XLXI_89/Mcount_cntBytes_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  XLXI_89/Mcount_cntBytes_cy<1> (XLXI_89/Mcount_cntBytes_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  XLXI_89/Mcount_cntBytes_cy<2> (XLXI_89/Mcount_cntBytes_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  XLXI_89/Mcount_cntBytes_cy<3> (XLXI_89/Mcount_cntBytes_cy<3>)
     MUXCY:CI->O           1   0.059   0.000  XLXI_89/Mcount_cntBytes_cy<4> (XLXI_89/Mcount_cntBytes_cy<4>)
     MUXCY:CI->O           1   0.059   0.000  XLXI_89/Mcount_cntBytes_cy<5> (XLXI_89/Mcount_cntBytes_cy<5>)
     MUXCY:CI->O           1   0.059   0.000  XLXI_89/Mcount_cntBytes_cy<6> (XLXI_89/Mcount_cntBytes_cy<6>)
     MUXCY:CI->O           1   0.059   0.000  XLXI_89/Mcount_cntBytes_cy<7> (XLXI_89/Mcount_cntBytes_cy<7>)
     MUXCY:CI->O           1   0.059   0.000  XLXI_89/Mcount_cntBytes_cy<8> (XLXI_89/Mcount_cntBytes_cy<8>)
     MUXCY:CI->O           1   0.059   0.000  XLXI_89/Mcount_cntBytes_cy<9> (XLXI_89/Mcount_cntBytes_cy<9>)
     MUXCY:CI->O           0   0.059   0.000  XLXI_89/Mcount_cntBytes_cy<10> (XLXI_89/Mcount_cntBytes_cy<10>)
     XORCY:CI->O           1   0.804   0.000  XLXI_89/Mcount_cntBytes_xor<11> (XLXI_89/Result<11>)
     FDRE:D                    0.308          XLXI_89/cntBytes_11
    ----------------------------------------
    Total                     12.738ns (7.685ns logic, 5.053ns route)
                                       (60.3% logic, 39.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk_50MHz'
  Total number of paths / destination ports: 97 / 91
-------------------------------------------------------------------------
Offset:              10.170ns (Levels of Logic = 9)
  Source:            SW_0 (PAD)
  Destination:       XLXI_3/XLXI_94/State_23 (FF)
  Destination Clock: Clk_50MHz rising

  Data Path: SW_0 to XLXI_3/XLXI_94/State_23
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.218   0.420  SW_0_IBUF (SW_0_IBUF)
     BUF:I->O              1   0.704   0.595  XLXI_17 (FName<0>)
     begin scope: 'XLXI_3'
     LUT2:I0->O            1   0.704   0.424  XLXI_94/NextState_and0010124 (XLXI_94/NextState_and0010124)
     LUT4:I3->O            2   0.704   0.451  XLXI_94/NextState_and0010159_SW0 (N421)
     LUT4_L:I3->LO         1   0.704   0.275  XLXI_94/NextState_and0010159 (XLXI_94/NextState_and0010)
     LUT4:I0->O            1   0.704   0.424  XLXI_94/State_mux0002<8>117_SW0 (N489)
     LUT4_L:I3->LO         1   0.704   0.104  XLXI_94/State_mux0002<8>117 (XLXI_94/State_mux0002<8>117)
     LUT4:I3->O            1   0.704   0.420  XLXI_94/State_mux0002<8>167 (XLXI_94/State_mux0002<8>167)
     FDS:S                     0.911          XLXI_94/State_23
    ----------------------------------------
    Total                     10.170ns (7.057ns logic, 3.113ns route)
                                       (69.4% logic, 30.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk_50MHz'
  Total number of paths / destination ports: 40 / 17
-------------------------------------------------------------------------
Offset:              7.533ns (Levels of Logic = 4)
  Source:            XLXI_3/XLXI_96/I_Transc/State_3 (FF)
  Destination:       SDC_MOSI (PAD)
  Source Clock:      Clk_50MHz rising

  Data Path: XLXI_3/XLXI_96/I_Transc/State_3 to SDC_MOSI
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             12   0.591   1.136  XLXI_96/I_Transc/State_3 (XLXI_96/I_Transc/State<3>)
     LUT3_D:I0->O          3   0.704   0.706  XLXI_96/I_Transc/TxByteCE_cmp_eq000011 (XLXI_96/I_Transc/N6)
     LUT3:I0->O            1   0.704   0.420  XLXI_96/I_Transc/MOSI1 (SDC_MOSI)
     end scope: 'XLXI_3'
     OBUF:I->O                 3.272          SDC_MOSI_OBUF (SDC_MOSI)
    ----------------------------------------
    Total                      7.533ns (5.271ns logic, 2.262ns route)
                                       (70.0% logic, 30.0% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               7.263ns (Levels of Logic = 4)
  Source:            Clk_50MHz (PAD)
  Destination:       SPI_SCK (PAD)

  Data Path: Clk_50MHz to SPI_SCK
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O          918   1.457   1.410  Clk_50MHz_BUFGP (Clk_50MHz_BUFGP)
     begin scope: 'XLXI_21'
     INV:I->O              1   0.704   0.420  SPI_SCK1_INV_0 (SPI_SCK)
     end scope: 'XLXI_21'
     OBUF:I->O                 3.272          SPI_SCK_OBUF (SPI_SCK)
    ----------------------------------------
    Total                      7.263ns (5.433ns logic, 1.830ns route)
                                       (74.8% logic, 25.2% route)

=========================================================================


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.22 secs
 
--> 

Total memory usage is 4564652 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   17 (   0 filtered)
Number of infos    :   15 (   0 filtered)