UCISW2/WAV_reader_map.map at main · xololt-dev/UCISW2 · GitHub

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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'WAV_reader'

Design Information
------------------
Command Line   : map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off
-c 100 -o WAV_reader_map.ncd WAV_reader.ngd WAV_reader.pcf
Target Device  : xc3s500e
Target Package : fg320
Target Speed   : -4
Mapper Version : spartan3e -- $Revision: 1.55 $
Mapped Date    : Thu Apr 18 14:10:35 2024

Mapping design into LUTs...
Running directed packing...
WARNING:Pack:1186 - One or more I/O components have conflicting property values.
    For each occurrence, the system will use the property value attached to the
   pad.  Otherwise, the system will use the first property value read.  To view
   each occurrence, create a detailed map report (run map using the -detail
   option).
Running delay-based LUT packing...
Running related packing...
Updating timing models...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:           910 out of   9,312    9%
  Number of 4 input LUTs:             2,058 out of   9,312   22%
Logic Distribution:
  Number of occupied Slices:          1,373 out of   4,656   29%
    Number of Slices containing only related logic:   1,373 out of   1,373 100%
    Number of Slices containing unrelated logic:          0 out of   1,373   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:       2,347 out of   9,312   25%
    Number used as logic:             2,058
    Number used as a route-thru:        289

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 34 out of     232   14%
    IOB Flip Flops:                       1
  Number of RAMB16s:                      1 out of      20    5%
  Number of BUFGMUXs:                     1 out of      24    4%

Average Fanout of Non-Clock Nets:                3.56

Peak Memory Usage:  4436 MB
Total REAL time to MAP completion:  2 secs
Total CPU time to MAP completion:   2 secs

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "WAV_reader_map.mrp" for details.