baseSchema_map.mrp

Release 14.7 Map P.20131013 (lin64)
Xilinx Mapping Report File for Design 'baseSchema'

Design Information
------------------
Command Line   : map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off
-c 100 -o baseSchema_map.ncd baseSchema.ngd baseSchema.pcf 
Target Device  : xc3s500e
Target Package : fg320
Target Speed   : -4
Mapper Version : spartan3e -- $Revision: 1.55 $
Mapped Date    : Fri Mar 29 20:31:09 2024

Design Summary
--------------
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:           690 out of   9,312    7%
  Number of 4 input LUTs:             1,650 out of   9,312   17%
Logic Distribution:
  Number of occupied Slices:          1,071 out of   4,656   23%
    Number of Slices containing only related logic:   1,071 out of   1,071 100%
    Number of Slices containing unrelated logic:          0 out of   1,071   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:       1,824 out of   9,312   19%
    Number used as logic:             1,650
    Number used as a route-thru:        174

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 23 out of     232    9%
    IOB Flip Flops:                       1
  Number of RAMB16s:                      1 out of      20    5%
  Number of BUFGMUXs:                     1 out of      24    4%

Average Fanout of Non-Clock Nets:                3.52

Peak Memory Usage:  576 MB
Total REAL time to MAP completion:  2 secs 
Total CPU time to MAP completion:   2 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:Pack:1186 - One or more I/O components have conflicting property values.
    For each occurrence, the system will use the property value attached to the
   pad.  Otherwise, the system will use the first property value read.  To view
   each occurrence, create a detailed map report (run map using the -detail
   option).

Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network N6 has no load.
INFO:LIT:395 - The above info message is repeated 6 more times for the following
   (max. 5 shown):
   N7,
   N8,
   N9,
   XLXI_1/genIOBUF[0].instIOBUF/O,
   XLXI_1/genIOBUF[1].instIOBUF/O
   To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:159 - Net Timing constraints on signal Clk_50MHz are pushed forward
   through input buffer.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.

Section 4 - Removed Logic Summary
---------------------------------
   5 block(s) removed
  18 block(s) optimized away
   7 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "XLXI_20/XLXN_1" is sourceless and has been removed.
The signal "XLXI_20/XLXN_2" is sourceless and has been removed.
The signal "XLXI_1/genIOBUF[0].instIOBUF/O" is sourceless and has been removed.
The signal "XLXI_1/genIOBUF[1].instIOBUF/O" is sourceless and has been removed.
The signal "XLXI_1/genIOBUF[2].instIOBUF/O" is sourceless and has been removed.
The signal "XLXI_3/XLXI_94/NextState_cmp_ne000826/O" is sourceless and has been
removed.
The signal "XLXI_3/XLXI_94/NextState_cmp_ne000939_SW0/O" is sourceless and has
been removed.
Unused block "XLXI_1/genIOBUF[0].instIOBUF/IBUF" (BUF) removed.
Unused block "XLXI_1/genIOBUF[1].instIOBUF/IBUF" (BUF) removed.
Unused block "XLXI_1/genIOBUF[2].instIOBUF/IBUF" (BUF) removed.
Unused block "XLXI_3/XLXI_94/NextState_cmp_ne000826" (ROM) removed.
Unused block "XLXI_3/XLXI_94/NextState_cmp_ne000939_SW0" (ROM) removed.

Optimized Block(s):
TYPE 		BLOCK
LUT3 		XLXI_1/Mmux_Blank_mux0000_5
   optimized to 0
LUT3 		XLXI_1/Mmux_Blank_mux0000_6
   optimized to 0
LUT3 		XLXI_1/Mmux_Blank_mux0000_61
   optimized to 0
LUT3 		XLXI_1/Mmux_Blank_mux0000_62
   optimized to 0
LUT3 		XLXI_1/Mmux_Blank_mux0000_7
   optimized to 0
LUT3 		XLXI_1/Mmux_Blank_mux0000_71
   optimized to 0
LUT3 		XLXI_1/Mmux_Blank_mux0000_72
   optimized to 0
LUT3 		XLXI_1/Mmux_Blank_mux0000_8
   optimized to 0
GND 		XLXI_1/XST_GND
VCC 		XLXI_1/XST_VCC
GND 		XLXI_12
VCC 		XLXI_19
VCC 		XLXI_20/I_36_26
GND 		XLXI_20/I_36_29
LUT4 		XLXI_3/XLXI_94/NextState_cmp_ne000835
   optimized to 0
LUT4 		XLXI_3/XLXI_94/NextState_cmp_ne000949
   optimized to 0
GND 		XLXI_3/XST_GND
VCC 		XLXI_3/XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| BTN_EAST                           | IBUF             | INPUT     | LVTTL                |       |          |      |              | PULLDOWN | 0 / 0    |
| BTN_SOUTH                          | IBUF             | INPUT     | LVTTL                |       |          |      | IFF1         | PULLDOWN | 0 / 3    |
| BTN_WEST                           | IBUF             | INPUT     | LVTTL                |       |          |      |              | PULLDOWN | 0 / 0    |
| Clk_50MHz                          | IBUF             | INPUT     | LVTTL                |       |          |      |              |          | 0 / 0    |
| LCD_D<0>                           | IOB              | OUTPUT    | LVCMOS33             |       | 4        | SLOW |              |          | 0 / 0    |
| LCD_D<1>                           | IOB              | OUTPUT    | LVCMOS33             |       | 4        | SLOW |              |          | 0 / 0    |
| LCD_D<2>                           | IOB              | OUTPUT    | LVCMOS33             |       | 4        | SLOW |              |          | 0 / 0    |
| LCD_D<3>                           | IOB              | BIDIR     | LVCMOS33             |       | 4        | SLOW |              |          | 0 / 0    |
| LCD_E                              | IOB              | OUTPUT    | LVCMOS33             |       | 4        | SLOW |              |          | 0 / 0    |
| LCD_RS                             | IOB              | OUTPUT    | LVCMOS33             |       | 4        | SLOW |              |          | 0 / 0    |
| LCD_RW                             | IOB              | OUTPUT    | LVCMOS33             |       | 4        | SLOW |              |          | 0 / 0    |
| LED<0>                             | IOB              | OUTPUT    | LVTTL                |       | 4        | SLOW |              |          | 0 / 0    |
| LED<1>                             | IOB              | OUTPUT    | LVTTL                |       | 4        | SLOW |              |          | 0 / 0    |
| LED_7                              | IOB              | OUTPUT    | LVTTL                |       | 4        | SLOW |              |          | 0 / 0    |
| SDC_MISO                           | IBUF             | INPUT     | LVTTL                |       |          |      |              |          | 0 / 0    |
| SDC_MOSI                           | IOB              | OUTPUT    | LVTTL                |       | 12       | SLOW |              |          | 0 / 0    |
| SDC_SCK                            | IOB              | OUTPUT    | LVTTL                |       | 12       | SLOW |              |          | 0 / 0    |
| SDC_SS                             | IOB              | OUTPUT    | LVTTL                |       | 12       | SLOW |              |          | 0 / 0    |
| SF_CE                              | IOB              | OUTPUT    | LVCMOS33             |       | 4        | SLOW |              |          | 0 / 0    |
| SW_0                               | IBUF             | INPUT     | LVTTL                |       |          |      |              | PULLUP   | 0 / 0    |
| SW_1                               | IBUF             | INPUT     | LVTTL                |       |          |      |              | PULLUP   | 0 / 0    |
| SW_2                               | IBUF             | INPUT     | LVTTL                |       |          |      |              | PULLUP   | 0 / 0    |
| SW_3                               | IBUF             | INPUT     | LVTTL                |       |          |      |              | PULLUP   | 0 / 0    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Timing Report
--------------------------
This design was not run using timing mode.

Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.

Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.