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pd_system.qsys
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<?xml version="1.0" ?>
<!--Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<ipxact:design xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Altera Corporation</ipxact:vendor>
<ipxact:library>pd_system</ipxact:library>
<ipxact:name>pd_system</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:componentInstances></ipxact:componentInstances>
<ipxact:vendorExtensions>
<altera:catalog_card_info>
<altera:name>$${FILENAME}</altera:name>
<altera:displayName>$${FILENAME}</altera:displayName>
<altera:version>1.0</altera:version>
<altera:description></altera:description>
<altera:tags></altera:tags>
<altera:categories>Systems</altera:categories>
<altera:tool>QsysPro</altera:tool>
</altera:catalog_card_info>
<altera:altera_system_parameters>
<ipxact:parameters>
<ipxact:parameter parameterId="board" type="string">
<ipxact:name>board</ipxact:name>
<ipxact:displayName>Board</ipxact:displayName>
<ipxact:value>default</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="bonusData" type="string">
<ipxact:name>bonusData</ipxact:name>
<ipxact:displayName>bonusData</ipxact:displayName>
<ipxact:value>bonusData
{
element clock_in
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element code_data_ram
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element code_data_ram.s1
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
}
element nios
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element nios.dm_agent
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "1048576";
type = "String";
}
}
element nios.timer_sw_agent
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "1114112";
type = "String";
}
}
element reset_in
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element simple_dma_accelerator
{
datum _sortIndex
{
value = "5";
type = "int";
}
}
element simple_dma_accelerator.csr_ring_root_avs
{
datum baseAddress
{
value = "1114368";
type = "String";
}
}
element uart
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element uart.avalon_jtag_slave
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "1114176";
type = "String";
}
}
}
</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="cpuInfo" type="string">
<ipxact:name>cpuInfo</ipxact:name>
<ipxact:displayName>cpuInfo</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="designId" type="string">
<ipxact:name>designId</ipxact:name>
<ipxact:displayName>designId</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="device" type="string">
<ipxact:name>device</ipxact:name>
<ipxact:displayName>Device</ipxact:displayName>
<ipxact:value>10AS016C3U19E2LG</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="deviceFamily" type="string">
<ipxact:name>deviceFamily</ipxact:name>
<ipxact:displayName>Device family</ipxact:displayName>
<ipxact:value>Arria 10</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
<ipxact:name>deviceSpeedGrade</ipxact:name>
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
<ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="dflBitArray" type="string">
<ipxact:name>dflBitArray</ipxact:name>
<ipxact:displayName>dflBitArray</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="fabricMode" type="string">
<ipxact:name>fabricMode</ipxact:name>
<ipxact:displayName>fabricMode</ipxact:displayName>
<ipxact:value>QSYS</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generateLegacySim" type="bit">
<ipxact:name>generateLegacySim</ipxact:name>
<ipxact:displayName>generateLegacySim</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generationId" type="int">
<ipxact:name>generationId</ipxact:name>
<ipxact:displayName>Generation Id</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="globalResetBus" type="bit">
<ipxact:name>globalResetBus</ipxact:name>
<ipxact:displayName>Global reset</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="hdlLanguage" type="string">
<ipxact:name>hdlLanguage</ipxact:name>
<ipxact:displayName>hdlLanguage</ipxact:displayName>
<ipxact:value>VERILOG</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
<ipxact:name>hideFromIPCatalog</ipxact:name>
<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
<ipxact:name>lockedInterfaceDefinition</ipxact:name>
<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="sopcBorderPoints" type="bit">
<ipxact:name>sopcBorderPoints</ipxact:name>
<ipxact:displayName>Use SOPC Builder port naming</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="systemHash" type="longint">
<ipxact:name>systemHash</ipxact:name>
<ipxact:displayName>systemHash</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="systemInfos" type="string">
<ipxact:name>systemInfos</ipxact:name>
<ipxact:displayName>systemInfos</ipxact:displayName>
<ipxact:value><systemInfosDefinition>
<connPtSystemInfos>
<entry>
<key>clk</key>
<value>
<connectionPointName>clk</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_DOMAIN</key>
<value>1</value>
</entry>
<entry>
<key>CLOCK_RATE</key>
<value>50000000</value>
</entry>
<entry>
<key>RESET_DOMAIN</key>
<value>1</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfosDefinition></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="systemScripts" type="string">
<ipxact:name>systemScripts</ipxact:name>
<ipxact:displayName>systemScripts</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="testBenchDutName" type="string">
<ipxact:name>testBenchDutName</ipxact:name>
<ipxact:displayName>Use Test Bench Naming Pattern</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="timeStamp" type="longint">
<ipxact:name>timeStamp</ipxact:name>
<ipxact:displayName>timeStamp</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="useTestBenchNamingPattern" type="bit">
<ipxact:name>useTestBenchNamingPattern</ipxact:name>
<ipxact:displayName>Use Test Bench Naming Pattern</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:instance_parameters></altera:instance_parameters>
<altera:instance_script></altera:instance_script>
<altera:modules>
<altera:module altera:enabled="true" altera:auto_export="false">
<altera:entity_info>
<ipxact:vendor>Altera Corporation</ipxact:vendor>
<ipxact:library>clock_in</ipxact:library>
<ipxact:name>altera_generic_component</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
<altera:altera_module_parameters>
<ipxact:parameters>
<ipxact:parameter parameterId="bspCpu" type="bit">
<ipxact:name>bspCpu</ipxact:name>
<ipxact:displayName>BSP CPU</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="componentDefinition" type="string">
<ipxact:name>componentDefinition</ipxact:name>
<ipxact:displayName>Component definition</ipxact:displayName>
<ipxact:value><componentDefinition>
<boundary>
<interfaces>
<interface>
<name>in_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_clk</name>
<type>clock</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_clk</name>
<role>clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedDirectClock</key>
<value>in_clk</value>
</entry>
<entry>
<key>clockRate</key>
<value>50000000</value>
</entry>
<entry>
<key>clockRateKnown</key>
<value>true</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>altera_clock_bridge</className>
<version>19.2.0</version>
<displayName>Clock Bridge Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue>0</parameterDefaultValue>
<parameterName>DERIVED_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>in_clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>in_clk</key>
<value>
<connectionPointName>in_clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>50000000</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>out_clk</key>
<value>
<connectionPointName>out_clk</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>50000000</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="cpuInfo" type="string">
<ipxact:name>cpuInfo</ipxact:name>
<ipxact:displayName>Cpu Info</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="defaultBoundary" type="string">
<ipxact:name>defaultBoundary</ipxact:name>
<ipxact:displayName>Default boundary</ipxact:displayName>
<ipxact:value><boundaryDefinition>
<interfaces>
<interface>
<name>in_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_clk</name>
<type>clock</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_clk</name>
<role>clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedDirectClock</key>
<value>in_clk</value>
</entry>
<entry>
<key>clockRate</key>
<value>50000000</value>
</entry>
<entry>
<key>clockRateKnown</key>
<value>true</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generationInfoDefinition" type="string">
<ipxact:name>generationInfoDefinition</ipxact:name>
<ipxact:displayName>Generation Behavior</ipxact:displayName>
<ipxact:value><generationInfoDefinition>
<hdlLibraryName>pd_system_clock_in</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>pd_system_clock_in</fileSetName>
<fileSetFixedName>pd_system_clock_in</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>pd_system_clock_in</fileSetName>
<fileSetFixedName>pd_system_clock_in</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>pd_system_clock_in</fileSetName>
<fileSetFixedName>pd_system_clock_in</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>pd_system_clock_in</fileSetName>
<fileSetFixedName>pd_system_clock_in</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>pd_system_clock_in</fileSetName>
<fileSetFixedName>pd_system_clock_in</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="hdlParameters" type="string">
<ipxact:name>hdlParameters</ipxact:name>
<ipxact:displayName>HDL Parameters</ipxact:displayName>
<ipxact:value><hdlParameterDescriptorDefinitionList/></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="hlsFile" type="string">
<ipxact:name>hlsFile</ipxact:name>
<ipxact:displayName>HLS file</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="liveModuleName" type="string">
<ipxact:name>liveModuleName</ipxact:name>
<ipxact:displayName>Live Module Name</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="logicalView" type="string">
<ipxact:name>logicalView</ipxact:name>
<ipxact:displayName>Logical view</ipxact:displayName>
<ipxact:value>ip/pd_system/pd_system_clock_in.ip</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="moduleAssignmentDefinition" type="string">
<ipxact:name>moduleAssignmentDefinition</ipxact:name>
<ipxact:displayName>Module Assignments</ipxact:displayName>
<ipxact:value><assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="svInterfaceDefinition" type="string">
<ipxact:name>svInterfaceDefinition</ipxact:name>
<ipxact:displayName>System Verilog Interface definition</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</altera:altera_module_parameters>
</altera:module>
<altera:module altera:enabled="true" altera:auto_export="false">
<altera:entity_info>
<ipxact:vendor>Altera Corporation</ipxact:vendor>
<ipxact:library>code_data_ram</ipxact:library>
<ipxact:name>altera_generic_component</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
<altera:altera_module_parameters>
<ipxact:parameters>
<ipxact:parameter parameterId="bspCpu" type="bit">
<ipxact:name>bspCpu</ipxact:name>
<ipxact:displayName>BSP CPU</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="componentDefinition" type="string">
<ipxact:name>componentDefinition</ipxact:name>
<ipxact:displayName>Component definition</ipxact:displayName>
<ipxact:value><componentDefinition>
<boundary>
<interfaces>
<interface>
<name>clk1</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>read</name>
<role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>byteenable</name>
<role>byteenable</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>write</name>
<role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>1048576</value>
</entry>
<entry>
<key>addressUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk1</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset1</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>1048576</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>true</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>1</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset1</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>reset_req</name>
<role>reset_req</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk1</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>intel_onchip_memory</className>
<version>1.4.8</version>
<displayName>On-Chip Memory II (RAM or ROM) Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>autoInitializationFileName</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>UNIQUE_ID</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>NONE</parameterDefaultValue>
<parameterName>deviceFamily</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>NONE</parameterDefaultValue>
<parameterName>deviceFeatures</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FEATURES</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>s1</key>