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pd_system.qsys.legacy
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<?xml version="1.0" encoding="UTF-8"?>
<!--Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.-->
<system name="pd_system">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="Systems"
tool="QsysPro" />
<parameter name="board" value="default" />
<parameter name="bonusData"><![CDATA[bonusData
{
element clock_in
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element code_data_ram
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element code_data_ram.s1
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
}
element nios
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element nios.dm_agent
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "1048576";
type = "String";
}
}
element nios.timer_sw_agent
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "1114112";
type = "String";
}
}
element reset_in
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element simple_dma_accelerator
{
datum _sortIndex
{
value = "5";
type = "int";
}
}
element simple_dma_accelerator.csr_ring_root_avs
{
datum baseAddress
{
value = "1114368";
type = "String";
}
}
element uart
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element uart.avalon_jtag_slave
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "1114176";
type = "String";
}
}
}
]]></parameter>
<parameter name="cpuInfo" value="" />
<parameter name="designId" value="" />
<parameter name="device" value="10AS016C3U19E2LG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="dflBitArray" value="" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos>
<entry>
<key>clk</key>
<value>
<connectionPointName>clk</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_DOMAIN</key>
<value>1</value>
</entry>
<entry>
<key>CLOCK_RATE</key>
<value>50000000</value>
</entry>
<entry>
<key>RESET_DOMAIN</key>
<value>1</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfosDefinition>]]></parameter>
<parameter name="systemScripts" value="" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clock_in.in_clk" type="clock" dir="end" />
<interface name="reset" internal="reset_in.in_reset" type="reset" dir="end" />
<interface
name="simple_dma_accelerator_device_exception_bus"
internal="simple_dma_accelerator.device_exception_bus"
type="conduit"
dir="end" />
<module
name="clock_in"
kind="altera_generic_component"
version="1.0"
enabled="1">
<parameter name="bspCpu" value="" />
<parameter name="componentDefinition"><![CDATA[<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>in_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_clk</name>
<type>clock</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_clk</name>
<role>clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedDirectClock</key>
<value>in_clk</value>
</entry>
<entry>
<key>clockRate</key>
<value>50000000</value>
</entry>
<entry>
<key>clockRateKnown</key>
<value>true</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>altera_clock_bridge</className>
<version>19.2.0</version>
<displayName>Clock Bridge Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue>0</parameterDefaultValue>
<parameterName>DERIVED_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>in_clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>in_clk</key>
<value>
<connectionPointName>in_clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>50000000</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>out_clk</key>
<value>
<connectionPointName>out_clk</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>50000000</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="cpuInfo" value="" />
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
<name>in_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_clk</name>
<type>clock</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_clk</name>
<role>clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedDirectClock</key>
<value>in_clk</value>
</entry>
<entry>
<key>clockRate</key>
<value>50000000</value>
</entry>
<entry>
<key>clockRateKnown</key>
<value>true</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
<hdlLibraryName>pd_system_clock_in</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>pd_system_clock_in</fileSetName>
<fileSetFixedName>pd_system_clock_in</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>pd_system_clock_in</fileSetName>
<fileSetFixedName>pd_system_clock_in</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>pd_system_clock_in</fileSetName>
<fileSetFixedName>pd_system_clock_in</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>pd_system_clock_in</fileSetName>
<fileSetFixedName>pd_system_clock_in</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
<fileSetName>pd_system_clock_in</fileSetName>
<fileSetFixedName>pd_system_clock_in</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hdlParameters"><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></parameter>
<parameter name="hlsFile" value="" />
<parameter name="liveModuleName" value="" />
<parameter name="logicalView">ip/pd_system/pd_system_clock_in.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
name="code_data_ram"
kind="altera_generic_component"
version="1.0"
enabled="1">
<parameter name="bspCpu" value="false" />
<parameter name="componentDefinition"><![CDATA[<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>clk1</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>read</name>
<role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>byteenable</name>
<role>byteenable</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>write</name>
<role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>1048576</value>
</entry>
<entry>
<key>addressUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk1</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset1</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>1048576</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>true</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>1</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset1</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>reset_req</name>
<role>reset_req</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk1</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>intel_onchip_memory</className>
<version>1.4.8</version>
<displayName>On-Chip Memory II (RAM or ROM) Intel FPGA IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>autoInitializationFileName</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>UNIQUE_ID</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>NONE</parameterDefaultValue>
<parameterName>deviceFamily</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>NONE</parameterDefaultValue>
<parameterName>deviceFeatures</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FEATURES</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>s1</key>
<value>
<connectionPointName>s1</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value><address-map><slave name='s1' start='0x0' end='0x100000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>20</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
<value>32</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="cpuInfo" value="" />
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
<name>clk1</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>18</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>read</name>
<role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>byteenable</name>
<role>byteenable</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>write</name>
<role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>1</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>1048576</value>
</entry>
<entry>
<key>addressUnits</key>