Providing the tcl file for the partial modules

[RezaMehrabian]

Hello there,

In create_pr.tcl file, you used tcl files for rms (in line 12). How can I have those files? It seems we should provide them one by one, then convert the hierarchy block (gpio_0) to a partial region and use them to get the bitstream. However, in the tutorial video, it is shown how to get tcl when the hierarchy part (gpio_0) is already converted to PR. How we can have them to be imported in create_pr.tcl?

[yunqu]

Open the PR region as a block design, then use the tcl command write_bd_tcl. If you need to generate different tcls for RMs, make changes to the opened block design and reuse write_bd_tcl.

[RezaMehrabian]

I wrote a class in Python (Jupyter notebook) to download the partial bitstreams on PYNQ and I could run your project on v2.3. But when I start your project from scratch, I could not have the tcl files for partial modules.

When the project is open, I click on the goip_0 then it is opened. It contains three sub-blocks. One of them is rm and the others are static. Then I use write_bd_tcl. This command generates the same tcl file as gpio_pr. Both are completely the same. Do you mean I can open the partial region without opening the design (gpio_pr)?

[yunqu]

When you write_bd_tcl, make sure the PR region is the currently opened block design. Give it another name so you don't confuse yourself. It should work.

[RezaMehrabian]

Not working. It gives me the same file as the main block diagram. May you set some option for this? Or use write_ip_tcl command?

[yunqu]

I am attaching the result after running write_bd_tcl:

Successfully read diagram <gpio_pr> from BD file </home/yunq/workspace/pynqz1_partial/boards/Pynq-Z1/gpio_pr/gpio_pr/gpio_pr.srcs/sources_1/bd/gpio_pr/gpio_pr.bd>
open_bd_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 7350.129 ; gain = 0.000 ; free physical = 10669 ; free virtual = 49112
open_bd_design {/home/yunq/workspace/pynqz1_partial/boards/Pynq-Z1/gpio_pr/gpio_pr/gpio_pr.srcs/sources_1/bd/led_0/led_0.bd}
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - btns_gpio
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - leds_gpio
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - rgbleds_gpio
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - switches_gpio
Successfully read diagram <led_0> from BD file </home/yunq/workspace/pynqz1_partial/boards/Pynq-Z1/gpio_pr/gpio_pr/gpio_pr.srcs/sources_1/bd/led_0/led_0.bd>
write_bd_tcl example.tcl
INFO: [BD 5-148] Tcl file written out </home/yunq/workspace/pynqz1_partial/boards/Pynq-Z1/gpio_pr/gpio_pr/example.tcl>.

I checked example.tcl contents, it is the partial block design.

Another thing you can try is the Generate Block Design on the left panel of your GUI.

I am not sure which vivado you are using, if not 2018.3, please try 2018.3

[RezaMehrabian]

Do you set Tool->Enable Partial Reconfiguration? Maybe it is just the difference?
I use 2018.3

[yunqu]

Yes I did