stm32cube: stm32f4, stm32f7: Fix errata workaround

The errata for STM32F4 says successive writes to MACCR may be ignored,
and recommends reading back, waiting and rewriting as a workaround. This
workaround has been done correctly for writes to TE, but has mistakenly
been removed after enabling RE, which means that receiving sometimes
ended up not working. The errata recommends doing multiple writes, then
a final wait and rewrite at the end, which seems to work correctly.

Even though this is not mentioned in the F7 errata, the same fix is
required there.

Fixes zephyrproject-rtos/zephyr#107024.

Signed-off-by: Ole Morten Haaland <omh@ixys.no>

Author: icsys-omh

stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_eth.c

@@ -804,15 +804,15 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
     /* Enable the MAC transmission */
     SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
 
+    /* Enable the MAC reception */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
     /* Wait until the write operation will be taken into account :
     at least four TX_CLK/RX_CLK clock cycles */
     tmpreg1 = (heth->Instance)->MACCR;
     HAL_Delay(ETH_REG_WRITE_DELAY);
     (heth->Instance)->MACCR = tmpreg1;
 
-    /* Enable the MAC reception */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
     /* Enable ETH DMA interrupts:
     - Tx complete interrupt
     - Rx complete interrupt

stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_eth.c

@@ -804,15 +804,15 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
     /* Enable the MAC transmission */
     SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
 
+    /* Enable the MAC reception */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
     /* Wait until the write operation will be taken into account :
     at least four TX_CLK/RX_CLK clock cycles */
     tmpreg1 = (heth->Instance)->MACCR;
     HAL_Delay(ETH_REG_WRITE_DELAY);
     (heth->Instance)->MACCR = tmpreg1;
 
-    /* Enable the MAC reception */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
     /* Enable ETH DMA interrupts:
     - Tx complete interrupt
     - Rx complete interrupt