diff --git a/stm32cube/stm32f4xx/README b/stm32cube/stm32f4xx/README
index 5738b4d8d..22a3af7e6 100644
--- a/stm32cube/stm32f4xx/README
+++ b/stm32cube/stm32f4xx/README
@@ -60,4 +60,9 @@ Patch List:
     Impacted files:
      drivers/include/stm32f4xx_ll_fsmc.h
     ST Internal Reference: 223859
+
+   *Fix missing errata workaround after writing RE in ETH->MACCR
+    Impacted files:
+     drivers/src/stm32f4xx_hal_eth.c
+
    See release_note.html from STM32Cube
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_eth.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_eth.c
index 8530e8106..090f63362 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_eth.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_eth.c
@@ -804,15 +804,15 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
     /* Enable the MAC transmission */
     SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
 
+    /* Enable the MAC reception */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
     /* Wait until the write operation will be taken into account :
     at least four TX_CLK/RX_CLK clock cycles */
     tmpreg1 = (heth->Instance)->MACCR;
     HAL_Delay(ETH_REG_WRITE_DELAY);
     (heth->Instance)->MACCR = tmpreg1;
 
-    /* Enable the MAC reception */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
     /* Enable ETH DMA interrupts:
     - Tx complete interrupt
     - Rx complete interrupt
diff --git a/stm32cube/stm32f7xx/README b/stm32cube/stm32f7xx/README
index da6f58361..9f98e91ef 100644
--- a/stm32cube/stm32f7xx/README
+++ b/stm32cube/stm32f7xx/README
@@ -55,4 +55,8 @@ Patch List:
     Impacted files:
      drivers/include/Legacy/stm32_hal_legacy.h
 
+   *Fix missing errata workaround after writing RE in ETH->MACCR
+    Impacted files:
+     drivers/src/stm32f7xx_hal_eth.c
+
    See release_note.html from STM32Cube
diff --git a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_eth.c b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_eth.c
index 73f72d1e2..808143b55 100644
--- a/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_eth.c
+++ b/stm32cube/stm32f7xx/drivers/src/stm32f7xx_hal_eth.c
@@ -804,15 +804,15 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
     /* Enable the MAC transmission */
     SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
 
+    /* Enable the MAC reception */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
     /* Wait until the write operation will be taken into account :
     at least four TX_CLK/RX_CLK clock cycles */
     tmpreg1 = (heth->Instance)->MACCR;
     HAL_Delay(ETH_REG_WRITE_DELAY);
     (heth->Instance)->MACCR = tmpreg1;
 
-    /* Enable the MAC reception */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
     /* Enable ETH DMA interrupts:
     - Tx complete interrupt
     - Rx complete interrupt