|
clocks { |
|
clk_hse: clk-hse { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-hse-clock"; |
|
status = "disabled"; |
|
}; |
|
|
|
clk_hsi: clk-hsi { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32h7-hsi-clock"; |
|
clock-frequency = <DT_FREQ_M(64)>; |
|
status = "disabled"; |
|
}; |
|
|
|
clk_lse: clk-lse { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32-lse-clock"; |
|
clock-frequency = <32768>; |
|
driving-capability = <2>; |
|
status = "disabled"; |
|
}; |
|
|
|
clk_lsi: clk-lsi { |
|
#clock-cells = <0>; |
|
compatible = "fixed-clock"; |
|
clock-frequency = <DT_FREQ_K(32)>; |
|
status = "disabled"; |
|
}; |
|
|
|
pll1: pll: pll { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-pll-clock"; |
|
status = "disabled"; |
|
}; |
|
|
|
pll2: pll2 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-pll-clock"; |
|
status = "disabled"; |
|
}; |
|
|
|
pll3: pll3 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-pll-clock"; |
|
status = "disabled"; |
|
}; |
|
|
|
pll4: pll4 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-pll-clock"; |
|
status = "disabled"; |
|
}; |
|
|
|
cpusw: cpusw { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-cpu-clock-mux", "st,stm32-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
perck: perck { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic1: ic1 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic2: ic2 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic3: ic3 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic4: ic4 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic5: ic5 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic6: ic6 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic7: ic7 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic8: ic8 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic9: ic9 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic10: ic10 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic11: ic11 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic12: ic12 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic13: ic13 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic14: ic14 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic15: ic15 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic16: ic16 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic17: ic17 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic18: ic18 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic19: ic19 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
|
|
ic20: ic20 { |
|
#clock-cells = <0>; |
|
compatible = "st,stm32n6-ic-clock-mux"; |
|
status = "disabled"; |
|
}; |
|
}; |
Summary
Currently there's no way from the device tree to enable the MSI clock.
List of clocks can be found here.
zephyr/dts/arm/st/n6/stm32n6.dtsi
Lines 65 to 249 in e4f97dd
Describe the solution you'd like
I looked at stm32U5 and the stm32L1 for reference on how they added support for MSI clock enabling.
So it's like the u5 because it has a custom clock configuration, but it's also like the L1 in that it only has one MSI clock not MSIK and MSIS clock.
So a mix of both approaches would work.
Alternatives
No response
Additional Context
No response