STM32 Ethernet init regression: MAC init starts before DP83825 PHY reset is released after ethernet DT refactor

[NINI1988]

Describe the bug

Description

After #104310 (drivers: ethernet: set init priorities to the same value) and after
747adf2 (drivers: ethernet: stm32: remove parent child structure), the ethernet boot order is wrong.

The failure is reproducible on an STM32H745 board with a TI DP83825 PHY on RMII. With the older Zephyr state before that refactor, Ethernet init works. With the refactored state,
HAL_ETH_Init() times out in the STM32 HAL while the PHY reset pin is still asserted.

Working / failing Zephyr revisions

Working:

• 80fc086

Failing:

• 747adf2

A later mainline state also fails:

• 31fee3b

Board / hardware

• STM32H745
• RMII ethernet
• TI DP83825 PHY
• PHY reset pin: PF14
• DTS uses:
  • phy-handle = <&eth_phy>;
  • phy-connection-type = "rmii";
  • PHY node:
    • compatible = "ti,dp83825";
    • ti,interface-type = "rmii";
    • reset-gpios = <&gpiof 14 GPIO_ACTIVE_LOW>;

Observed behavior

Boot fails in the STM32 HAL during ethernet init:

• eth_initialize() calls eth_stm32_hal_init()
• HAL_ETH_Init() hangs in the DMAMR software reset loop
• the PHY reset pin is still low at that point, so the PHY is still held in reset

Init-order evidence

With the working revision, the init order is:

• MDIO
• PHY
• MAC

On the failing revision, the order becomes:

• MAC
• MDIO
• PHY

Regression

• This is a regression.

Steps to reproduce

No response

Relevant log output

[00:00:00.553,000] <err> eth_stm32_hal: HAL_ETH_SetMACConfig failed: 1
[00:00:00.563,000] <err> eth_stm32_hal: HAL_ETH_Start{_IT} failed

Impact

Showstopper – Prevents release or major functionality; system unusable.

Environment

• OS: WSL2
• ghcr.io/zephyrproject-rtos/ci:v0.28.6 and ghcr.io/zephyrproject-rtos/ci:v0.29.1

Additional Context

No response

[github-actions]

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[maass-hamburg]

you can instead use a gpio-hog or add a board specific init to make sure the gpio pin is at the right level