The risc-v privilege specs state that:
For G-stage translation Address bits 63:41 must all be zeros, or else a guest-page-fault exception occurs.
I wrote an assertion that states:
If stage 2 is enabled and stage 1 is disabled then the IOVA[63:41] must all be zero else a guest page exception occurs. (Because in the case of stage 1 disabled and stage 2 enabled, the IOVA is a GPA.)
Here is the counter-example of the assertion failure. In the 11th cycle, we have a first non-leaf pte for second stage translation with the iova[63:41] bits set then in the 12th cycle there must be trans_error with cause_code == guest_page_fault, but RTL is not giving any error.
The risc-v privilege specs state that:
I wrote an assertion that states:
Here is the counter-example of the assertion failure. In the 11th cycle, we have a first non-leaf pte for second stage translation with the iova[63:41] bits set then in the 12th cycle there must be trans_error with cause_code == guest_page_fault, but RTL is not giving any error.
