Removing delay statements

- Interferes with open soruce tools

Author: aolofsson

logikbench/blocks/fpu32/rtl/except.v

@@ -78,76 +78,75 @@ assign fractb = opb[22:0];
 //
 
 always @(posedge clk)
-	expa_ff <= #1 &expa;
+	expa_ff <= &expa;
 
 always @(posedge clk)
-	expb_ff <= #1 &expb;
-	
+	expb_ff <= &expb;
+
 always @(posedge clk)
-	infa_f_r <= #1 !(|fracta);
+	infa_f_r <= !(|fracta);
 
 always @(posedge clk)
-	infb_f_r <= #1 !(|fractb);
+	infb_f_r <= !(|fractb);
 
 always @(posedge clk)
-	qnan_r_a <= #1  fracta[22];
+	qnan_r_a <=  fracta[22];
 
 always @(posedge clk)
-	snan_r_a <= #1 !fracta[22] & |fracta[21:0];
-	
+	snan_r_a <= !fracta[22] & |fracta[21:0];
+
 always @(posedge clk)
-	qnan_r_b <= #1  fractb[22];
+	qnan_r_b <=  fractb[22];
 
 always @(posedge clk)
-	snan_r_b <= #1 !fractb[22] & |fractb[21:0];
+	snan_r_b <= !fractb[22] & |fractb[21:0];
 
 always @(posedge clk)
-	ind  <= #1 (expa_ff & infa_f_r) & (expb_ff & infb_f_r);
+	ind  <= (expa_ff & infa_f_r) & (expb_ff & infb_f_r);
 
 always @(posedge clk)
-	inf  <= #1 (expa_ff & infa_f_r) | (expb_ff & infb_f_r);
+	inf  <= (expa_ff & infa_f_r) | (expb_ff & infb_f_r);
 
 always @(posedge clk)
-	qnan <= #1 (expa_ff & qnan_r_a) | (expb_ff & qnan_r_b);
+	qnan <= (expa_ff & qnan_r_a) | (expb_ff & qnan_r_b);
 
 always @(posedge clk)
-	snan <= #1 (expa_ff & snan_r_a) | (expb_ff & snan_r_b);
+	snan <= (expa_ff & snan_r_a) | (expb_ff & snan_r_b);
 
 always @(posedge clk)
-	opa_nan <= #1 &expa & (|fracta[22:0]);
+	opa_nan <= &expa & (|fracta[22:0]);
 
 always @(posedge clk)
-	opb_nan <= #1 &expb & (|fractb[22:0]);
+	opb_nan <= &expb & (|fractb[22:0]);
 
 always @(posedge clk)
-	opa_inf <= #1 (expa_ff & infa_f_r);
+	opa_inf <= (expa_ff & infa_f_r);
 
 always @(posedge clk)
-	opb_inf <= #1 (expb_ff & infb_f_r);
+	opb_inf <= (expb_ff & infb_f_r);
 
 always @(posedge clk)
-	expa_00 <= #1 !(|expa);
+	expa_00 <= !(|expa);
 
 always @(posedge clk)
-	expb_00 <= #1 !(|expb);
+	expb_00 <= !(|expb);
 
 always @(posedge clk)
-	fracta_00 <= #1 !(|fracta);
+	fracta_00 <= !(|fracta);
 
 always @(posedge clk)
-	fractb_00 <= #1 !(|fractb);
+	fractb_00 <= !(|fractb);
 
 always @(posedge clk)
-	opa_00 <= #1 expa_00 & fracta_00;
+	opa_00 <= expa_00 & fracta_00;
 
 always @(posedge clk)
-	opb_00 <= #1 expb_00 & fractb_00;
+	opb_00 <= expb_00 & fractb_00;
 
 always @(posedge clk)
-	opa_dn <= #1 expa_00;
+	opa_dn <= expa_00;
 
 always @(posedge clk)
-	opb_dn <= #1 expb_00;
+	opb_dn <= expb_00;
 
 endmodule
-

logikbench/blocks/fpu32/rtl/fpu.v

@@ -109,28 +109,28 @@ wire		mul_00, div_00;
 //
 
 always @(posedge clk)
-	opa_r <= #1 opa;
+	opa_r <= opa;
 
 always @(posedge clk)
-	opb_r <= #1 opb;
+	opb_r <= opb;
 
 always @(posedge clk)
-	rmode_r1 <= #1 rmode;
+	rmode_r1 <= rmode;
 
 always @(posedge clk)
-	rmode_r2 <= #1 rmode_r1;
+	rmode_r2 <= rmode_r1;
 
 always @(posedge clk)
-	rmode_r3 <= #1 rmode_r2;
+	rmode_r3 <= rmode_r2;
 
 always @(posedge clk)
-	fpu_op_r1 <= #1 fpu_op;
+	fpu_op_r1 <= fpu_op;
 
 always @(posedge clk)
-	fpu_op_r2 <= #1 fpu_op_r1;
+	fpu_op_r2 <= fpu_op_r1;
 
 always @(posedge clk)
-	fpu_op_r3 <= #1 fpu_op_r2;
+	fpu_op_r3 <= fpu_op_r2;
 
 ////////////////////////////////////////////////////////////////////////
 //
@@ -190,7 +190,7 @@ pre_norm u1(.clk(clk),				// System Clock
 	);
 
 always @(posedge clk)
-	sign_fasu_r <= #1 sign_fasu;
+	sign_fasu_r <= sign_fasu;
 
 pre_norm_fmul u2(
 		.clk(clk),
@@ -208,16 +208,16 @@ pre_norm_fmul u2(
 
 
 always @(posedge clk)
-	sign_mul_r <= #1 sign_mul;
+	sign_mul_r <= sign_mul;
 
 always @(posedge clk)
-	sign_exe_r <= #1 sign_exe;
+	sign_exe_r <= sign_exe;
 
 always @(posedge clk)
-	inf_mul_r <= #1 inf_mul;
+	inf_mul_r <= inf_mul;
 
 always @(posedge clk)
-	exp_ovf_r <= #1 exp_ovf;
+	exp_ovf_r <= exp_ovf;
 
 
 ////////////////////////////////////////////////////////////////////////
@@ -233,7 +233,7 @@ add_sub27 u3(
 	.co(co_d) );			// Carry Output
 
 always @(posedge clk)
-	fract_out_q <= #1 {co_d, fract_out_d};
+	fract_out_q <= {co_d, fract_out_d};
 
 ////////////////////////////////////////////////////////////////////////
 //
@@ -288,10 +288,10 @@ div_r2 u6(.clk(clk), .opa(fdiv_opa), .opb(fractb_mul), .quo(quo), .rem(remainder
 assign remainder_00 = !(|remainder);
 
 always @(posedge clk)
-	div_opa_ldz_r1 <= #1 div_opa_ldz_d;
+	div_opa_ldz_r1 <= div_opa_ldz_d;
 
 always @(posedge clk)
-	div_opa_ldz_r2 <= #1 div_opa_ldz_r1;
+	div_opa_ldz_r2 <= div_opa_ldz_r1;
 
 
 ////////////////////////////////////////////////////////////////////////
@@ -310,19 +310,19 @@ wire		f2i_out_sign;
 
 always @(posedge clk)			// Exponent must be once cycle delayed
 	case(fpu_op_r2)
-	  0,1:	exp_r <= #1 exp_fasu;
-	  2,3:	exp_r <= #1 exp_mul;
-	  4:	exp_r <= #1 0;
-	  5:	exp_r <= #1 opa_r1[30:23];
+	  0,1:	exp_r <= exp_fasu;
+	  2,3:	exp_r <= exp_mul;
+	  4:	exp_r <= 0;
+	  5:	exp_r <= opa_r1[30:23];
 	endcase
 
 assign fract_div = (opb_dn ? quo[49:2] : {quo[26:0], 21'h0});
 
 always @(posedge clk)
-	opa_r1 <= #1 opa_r[30:0];
+	opa_r1 <= opa_r[30:0];
 
 always @(posedge clk)
-	fract_i2f <= #1 (fpu_op_r2==5) ?
+	fract_i2f <= (fpu_op_r2==5) ?
 			(sign_d ?  1-{24'h00, (|opa_r1[30:23]), opa_r1[22:0]}-1 : {24'h0, (|opa_r1[30:23]), opa_r1[22:0]}) :
 			(sign_d ? 1 - {opa_r1, 17'h01} : {opa_r1, 17'h0});
 
@@ -336,15 +336,15 @@ always @(fpu_op_r3 or fract_out_q or prod or fract_div or fract_i2f)
 
 
 always @(posedge clk)
-	opas_r1 <= #1 opa_r[31];
+	opas_r1 <= opa_r[31];
 
 always @(posedge clk)
-	opas_r2 <= #1 opas_r1;
+	opas_r2 <= opas_r1;
 
 assign sign_d = fpu_op_r2[1] ? sign_mul : sign_fasu;
 
 always @(posedge clk)
-	sign <= #1 (rmode_r2==2'h3) ? !sign_d : sign_d;
+	sign <= (rmode_r2==2'h3) ? !sign_d : sign_d;
 
 post_norm u4(.clk(clk),			// System Clock
 	.fpu_op(fpu_op_r3),		// Floating Point Operation
@@ -391,13 +391,13 @@ reg		opa_nan_r;
 
 
 always @(posedge clk)
-	fasu_op_r1 <= #1 fasu_op;
+	fasu_op_r1 <= fasu_op;
 
 always @(posedge clk)
-	fasu_op_r2 <= #1 fasu_op_r1;
+	fasu_op_r2 <= fasu_op_r1;
 
 always @(posedge clk)
-	inf_mul2 <= #1 exp_mul == 8'hff;
+	inf_mul2 <= exp_mul == 8'hff;
 
 
 // Force pre-set values for non numerical output
@@ -414,7 +414,7 @@ assign out_fixed = (	(qnan_d | snan_d) |
 		   )  ? QNAN : INF;
 
 always @(posedge clk)
-	out[30:0] <= #1 (mul_inf | div_inf | (inf_d & (fpu_op_r3!=3'b011) & (fpu_op_r3!=3'b101)) | snan_d | qnan_d) & fpu_op_r3!=3'b100 ? out_fixed :
+	out[30:0] <= (mul_inf | div_inf | (inf_d & (fpu_op_r3!=3'b011) & (fpu_op_r3!=3'b101)) | snan_d | qnan_d) & fpu_op_r3!=3'b100 ? out_fixed :
 			out_d;
 
 assign out_d_00 = !(|out_d);
@@ -423,7 +423,7 @@ assign sign_mul_final = (sign_exe_r & ((opa_00 & opb_inf) | (opb_00 & opa_inf)))
 assign sign_div_final = (sign_exe_r & (opa_inf & opb_inf)) ? !sign_mul_r : sign_mul_r | (opa_00 & opb_00);
 
 always @(posedge clk)
-	out[31] <= #1	((fpu_op_r3==3'b101) & out_d_00) ? (f2i_out_sign & !(qnan_d | snan_d) ) :
+	out[31] <= 	((fpu_op_r3==3'b101) & out_d_00) ? (f2i_out_sign & !(qnan_d | snan_d) ) :
 			((fpu_op_r3==3'b010) & !(snan_d | qnan_d)) ?	sign_mul_final :
 			((fpu_op_r3==3'b011) & !(snan_d | qnan_d)) ?	sign_div_final :
 			(snan_d | qnan_d | ind_d) ?			nan_sign_d :
@@ -440,7 +440,7 @@ assign ine_div  = (ine_d | overflow_d | underflow_d) & !(opb_00 | snan_d | qnan_
 assign ine_fasu = (ine_d | overflow_d | underflow_d) & !(snan_d | qnan_d | inf_d);
 
 always @(posedge  clk)
-	ine <= #1	 fpu_op_r3[2] ? ine_d :
+	ine <= 	 fpu_op_r3[2] ? ine_d :
 			!fpu_op_r3[1] ? ine_fasu :
 			 fpu_op_r3[0] ? ine_div  : ine_mul;
 
@@ -450,12 +450,12 @@ assign overflow_fmul = !inf_d & (inf_mul_r | inf_mul2 | overflow_d) & !(snan_d |
 assign overflow_fdiv = (overflow_d & !(opb_00 | inf_d | snan_d | qnan_d));
 
 always @(posedge clk)
-	overflow <= #1	 fpu_op_r3[2] ? 0 :
+	overflow <= 	 fpu_op_r3[2] ? 0 :
 			!fpu_op_r3[1] ? overflow_fasu :
 			 fpu_op_r3[0] ? overflow_fdiv : overflow_fmul;
 
 always @(posedge clk)
-	underflow_fmul_r <= #1 underflow_fmul_d;
+	underflow_fmul_r <= underflow_fmul_d;
 
 
 assign underflow_fmul1 = underflow_fmul_r[0] |
@@ -468,17 +468,17 @@ assign underflow_fmul = underflow_fmul1 & !(snan_d | qnan_d | inf_mul_r);
 assign underflow_fdiv = underflow_fasu & !opb_00;
 
 always @(posedge clk)
-	underflow <= #1  fpu_op_r3[2] ? 0 :
+	underflow <=  fpu_op_r3[2] ? 0 :
 			!fpu_op_r3[1] ? underflow_fasu :
 			 fpu_op_r3[0] ? underflow_fdiv : underflow_fmul;
 
 always @(posedge clk)
-	snan <= #1 snan_d;
+	snan <= snan_d;
 
 
 // Status Outputs
 always @(posedge clk)
-	qnan <= #1	fpu_op_r3[2] ? 0 : (
+	qnan <= 	fpu_op_r3[2] ? 0 : (
 						snan_d | qnan_d | (ind_d & !fasu_op_r2) |
 						(opa_00 & opb_00 & fpu_op_r3==3'b011) |
 						(((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3==3'b010)
@@ -489,7 +489,7 @@ assign inf_fmul = 	(((inf_mul_r | inf_mul2) & (rmode_r3==2'h0)) | opa_inf | opb_
 			fpu_op_r3==3'b010;
 
 always @(posedge clk)
-	inf <= #1	fpu_op_r3[2] ? 0 :
+	inf <= 	fpu_op_r3[2] ? 0 :
 			(!(qnan_d | snan_d) & (
 						((&out_d[30:23]) & !(|out_d[22:0]) & !(opb_00 & fpu_op_r3==3'b011)) |
 						(inf_d & !(ind_d & !fasu_op_r2) & !fpu_op_r3[1]) |
@@ -507,15 +507,15 @@ assign output_zero_fmul = (out_d_00 | opa_00 | opb_00) &
 			  !(opa_inf & opb_00) & !(opb_inf & opa_00);
 
 always @(posedge clk)
-	zero <= #1	fpu_op_r3==3'b101 ?	out_d_00 & !(snan_d | qnan_d):
+	zero <= 	fpu_op_r3==3'b101 ?	out_d_00 & !(snan_d | qnan_d):
 			fpu_op_r3==3'b011 ?	output_zero_fdiv :
 			fpu_op_r3==3'b010 ?	output_zero_fmul :
 						output_zero_fasu ;
 
 always @(posedge clk)
-	opa_nan_r <= #1 !opa_nan & fpu_op_r2==3'b011;
+	opa_nan_r <= !opa_nan & fpu_op_r2==3'b011;
 
 always @(posedge clk)
-	div_by_zero <= #1 opa_nan_r & !opa_00 & !opa_inf & opb_00;
+	div_by_zero <= opa_nan_r & !opa_00 & !opa_inf & opb_00;
 
 endmodule