Fixing class names

Author: aolofsson

logikbench/__init__.py

@@ -66,6 +66,7 @@
 from .arithmetic.sum.sum import Sum
 
 # Memory
+from .memory.axiram.axiram import Axiram
 from .memory.cache.cache import Cache
 from .memory.fifoasync.fifoasync import Fifoasync
 from .memory.fifosync.fifosync import Fifosync
@@ -81,19 +82,21 @@
 
 # Blocks
 from .blocks.aes.aes import Aes
-from .blocks.apbdev.apbdev import Apbdev
+from .blocks.apbregs.apbregs import Apbregs
 from .blocks.axicrossbar.axicrossbar import Axicrossbar
 from .blocks.ethmac.ethmac import Ethmac
 from .blocks.fft.fft import Fft
 from .blocks.firfix.firfix import Firfix
 from .blocks.firprog.firprog import Firprog
+from .blocks.fpu32.fpu32 import Fpu32
+from .blocks.fpu64.fpu64 import Fpu64
 from .blocks.ialu.ialu import Ialu
 from .blocks.i2c.i2c import I2c
 from .blocks.lfsr.lfsr import Lfsr
 from .blocks.picorv32.picorv32 import Picorv32
 from .blocks.serv.serv import Serv
 from .blocks.uart.uart import Uart
-from .blocks.umidev.umidev import Umidev
+from .blocks.umiregs.umiregs import Umiregs
 
 # EPFL
 from .epfl.adder.adder import Adder

logikbench/blocks/apbregs/apbregs.py

@@ -2,7 +2,7 @@
 from siliconcompiler.design import DesignSchema
 
 
-class Apbdev(DesignSchema):
+class Apbregs(DesignSchema):
     def __init__(self):
 
         name = 'apbregs'

logikbench/blocks/fpu32/README

@@ -1,3 +1,6 @@
 -downloaded from opencoreson Jul 14, 2025
 -removed debug logic that relied on synsopsys pragmas
 -some suspect practices like casex in code
+
+
+-removed delay statements

logikbench/blocks/fpu34/rtl/fpu34.v

@@ -2,7 +2,7 @@
 from siliconcompiler.design import DesignSchema
 
 
-class Fpu32(DesignSchema):
+class Fpu64(DesignSchema):
     def __init__(self):
 
         name = 'fpu64'
@@ -37,5 +37,5 @@ def __init__(self):
         self.set_topmodule(topmodule, fileset)
 
 if __name__ == "__main__":
-   d = Fpu32()
+   d = Fpu64()
    d.write_fileset(f"{d.name()}.f", fileset="rtl")

logikbench/blocks/fpu64/fpu64.py

@@ -2,7 +2,7 @@
 from siliconcompiler.design import DesignSchema
 
 
-class Umidev(DesignSchema):
+class Umiregs(DesignSchema):
     def __init__(self):
 
         name = 'umiregs'