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Adding synthesis examples
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README.md

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LogikBench
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LogikBench is technology agnostic RTL benchmark suite developed to promote open and unbiased:
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- EDA tool benchmarks (synthesis, placement, routing, verification, ...)
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- Foundry process benchmark
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- Standard cell library bench-marking
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- FPGA device bench-marking
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- Architecture exploration
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An parametrized RTL benchmark suite for open and unbiased evaluation of:
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1. EDA tools and flows (synthesis, placement, routing, verification, ...)
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2. Foundry processes
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3. Standard cell librares
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4. FPGA devices
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5. Digital architectures
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**Installation**
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# Installation
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```bash
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git clone https://github.com/zeroasiccorp/logikbench
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pip install -e .
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```
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**Examples**
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# Quick Start Quide
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Various examples demonstrating the LogikBench usage models can be found in the examples folder.
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## Synthesis Examples
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**Run `basic` benchmarks**
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```sh
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python examples/baremetal/make.py -g basic
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```
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**Clean build dir and then run `arithmetic` and `basic' benchmarks
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```sh
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python examples/baremetal/make.py -g basic arithmetic -clean
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```
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**Run a single `memory` benchmark in vivado
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```sh
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python examples/baremetal/make.py -g memory -name ramsp -tool vivado
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```
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# Benchmark Listing
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TBD
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## License
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# License
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The LogikBench project is licensed under [MIT](LICENSE). Individual benchmark components are covered by licensed documented by the LICENSE file found in the root directory of each benchmark.
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The LogikBench project is licensed under [MIT](LICENSE). Individual benchmarks are are covered by licensed documented by the LICENSE file found in the root directory of each benchmark.

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