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Adding basic yosys testing script
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tests/template.ys.j2

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# Read the Verilog source file
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read_verilog_file_list -f {{ cmdfile }}
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# Set the top module
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hierarchy -top {{ topmodule }}
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# Generic synthesis
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proc; opt; flatten; opt
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# Write synthesized netlist in Verilog
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write_verilog {{ netlist }}

tests/test_yosys.py

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import common
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import subprocess
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from jinja2 import Environment, FileSystemLoader
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def run_yosys(dlist):
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env = Environment(loader=FileSystemLoader('.'))
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template = env.get_template('template.ys.j2')
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for item in dlist:
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name = item.name()
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cmdfile = f'{name}.f'
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netlist = f'{name}.vg'
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# create .f cmd file
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item.write_fileset(cmdfile, fileset='rtl')
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topmodule = item.get_topmodule(fileset='rtl')
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# clean up cmd file (yosys bug)
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cleanfile = cmdfile + ".clean"
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with open(cmdfile, "r") as f_in, open(cleanfile, "w") as f_out:
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for line in f_in:
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if "//" not in line.strip():
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f_out.write(line)
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# create yosys script
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context = {
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'topmodule': topmodule,
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'cmdfile': cleanfile,
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'netlist' : netlist
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}
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output = template.render(context)
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script = f"{name}.ys"
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with open(script, 'w') as f:
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f.write(output)
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# run
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subprocess.run(["yosys", "-s", script], check=True)
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def test_yosys_basic():
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run_yosys(common.basic_list)
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def test_yosys_memory():
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run_yosys(common.memory_list)
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def test_icarus_arithmetic():
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run_yosys(common.arithmetic_list)

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