Adding umi/apb device

- Showing that optimizing for silly low performance bus is dumb, registers dominate area.

Author: aolofsson

logikbench/__init__.py

@@ -81,6 +81,7 @@
 
 # Blocks
 from .blocks.aes.aes import Aes
+from .blocks.apbdev.apbdev import Apbdev
 from .blocks.axicrossbar.axicrossbar import Axicrossbar
 from .blocks.ethmac.ethmac import Ethmac
 from .blocks.fft.fft import Fft
@@ -92,10 +93,9 @@
 from .blocks.picorv32.picorv32 import Picorv32
 from .blocks.serv.serv import Serv
 from .blocks.uart.uart import Uart
-
+from .blocks.umidev.umidev import Umidev
 
 # EPFL
-
 from .epfl.adder.adder import Adder
 from .epfl.arbiter.arbiter import Arbiter
 from .epfl.bar.bar import Bar

logikbench/blocks/apbdev/apbdev.py

@@ -0,0 +1,28 @@
+from os.path import dirname, abspath
+from siliconcompiler.design import DesignSchema
+
+
+class Apbdev(DesignSchema):
+    def __init__(self):
+
+        name = 'apbdev'
+        root = f'{name}_root'
+        source = [f'rtl/{name}.v']
+
+        # create a Design object
+        super().__init__(name)
+
+        # set data home directory
+        self.register_package(root, dirname(abspath(__file__)))
+
+        # rtl files
+        fileset = 'rtl'
+        for item in source:
+            self.add_file(item, fileset, package=root)
+
+        # top module
+        self.set_topmodule(name, fileset)
+
+if __name__ == "__main__":
+   d = Apbdev()
+   d.write_fileset(f"apbdev.f", fileset="rtl")

logikbench/blocks/apbdev/rtl/apbdev.v

@@ -1,3 +1,33 @@
-module apbdev();
-//complete code
+module apbdev
+  #(parameter AW = 32, // architecture address width
+    parameter RW = 32, // reg width
+    parameter RAW = 5  // reg address width
+    )
+   (input               nreset,      // async active low
+    input               apb_pclk,    // apb clock
+    input [RAW-1:0]     apb_paddr,   // address bus
+    input               apb_penable, // goes high for cycle 2:n
+    input               apb_pwrite,  // 1=write, 0=read
+    input [RW-1:0]      apb_pwdata,  // write data (8, 16, 32b)
+    input [3:0]         apb_pstrb,   // (optional) wire strobe bytelanes
+    input [2:0]         apb_pprot,   // (optional) level of access
+    input               apb_psel,    // select signal for each device
+    output              apb_pready,  // device "wait" signal
+    output reg [RW-1:0] apb_prdata   // read data (8, 16, 32b)
+    );
+
+   reg [RW-1:0] regs [(2**RAW)-1:0];
+
+   // apb interface
+   assign reg_write    = apb_psel & apb_penable & apb_pwrite;
+   assign reg_read     = apb_psel & ~apb_penable & ~apb_pwrite;
+   assign apb_pready   = 1'b1;
+
+   // register access
+   always @(posedge apb_pclk) begin
+      if (reg_write)
+        regs[apb_paddr] <= apb_pwdata;
+      apb_prdata <= regs[apb_paddr];
+   end
+
 endmodule

logikbench/blocks/umidev/rtl/umidev.v

@@ -26,11 +26,12 @@
  *   address range by setting the GRPOFFSET, GRPAW, and GRPID parameter.
  *   The address range [GRPOFFSET+:GRPAW] is checked against GRPID for a
  *   match. To disable the check, set the GRPAW to 0.
+ * - Modified from original umi_regif code to add an array of registers
  *
  *****************************************************************************/
 module umidev
   #(parameter RW = 32,        // register data width (RW<=DW)
-    parameter RAW = 32,       // register address width (RAW<=AW)
+    parameter RAW = 5,        // register address width (RAW<=AW)
     parameter GRPOFFSET = 24, // group address offset
     parameter GRPAW = 0,      // group address width
     parameter GRPID = 0,      // group ID
@@ -55,32 +56,34 @@ module umidev
     output reg [AW-1:0] udev_resp_dstaddr,
     output reg [AW-1:0] udev_resp_srcaddr,
     output reg [DW-1:0] udev_resp_data,
-    input               udev_resp_ready,
-    // single-port register interface
-    output              reg_write, // write enable
-    output              reg_read,  // read request
-    output [RAW-1:0]    reg_addr,  // address
-    output [RW-1:0]     reg_wdata, // write data
-    output [1:0]        reg_prot,  // protection
-    input [RW-1:0]      reg_rdata, // read data
-    input [1:0]         reg_err,   // device error
-    input               reg_ready  // device is ready
+    input               udev_resp_ready
     );
 
 `include "umi_messages.vh"
 
    // local state
    reg udev_req_safe_ready;
-
+   reg [RW-1:0] regs [(2**RAW)-1:0];
 
    // local wires
-   wire [CW-1:0] resp_cmd;
-   wire          cmd_read;
-   wire          cmd_write;
-   wire          cmd_posted;
-   wire          cmd_atomic;
-   wire          match;
-   wire          beat;
+   wire [CW-1:0]  resp_cmd;
+   wire           cmd_read;
+   wire           cmd_write;
+   wire           cmd_posted;
+   wire           cmd_atomic;
+   wire           match;
+   wire           beat;
+   wire           reg_ready;
+   wire [1:0]     reg_err;
+   wire [RAW-1:0] reg_addr;
+   wire [RW-1:0]  reg_wdata;
+   wire [RW-1:0]  reg_rdata;
+
+   //######################################
+   // Constants
+   //######################################
+   assign reg_ready = 1'b1;
+   assign reg_err[1:0] = 2'b00;
 
    //######################################
    // UMI Request
@@ -118,14 +121,20 @@ module umidev
    assign beat = udev_req_valid & udev_req_ready;
 
    //######################################
-   // Register Interface
+   // Register Access
    //######################################
 
    assign reg_write = (cmd_write | cmd_posted) & beat;
    assign reg_read = cmd_read & beat;
    assign reg_addr[RAW-1:0] = udev_req_dstaddr[RAW-1:0];
    assign reg_wdata[RW-1:0] = udev_req_data[RW-1:0];
-   assign reg_prot[1:0] = udev_req_cmd[21:20];
+
+   always @(posedge clk) begin
+      if (reg_write)
+        regs[reg_addr] <= reg_wdata[RW-1:0];
+   end
+
+   assign reg_rdata = regs[reg_addr];
 
    //######################################
    // UMI Response