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Adding wip fft module
1 parent 2708a35 commit d677d23

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logikbench/blocks/fft/fft.py

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import numpy as np
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from os.path import dirname, abspath
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from siliconcompiler.design import DesignSchema
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class Fft(DesignSchema):
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def __init__(self):
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name = 'fft'
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root = f'{name}_root'
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source = [f'rtl/{name}.v']
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# create a Design object
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super().__init__(name)
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# set data home directory
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self.register_package(root, dirname(abspath(__file__)))
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# rtl files
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fileset = 'rtl'
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for item in source:
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self.add_file(item, fileset, package=root)
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# top module
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self.set_topmodule(name, fileset)
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def sin_table(self, width=16, size=256):
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'''
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Generates sin table with:
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1 sign bit, N-1 fractional bits
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'''
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maxval = (2**(width-1)-1)
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for i in range(size):
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val = int(np.sin(2 * np.pi * i / size) * maxval)
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if val < 0:
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print(f"sine_lut[{i}] = -16'sd{abs(val)};")
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else:
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print(f"sine_lut[{i}] = 16'sd{val};")
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if __name__ == "__main__":
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d = Fft()
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d.write_fileset(f"fft.f", fileset="rtl")
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d.sin_table()

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