Adding fpu64

Author: aolofsson

logikbench/blocks/fpu64/LICENSE

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+
+/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd.
+
+Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
+
+*/

logikbench/blocks/fpu64/README

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+url: "https://github.com/T-head-Semi/openc910"
+rev: "e0c4ad8ec7f8c70f649d826ebd6c949086453272"

logikbench/blocks/fpu64/fpu64.py

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+from os.path import dirname, abspath
+from siliconcompiler.design import DesignSchema
+
+
+class Fpu32(DesignSchema):
+    def __init__(self):
+
+        name = 'fpu64'
+        topmodule = 'ct_vfdsu_double'
+        root = f'{name}_root'
+        source = ['rtl/ct_vfdsu_ctrl.v',
+                  'rtl/ct_vfdsu_pack.v',
+                  'rtl/ct_vfdsu_scalar_dp.v',
+		  'rtl/ct_vfdsu_srt_radix16_with_sqrt.v',
+                  'rtl/gated_clk_cell.v',
+                  'rtl/ct_vfdsu_double.v',
+                  'rtl/ct_vfdsu_prepare.v',
+                  'rtl/ct_vfdsu_srt_radix16_bound_table.v',
+                  'rtl/ct_vfdsu_srt.v',
+                  'rtl/ct_vfdsu_ff1.v',
+                  'rtl/ct_vfdsu_round.v',
+                  'rtl/ct_vfdsu_srt_radix16_only_div.v',
+                  'rtl/ct_vfdsu_top.v']
+
+        # create a Design object
+        super().__init__(name)
+
+        # set data home directory
+        self.register_package(root, dirname(abspath(__file__)))
+
+        # rtl files
+        fileset = 'rtl'
+        for item in source:
+            self.add_file(item, fileset, package=root)
+
+        # top module
+        self.set_topmodule(topmodule, fileset)
+
+if __name__ == "__main__":
+   d = Fpu32()
+   d.write_fileset(f"{d.name()}.f", fileset="rtl")