Merge pull request #270 from zeroasiccorp/rice/axi2umi_made_hostaddr_dynamic

made axi2umi hostaddr dynamic

Author: aolofsson

tests/adapters/axi2umi/test_axi2umi.py

@@ -36,6 +36,9 @@ async def setup(self):
         """Initialize and reset the DUT, create AXI master."""
         dut = self.dut
 
+        # Initialize config ports
+        dut.hostaddr.value = 0
+
         # Initialize AXI write signals
         dut.s_axi_wid.value = 0
         dut.s_axi_awvalid.value = 0

tests/adapters/axi2umi/test_axird2umi.py

@@ -33,6 +33,9 @@ async def setup(self):
         """Initialize and reset the DUT, create AXI master."""
         dut = self.dut
 
+        # Initialize config ports
+        dut.hostaddr.value = 0
+
         # Initialize AXI signals that cocotbext-axi may not drive
         dut.s_axi_arvalid.value = 0
         dut.s_axi_rready.value = 0

tests/adapters/axi2umi/test_axiwr2umi.py

@@ -109,6 +109,9 @@ async def setup(self):
         """Initialize and reset the DUT, create AXI master."""
         dut = self.dut
 
+        # Initialize config ports
+        dut.hostaddr.value = 0
+
         # Initialize AXI signals that cocotbext-axi may not drive
         dut.s_axi_wid.value = 0
         dut.s_axi_awvalid.value = 0

umi/__init__.py

@@ -3,7 +3,7 @@
 from umi import adapters
 from umi.common import Standard
 
-__version__ = "0.4.5"
+__version__ = "0.4.6"
 
 __all__ = [
     "Standard",

umi/adapters/axi2umi/rtl/axi2umi.v

@@ -30,14 +30,16 @@
  *                      unrecognized opcodes are forwarded to a drop port
  *
  * Parameters:
- *   CW       - UMI command width (default 32)
- *   DW       - Data width in bits, must be <= 128
- *   AW       - Address width in bits (default 64)
- *   IDW      - AXI ID width (default 8)
- *   HOSTADDR - UMI source address used by both write and read sub-modules
- *              (default MSB set). The lower DW/8 bits are reserved per the
- *              UMI spec; the write path uses those bits to encode the AXI
- *              write strobe value.
+ *   CW  - UMI command width (default 32)
+ *   DW  - Data width in bits, must be <= 128
+ *   AW  - Address width in bits (default 64)
+ *   IDW - AXI ID width (default 8)
+ *
+ * Config Ports:
+ *   hostaddr - UMI source address forwarded to both write and read sub-modules.
+ *              The lower DW/8 bits are reserved per the UMI spec; the write
+ *              path replaces those bits with the AXI write strobe value.
+ *              Typically static; if changed, must be synchronous to clk.
  *
  * Response Routing:
  *   UMI responses are routed back to the correct channel by inspecting the
@@ -49,18 +51,20 @@
  ******************************************************************************/
 
 module axi2umi #(
-  parameter           CW = 32,
-  parameter           DW = 128,
-  parameter           AW = 64,
-  parameter           IDW = 8,
-  /* Note the bottom DW/8 bits of HOSTADDR are ignored
-   * per UMI spec. The spec recommendation is to set the bottom
-   * DW/8 bits of srcaddr to the AXI write channels strobe value */
-  parameter [AW-1:0]  HOSTADDR = {AW{1'b0}}
+  parameter CW  = 32,
+  parameter DW  = 128,
+  parameter AW  = 64,
+  parameter IDW = 8
 )(
   input clk,
   input nreset,
 
+  /* UMI source address for all requests.
+   * The bottom DW/8 bits are replaced with the AXI write strobe on the
+   * write path (per UMI spec). Typically static if changed, must be
+   * synchronous to clk. */
+  input [AW-1:0] hostaddr,
+
   input [1:0] arbmode,
 
   //####################################
@@ -190,14 +194,14 @@ module axi2umi #(
   //####################################
 
   axiwr2umi #(
-    .CW       (CW),
-    .DW       (DW),
-    .AW       (AW),
-    .IDW      (IDW),
-    .HOSTADDR (HOSTADDR)
+    .CW  (CW),
+    .DW  (DW),
+    .AW  (AW),
+    .IDW (IDW)
   ) u_axiwr2umi (
     .clk              (clk),
     .nreset           (nreset),
+    .hostaddr         (hostaddr),
     // AXI4 Write Address Channel
     .s_axi_awid       (s_axi_awid),
     .s_axi_awaddr     (s_axi_awaddr),
@@ -243,14 +247,14 @@ module axi2umi #(
   //####################################
 
   axird2umi #(
-    .CW       (CW),
-    .DW       (DW),
-    .AW       (AW),
-    .IDW      (IDW),
-    .HOSTADDR (HOSTADDR)
+    .CW  (CW),
+    .DW  (DW),
+    .AW  (AW),
+    .IDW (IDW)
   ) u_axird2umi (
     .clk              (clk),
     .nreset           (nreset),
+    .hostaddr         (hostaddr),
     // AXI4 Read Address Channel
     .s_axi_arid       (s_axi_arid),
     .s_axi_araddr     (s_axi_araddr),

umi/adapters/axi2umi/rtl/axird2umi.v

@@ -24,11 +24,14 @@
  * setting EOM on the last response.
  *
  * Parameters:
- *   CW       - UMI command width (default 32)
- *   DW       - Data width in bits (default 128)
- *   AW       - Address width in bits (default 64)
- *   IDW      - AXI ID width (default 8)
- *   HOSTADDR - UMI source address, used as-is for all read requests
+ *   CW  - UMI command width (default 32)
+ *   DW  - Data width in bits (default 128)
+ *   AW  - Address width in bits (default 64)
+ *   IDW - AXI ID width (default 8)
+ *
+ * Config Ports:
+ *   hostaddr - UMI source address, used as-is for all read requests.
+ *              Typically static; if changed, must be synchronous to clk.
  *
  * Supported AXI4 Features:
  *   - Read address channel (AR) with ID, address, len, size, prot, qos
@@ -63,16 +66,18 @@
  ******************************************************************************/
 
 module axird2umi #(
-  parameter           CW = 32,
-  parameter           DW = 128,
-  parameter           AW = 64,
-  parameter           IDW = 8,
-  // UMI source address for read requests (used as-is, no strobe encoding)
-  parameter [AW-1:0]  HOSTADDR = {AW{1'b0}}
+  parameter CW  = 32,
+  parameter DW  = 128,
+  parameter AW  = 64,
+  parameter IDW = 8
 )(
   input clk,
   input nreset,
 
+  /* UMI source address for read requests (used as-is, no strobe encoding).
+   * Typically static; if changed, must be synchronous to clk. */
+  input [AW-1:0] hostaddr,
+
   //####################################
   // AXI4 FULL Read Channels
   //####################################
@@ -170,7 +175,7 @@ module axird2umi #(
   );
 
   assign uhost_req_dstaddr = {s_axi_araddr[AW-1:STRB_LOG2], {STRB_LOG2{1'b0}}};
-  assign uhost_req_srcaddr = HOSTADDR;
+  assign uhost_req_srcaddr = hostaddr;
   assign uhost_req_data = {DW{1'b0}};
 
   // Connect UMI Response to AXI4 Read Data Channel

umi/adapters/axi2umi/rtl/axiwr2umi.v

@@ -22,12 +22,15 @@
  * a UMI RESP_WRITE expected for each beat before proceeding to the next.
  *
  * Parameters:
- *   CW       - UMI command width (default 32)
- *   DW       - Data width in bits, must be <= 128 (16 byte strobe fits in SA[15:0])
- *   AW       - Address width in bits (default 64)
- *   IDW      - AXI ID width (default 8)
- *   HOSTADDR - UMI source address base. The bottom DW/8 bits are replaced
+ *   CW  - UMI command width (default 32)
+ *   DW  - Data width in bits, must be <= 128 (16 byte strobe fits in SA[15:0])
+ *   AW  - Address width in bits (default 64)
+ *   IDW - AXI ID width (default 8)
+ *
+ * Config Ports:
+ *   hostaddr - UMI source address base. The bottom DW/8 bits are replaced
  *              with the raw AXI write strobe value per UMI spec recommendation.
+ *              Typically static; if changed, must be synchronous to clk.
  *
  * Supported AXI4 Features:
  *   - Write address channel (AW) with ID, address, len, size, burst, prot, qos
@@ -75,18 +78,20 @@
  ******************************************************************************/
 
 module axiwr2umi #(
-  parameter           CW = 32,
-  parameter           DW = 128,
-  parameter           AW = 64,
-  parameter           IDW = 8,
-  /* Note the bottom DW/8 bits of HOSTADDR are ignored
-   * Per UMI spec the recommendation is to set the bottom
-   * DW/8 bits of srcaddr to the AXI write channels strobe value */
-  parameter [AW-1:0]  HOSTADDR = {AW{1'b0}}
+  parameter CW  = 32,
+  parameter DW  = 128,
+  parameter AW  = 64,
+  parameter IDW = 8
 )(
   input clk,
   input nreset,
 
+  /* UMI source address base.
+   * Note: The bottom DW/8 bits of hostaddr are ignored per UMI spec.
+   * Those bits carry the raw AXI write strobe value instead.
+   * Typically static if changed, must be synchronous to clk. */
+  input [AW-1:0] hostaddr,
+
   //####################################
   // AXI4 FULL Write Channels
   //####################################
@@ -318,7 +323,7 @@ module axiwr2umi #(
     .packet_cmd         (uhost_req_cmd)
   );
 
-  assign uhost_req_srcaddr[AW-1:0] = {HOSTADDR[AW-1:DW/8], s_axi_wstrb[DW/8-1:0]};
+  assign uhost_req_srcaddr[AW-1:0] = {hostaddr[AW-1:DW/8], s_axi_wstrb[DW/8-1:0]};
   // Offset destination address to the first active strobe byte
   assign uhost_req_dstaddr[AW-1:0] = dst_addr[AW-1:0] + {{(AW-STRB_LOG2-1){1'b0}}, right_most_strb_bit_index[STRB_LOG2:0]};