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aolofssonaolofsson
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Merge pull request #280 from zeroasiccorp/umi_monitor
Adding umi monitor
2 parents fddd7d3 + 2bd0432 commit 7b083ba

8 files changed

Lines changed: 404 additions & 6 deletions

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‎.gitignore‎

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# simulation
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######################
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build/
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gtkw_files/
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*.q
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*.out
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*.vcd
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*.fst
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build/
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gmon.out
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coverage.dat
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*.fsdb
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*.dat
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*.log
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*.vcd
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a.out
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*.vvp
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*.f
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*.dump
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*.tmp
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*.vpi
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######################
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# Editor

‎tests/sumi/conftest.py‎

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@@ -43,7 +43,6 @@ def __init__(
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sumi.Isolate(),
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sumi.Mux(),
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sumi.Regif(),
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sumi.Switch(),
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sumi.RAM()
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]
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‎tests/sumi/test_switch.py‎

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from switchboard import UmiTxRx, delete_queue
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@pytest.mark.skip(reason="Skipped until SB has been properly updated")
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def test_switch(sumi_dut, umi_send, sb_umi_valid_mode, sb_umi_ready_mode):
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n = 1000 # Number of transactions to be sent to each switch input port
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in_ports = 4 # Number of input ports. Must match testbench

‎umi/__init__.py‎

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from umi import adapters
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from umi.common import Standard
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try:
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from umi._version import __version__
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except ImportError:

‎umi/sumi/__init__.py‎

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from .umi_isolate.umi_isolate import Isolate
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from .umi_memagent.umi_memagent import MemAgent
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from .umi_memif.umi_memif import Memif
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from .umi_monitor.umi_monitor import Monitor
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from .umi_mux.umi_mux import Mux
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from .umi_mux2.umi_mux2 import Mux2
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from .umi_pack.umi_pack import Pack
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from .umi_pipeline.umi_pipeline import Pipeline
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from .umi_ram.umi_ram import RAM
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from .umi_regif.umi_regif import Regif
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from .umi_stream.umi_stream import Stream
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from .umi_switch.umi_switch import Switch
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# from .umi_switch.umi_switch import Switch
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from .umi_tester.umi_tester import Tester
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from .umi_unpack.umi_unpack import Unpack
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from .umi_demux.umi_demux import Demux
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'Isolate',
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'MemAgent',
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'Memif',
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'Monitor',
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'Mux',
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'Mux2',
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'Pack',
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'Pipeline',
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'RAM',
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'Regif',
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'Stream',
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'Switch',
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'Tester',
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'Unpack',
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'Demux']

‎umi/sumi/umi_monitor/rtl/umi_monitor.v‎

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/*******************************************************************************
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* Copyright 2026 Zero ASIC Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* ----
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*
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* Documentation:
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*
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* Passive UMI bus monitor. Taps a UMI bus without driving any signals.
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*
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* Synthesis: produces a 1-cycle 'beat' pulse on every valid+ready
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* handshake. Can be used for transaction counters, performance
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* monitors, or activity indicators.
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*
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* Simulation: on negedge clock, displays the full transaction
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* (opcode name, addresses, data) whenever a handshake occurs.
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* Acts as a built-in protocol analyzer for debug.
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*
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******************************************************************************/
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module umi_monitor
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#(parameter CW = 32,
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parameter AW = 64,
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parameter DW = 128,
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parameter TIMEOUT = 100, // simulation only
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parameter VERBOSE = 0, // set to 1 always enable tracing
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parameter [12*8-1:0] NAME = "umi") // short label for display (12 chars)
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(// UMI bus tap
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input valid,
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input ready,
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input [CW-1:0] cmd,
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input [AW-1:0] dstaddr,
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input [AW-1:0] srcaddr,
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input [DW-1:0] data,
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// clk, reset only used for simulation display
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input clk,
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input nreset,
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// beat output
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output beat
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);
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//##########################################
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// A transaction has happened
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//##########################################
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`include "umi_messages.vh"
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assign beat = valid & ready;
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//##########################################
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// Simulation only monitoring
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//##########################################
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`ifdef SIMULATION
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// compile time enable of verbose tracing
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`ifdef VERBOSE
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localparam VERBOSE_SWITCH = 1;
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`else
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localparam VERBOSE_SWITCH = 0;
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`endif
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// sane printing
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initial $timeformat(-9, 2, "ns", 0);
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// Pad NAME with leading spaces for aligned display
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reg [12*8-1:0] name_padded;
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integer ni;
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initial begin
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name_padded = " "; // 12 spaces
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for (ni = 0; ni < 12; ni = ni + 1)
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if (NAME[ni*8+:8] != 0)
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name_padded[ni*8+:8] = NAME[ni*8+:8];
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end
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wire [4:0] opcode;
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assign opcode = cmd[4:0];
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// Stall timeout: valid high but ready low for TIMEOUT cycles
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integer stall_count;
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always @(posedge clk or negedge nreset)
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if (!nreset)
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stall_count <= 0;
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else if (valid & ~ready)
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stall_count <= stall_count + 1;
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else
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stall_count <= 0;
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always @(posedge clk) begin
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if (nreset & (stall_count == TIMEOUT)) begin
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$display("%10t %s WARNING: UMI_TIMEOUT: valid=%b ready=%b dst=0x%h src=0x%h cmd=0x%h (%0d cycles) (%m)",
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$realtime, name_padded, valid, ready, dstaddr, srcaddr, cmd, stall_count);
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end
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end
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if (VERBOSE | VERBOSE_SWITCH) begin
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// Transaction display on handshake
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always @(negedge clk) begin
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if (nreset & beat) begin
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case (opcode)
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UMI_REQ_READ: $display("%10t %s UMI_REQ_READ: dst=0x%h src=0x%h data=0x%h (%m)", $realtime, name_padded, dstaddr, srcaddr, data);
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UMI_REQ_WRITE: $display("%10t %s UMI_REQ_WRITE: dst=0x%h src=0x%h data=0x%h (%m)", $realtime, name_padded, dstaddr, srcaddr, data);
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UMI_REQ_POSTED: $display("%10t %s UMI_REQ_POSTED: dst=0x%h src=0x%h data=0x%h (%m)", $realtime, name_padded, dstaddr, srcaddr, data);
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UMI_RESP_READ: $display("%10t %s UMI_RESP_READ: dst=0x%h src=0x%h data=0x%h (%m)", $realtime, name_padded, dstaddr, srcaddr, data);
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UMI_RESP_WRITE: $display("%10t %s UMI_RESP_WRITE: dst=0x%h src=0x%h data=0x%h (%m)", $realtime, name_padded, dstaddr, srcaddr, data);
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UMI_REQ_ATOMIC: $display("%10t %s UMI_REQ_ATOMIC: dst=0x%h src=0x%h data=0x%h (%m)", $realtime, name_padded, dstaddr, srcaddr, data);
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UMI_REQ_RDMA: $display("%10t %s UMI_REQ_RDMA: dst=0x%h src=0x%h data=0x%h (%m)", $realtime, name_padded, dstaddr, srcaddr, data);
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UMI_REQ_USER0: $display("%10t %s UMI_REQ_USER0: dst=0x%h src=0x%h data=0x%h (%m)", $realtime, name_padded, dstaddr, srcaddr, data);
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UMI_REQ_ERROR: $display("%10t %s UMI_REQ_ERROR: dst=0x%h src=0x%h data=0x%h (%m)", $realtime, name_padded, dstaddr, srcaddr, data);
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UMI_REQ_LINK: $display("%10t %s UMI_REQ_LINK: dst=0x%h src=0x%h data=0x%h (%m)", $realtime, name_padded, dstaddr, srcaddr, data);
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default: $display("%10t %s UMI_OPCODE=0x%h: dst=0x%h src=0x%h data=0x%h (%m)", $realtime, name_padded, opcode, dstaddr, srcaddr, data);
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endcase
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end
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end
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end
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`endif
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endmodule

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