Merge pull request #227 from zeroasiccorp/rice/added_la_asynfifo_almost_full_sig

Added almost full sig to la_asyncfifo instances

Author: gadfort

umi/lumi/rtl/lumi_rx.v

@@ -663,6 +663,7 @@ module lumi_rx
                   .PROP("DEFAULT")) // Pass through variable for hard macro
    lnk_fifo_i(// Outputs
               .wr_full          (),
+              .wr_almost_full   (),
               .rd_dout          (lnk_fifo_dout[CW-1:0]),
               .rd_empty         (lnk_fifo_empty),
               // Inputs
@@ -782,6 +783,7 @@ module lumi_rx
                   .PROP("DEFAULT"))       // Pass through variable for hard macro
    req_syncfifo_i(// Outputs
                   .wr_full          (sync_fifo_full[0]),
+                  .wr_almost_full   (),
                   .rd_dout          (sync_fifo_dout[IOW-1:0]),
                   .rd_empty         (sync_fifo_empty[0]),
                   // Inputs
@@ -810,6 +812,7 @@ module lumi_rx
                   .PROP("DEFAULT"))       // Pass through variable for hard macro
    resp_syncfifo_i(// Outputs
                    .wr_full          (sync_fifo_full[1]),
+                   .wr_almost_full   (),
                    .rd_dout          (sync_fifo_dout[2*IOW-1:IOW]),
                    .rd_empty         (sync_fifo_empty[1]),
                    // Inputs

umi/lumi/rtl/lumi_tx.v

@@ -632,6 +632,7 @@ module lumi_tx
                   .PROP("DEFAULT"))  // Pass through variable for hard macro
    phy_fifo_i(// Outputs
               .wr_full          (phy_fifo_full),
+              .wr_almost_full   (),
               .rd_dout          (phy_txdata[IOW-1:0]),
               .rd_empty         (phy_fifo_empty),
               // Inputs

umi/sumi/umi_fifoflex/rtl/umi_fifoflex.v

@@ -579,7 +579,6 @@ module umi_fifoflex
                         .DEPTH(DEPTH))
         fifo  (// Outputs
                .wr_full         (fifo_full_raw),
-               // TODO: Should almost full signal be exposed?
                .wr_almost_full  (),
                .rd_dout         (fifo_dout[ODW+AW+AW+CW-1:0]),
                .rd_empty        (fifo_empty_raw),