Doesn't matter if path is abs or rel

Author: gigeresk

src/synth_fpga.cc

@@ -2386,23 +2386,31 @@ struct SynthFpgaPass : public ScriptPass {
     // Get the parent cad directory path
     std::filesystem::path cad_directory = config_path.parent_path();
 
-    log("Loading cell models from config");
+    log("Loading cell models from config\n");
 
     if(G_config.dff_techmap != "") {
-      if(std::filesystem::path(G_config.dff_techmap).is_absolute()) {
-        log_warning("dff techmap file path '%s' is absolute.\n", G_config.dff_techmap.c_str()); // Path is expected to be relative, in same dir as .*config.json
+      std::filesystem::path dff_techmap_path(G_config.dff_techmap);
+      if(dff_techmap_path.is_absolute()) {
+        dff_techmap_path = cad_directory / dff_techmap_path.relative_path();
+        log_warning("dff techmap file path '%s' is absolute, but treating as relative to config file directory.\n", G_config.dff_techmap.c_str()); // Path is expected to be relative, in same dir as .*config.json
       }
-
-      std::filesystem::path dff_techmap_path = cad_directory / G_config.dff_techmap;
+      else {
+        dff_techmap_path = cad_directory / dff_techmap_path;
+      }
+      log("Reading dff techmap from %s\n", dff_techmap_path.string().c_str());
       run("read_verilog " + dff_techmap_path.string());
     }
 
     if(G_config.dsps_techmap != ""){
-      if(std::filesystem::path(G_config.dsps_techmap).is_absolute()) {
-        log_warning("dff techmap file path '%s' is absolute.\n", G_config.dsps_techmap.c_str()); // Path is expected to be relative, in same dir as .*config.json
+      std::filesystem::path dsp_techmap_path(G_config.dsps_techmap);
+      if(dsp_techmap_path.is_absolute()) {
+        dsp_techmap_path = cad_directory / dsp_techmap_path.relative_path();
+        log_warning("dsp techmap file path '%s' is absolute, but treating as relative to config file directory.\n", G_config.dsps_techmap.c_str()); // Path is expected to be relative, in same dir as .*config.json
       }
-
-      std::filesystem::path dsp_techmap_path = cad_directory / G_config.dsps_techmap;
+      else {
+        dsp_techmap_path = cad_directory / dsp_techmap_path;
+      }
+      log("Reading dsp techmap from %s\n", dsp_techmap_path.string().c_str());
       run("read_verilog " + dsp_techmap_path.string());
     }
   }

tests/unit/data/z1000/z1000.json

@@ -3,8 +3,18 @@
     "partname": "z1000",
     "lut_size": 4,
     "flipflops": {
-        "features": ["async_reset", "async_set", "flop_enable"],
-        "legalize_list": ["$_DFF_PN0_", "$_DFF_P_", "$_DFFE_PP_", "$_DFFE_PN0P_"],
+        "features": [
+            "async_reset",
+            "flop_enable"
+        ],
+        "models": {
+        },
+        "legalize_list": [
+            "$_DFF_PN0_",
+            "$_DFF_P_",
+            "$_DFFE_PP_",
+            "$_DFFE_PN0P_"
+        ],
         "techmap": "tech_flops.v"
     }
 }

tests/unit/data/z1000/z1000_abspath.json

@@ -0,0 +1,20 @@
+{
+    "version": 1,
+    "partname": "z1000",
+    "lut_size": 4,
+    "flipflops": {
+        "features": [
+            "async_reset",
+            "flop_enable"
+        ],
+        "models": {
+        },
+        "legalize_list": [
+            "$_DFF_PN0_",
+            "$_DFF_P_",
+            "$_DFFE_PP_",
+            "$_DFFE_PN0P_"
+        ],
+        "techmap": "/tech_flops.v"
+    }
+}

tests/unit/data/z1010/z1010.json

@@ -4,6 +4,8 @@
     "lut_size": 4,
     "flipflops": {
         "features": ["async_reset", "async_set", "flop_enable"],
+	"models": {
+        },
         "legalize_list": ["$_DFF_PN0_", "$_DFF_P_", "$_DFFE_PP_", "$_DFFE_PN0P_"],
         "techmap": "tech_flops.v"
     },

tests/unit/data/z1010/z1010_abspath.json

@@ -0,0 +1,29 @@
+{
+    "version": 1,
+    "partname": "z1010",
+    "lut_size": 4,
+    "flipflops": {
+        "features": ["async_reset", "async_set", "flop_enable"],
+	"models": {
+        },
+        "legalize_list": ["$_DFF_PN0_", "$_DFF_P_", "$_DFFE_PP_", "$_DFFE_PN0P_"],
+        "techmap": "/tech_flops.v"
+    },
+    "brams": {
+        "memory_libmap": ["/bram_memory_map.txt"],
+        "techmap": ["/tech_bram.v"]
+    },
+    "dsps": {
+        "family": "DSP48",
+        "techmap": "/mult18x18_DSP48.v",
+        "techmap_parameters": {
+            "DSP_A_MAXWIDTH": 18,
+            "DSP_B_MAXWIDTH": 18,
+            "DSP_A_MINWIDTH": 2,
+            "DSP_B_MINWIDTH": 2,
+            "DSP_Y_MINWIDTH": 9,
+            "DSP_SIGNEDONLY": 1,
+            "DSP_NAME": "$__MUL18X18"
+        }
+    }
+}

tests/unit/heartbeat-z1000-config-abspath.ys

@@ -0,0 +1,30 @@
+# yosys -m wildebeest -s heartbeat-z1000-config-abspath.ys
+read_verilog <<EOF
+module heartbeat #(
+    parameter N = 8
+) (
+    //inputs
+    input      clk,     // clock
+    input      nreset,  //async active low reset
+    //outputs
+    output reg out      //heartbeat
+);
+
+    reg [N-1:0] counter_reg;
+
+    always @(posedge clk or negedge nreset) begin
+        if (!nreset) begin
+            counter_reg <= {(N) {1'b0}};
+            out <= 1'b0;
+        end else begin
+            counter_reg <= counter_reg + 1'b1;
+            out <= (counter_reg == {(N) {1'b1}});
+        end
+    end
+
+endmodule
+EOF
+
+synth_fpga -config data/z1000/z1000_abspath.json -show_config
+select -assert-count 9 */t:dffr
+select -assert-count 11 */t:$lut

tests/unit/heartbeat-z1010-config-abspath.ys

@@ -0,0 +1,30 @@
+# yosys -m wildebeest -s heartbeat-z1000-hardcode.ys
+read_verilog <<EOF
+module heartbeat #(
+    parameter N = 8
+) (
+    //inputs
+    input      clk,     // clock
+    input      nreset,  //async active low reset
+    //outputs
+    output reg out      //heartbeat
+);
+
+    reg [N-1:0] counter_reg;
+
+    always @(posedge clk or negedge nreset) begin
+        if (!nreset) begin
+            counter_reg <= {(N) {1'b0}};
+            out <= 1'b0;
+        end else begin
+            counter_reg <= counter_reg + 1'b1;
+            out <= (counter_reg == {(N) {1'b1}});
+        end
+    end
+
+endmodule
+EOF
+
+synth_fpga -config data/z1010/z1010_abspath.json -show_config
+select -assert-count 9 */t:dffr
+select -assert-count 11 */t:$lut