Sdtrig #28

munailwaqar · 2025-04-16T12:55:15Z

No description provided.

github-actions · 2025-04-16T12:56:23Z

core/csr_regfile.sv

+  logic [CVA6Cfg.XLEN-1:0] tselect_q, tselect_d;
+  logic tselect_valid_q, tselect_valid_d;
+  logic [$clog2(N_Triggers)-1:0] tselect_idx_q, tselect_idx_d;
+  logic [CVA6Cfg.XLEN-1:0] triggers_q[N_Triggers-1:0][2:0], triggers_d[N_Triggers-1:0][2:0];   // 2D N trigger array with 3 registers: tdata1, tdata2, tdata3


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [CVA6Cfg.XLEN-1:0] triggers_q[N_Triggers-1:0][2:0], triggers_d[N_Triggers-1:0][2:0]; // 2D N trigger array with 3 registers: tdata1, tdata2, tdata3

logic [CVA6Cfg.XLEN-1:0]

triggers_q[N_Triggers-1:0][2:0],

triggers_d[N_Triggers-1:0][2:0]; // 2D N trigger array with 3 registers: tdata1, tdata2, tdata3

github-actions · 2025-04-16T12:56:23Z

core/csr_regfile.sv

+          if (CVA6Cfg.SDTRIG) begin
+            csr_rdata = tselect_q;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (CVA6Cfg.SDTRIG) begin

csr_rdata = tselect_q;

if (CVA6Cfg.SDTRIG) begin

csr_rdata = tselect_q;

github-actions · 2025-04-16T12:56:23Z

core/csr_regfile.sv

+          if (CVA6Cfg.SDTRIG) begin
+            csr_rdata = triggers_q[tselect_idx_q][0]; // tdata1


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (CVA6Cfg.SDTRIG) begin

csr_rdata = triggers_q[tselect_idx_q][0]; // tdata1

if (CVA6Cfg.SDTRIG) begin

csr_rdata = triggers_q[tselect_idx_q][0]; // tdata1

github-actions · 2025-04-16T12:56:23Z

core/csr_regfile.sv

+          if (CVA6Cfg.SDTRIG) begin
+            csr_rdata = triggers_q[tselect_idx_q][1]; // tdata2


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (CVA6Cfg.SDTRIG) begin

csr_rdata = triggers_q[tselect_idx_q][1]; // tdata2

if (CVA6Cfg.SDTRIG) begin

csr_rdata = triggers_q[tselect_idx_q][1]; // tdata2

github-actions · 2025-04-16T12:56:23Z

core/csr_regfile.sv

+          if (CVA6Cfg.SDTRIG) begin
+            csr_rdata = triggers_q[tselect_idx_q][2]; // tdata3


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (CVA6Cfg.SDTRIG) begin

csr_rdata = triggers_q[tselect_idx_q][2]; // tdata3

if (CVA6Cfg.SDTRIG) begin

csr_rdata = triggers_q[tselect_idx_q][2]; // tdata3

github-actions · 2025-04-16T12:56:24Z

core/csr_regfile.sv

+        if (CVA6Cfg.SDTRIG) begin
+            triggers_d[tselect_idx_d][1] = csr_wdata; // tdata2
+        end else begin
+            update_access_exception = 1'b1;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

update_access_exception = 1'b1;

update_access_exception = 1'b1;

github-actions · 2025-04-16T12:56:24Z

core/csr_regfile.sv

+        end
+        riscv::CSR_TDATA3:
+        if (CVA6Cfg.SDTRIG) begin
+            triggers_d[tselect_idx_d][2] = csr_wdata; // tdata3


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

triggers_d[tselect_idx_d][2] = csr_wdata; // tdata3

triggers_d[tselect_idx_d][2] = csr_wdata; // tdata3

github-actions · 2025-04-16T12:56:25Z

core/csr_regfile.sv

+        if (CVA6Cfg.SDTRIG) begin
+            triggers_d[tselect_idx_d][2] = csr_wdata; // tdata3
+        end else begin
+            update_access_exception = 1'b1;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

update_access_exception = 1'b1;

update_access_exception = 1'b1;

github-actions · 2025-04-16T12:56:25Z

core/csr_regfile.sv

+            update_access_exception = 1'b1;
+        end
+        riscv::CSR_TINFO: begin
+            update_access_exception = 1'b1;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

update_access_exception = 1'b1;

update_access_exception = 1'b1;

github-actions · 2025-04-16T12:56:25Z

core/csr_regfile.sv

@@ -2687,6 +2765,12 @@
        vsatp_q                  <= vsatp_d;
        en_ld_st_g_translation_q <= en_ld_st_g_translation_d;
      end
+      if (CVA6Cfg.SDTRIG) begin
+        tselect_q  <= tselect_d;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

tselect_q <= tselect_d;

tselect_q <= tselect_d;

YazanHussnain-10x · 2025-04-18T10:43:52Z

core/csr_regfile.sv

+            update_access_exception = 1'b1;
+        end
+        riscv::CSR_TINFO: begin
+            update_access_exception = 1'b1;


Write on tinfo should be ignored. Should not generate exception

YazanHussnain-10x · 2025-04-18T10:45:51Z

core/csr_regfile.sv

+  // logic [$clog2(N_Triggers)-1:0] tselect_idx;
+  // logic [CVA6Cfg.XLEN-1:0] triggers[N_Triggers-1:0][2:0];   // 2D N trigger array with 3 registers: tdata1, tdata2, tdata3
+
+  logic [CVA6Cfg.XLEN-1:0] tselect_q, tselect_d;


Should be of size N_TRIGGERS bits

YazanHussnain-10x · 2025-04-18T10:46:22Z

core/csr_regfile.sv

+
+  logic [CVA6Cfg.XLEN-1:0] tselect_q, tselect_d;
+  logic tselect_valid_q, tselect_valid_d;
+  logic [$clog2(N_Triggers)-1:0] tselect_idx_q, tselect_idx_d;


You can use tselect_q.

YazanHussnain-10x · 2025-04-18T10:47:31Z

core/csr_regfile.sv

+  logic [CVA6Cfg.XLEN-1:0] tselect_q, tselect_d;
+  logic tselect_valid_q, tselect_valid_d;
+  logic [$clog2(N_Triggers)-1:0] tselect_idx_q, tselect_idx_d;
+  logic [CVA6Cfg.XLEN-1:0] triggers_q[N_Triggers-1:0][2:0], triggers_d[N_Triggers-1:0][2:0];   // 2D N trigger array with 3 registers: tdata1, tdata2, tdata3


I would recommend you have separate singals for TDATA1, TDATA2, and TDATA3.

YazanHussnain-10x · 2025-04-18T10:48:26Z

core/csr_regfile.sv

+        end
+        riscv::CSR_TDATA1:
+          if (CVA6Cfg.SDTRIG) begin
+            csr_rdata = triggers_q[tselect_idx_q][0]; // tdata1


you can use tselect_q for indexing

YazanHussnain-10x · 2025-04-18T10:54:26Z

core/csr_regfile.sv

+        riscv::CSR_TSELECT:
+        if (CVA6Cfg.SDTRIG) begin
+            tselect_d = csr_wdata;
+            tselect_valid_d = (tselect_idx_q < N_Triggers);


YazanHussnain-10x · 2025-04-18T10:54:47Z

core/csr_regfile.sv

+        if (CVA6Cfg.SDTRIG) begin
+            tselect_d = csr_wdata;
+            tselect_valid_d = (tselect_idx_q < N_Triggers);
+            tselect_idx_d = tselect_q[$clog2(N_Triggers)-1:0];


you can use tselect_q

YazanHussnain-10x · 2025-04-18T10:56:14Z

core/csr_regfile.sv

+        end
+        riscv::CSR_TDATA1:
+        if (CVA6Cfg.SDTRIG) begin
+            triggers_d[tselect_idx_d][0] = csr_wdata;  // tdata1


There are multiple registers on TDATA1 and all have some WARL fields in them. You need to handle them. For example for now, vs and vu should be hardwired to 0. and should be writable.

YazanHussnain-10x · 2025-04-18T10:57:18Z

core/csr_regfile.sv

+            update_access_exception = 1'b1;
+        end
+        riscv::CSR_TDATA2:
+        if (CVA6Cfg.SDTRIG) begin


Check for WARL here also if any. Check spec for that.

YazanHussnain-10x · 2025-04-18T10:57:26Z

core/csr_regfile.sv

+            update_access_exception = 1'b1;
+        end
+        riscv::CSR_TDATA3:
+        if (CVA6Cfg.SDTRIG) begin


Check for WARL here also if any. Check spec for that.

github-actions · 2025-05-07T10:16:24Z

core/csr_regfile.sv

+  //    if (CVA6Cfg.SDTRIG) begin
+  //      if (trigger_type_d[tselect_q] == 4'd3) begin
+  //        //   case(priv_lvl_o) // trigger will only fire if current priv lvl is same as the trigger wants to fire in
+  //         //    riscv::PRIV_LVL_M : if (icount32_tdata1_d[tselect_q].m) priv_match = 1'b1;
+  //         //    riscv::PRIV_LVL_S : if (icount32_tdata1_d[tselect_q].s) priv_match = 1'b1;
+  //         //    riscv::PRIV_LVL_U : if (icount32_tdata1_d[tselect_q].u) priv_match = 1'b1;
+  //         //  endcase
+  //         //  if (commit_ack_i) begin
+  //         //      icount_d--;
+  //          //   end
+  //          // if ((icache_d == 0) && priv_match) begin
+  //             //icount32_tdata1_q[tselect_q].pending = 1'b1;
+  //             //icount32_tdata1_q[tselect_q].hit = 1'b1;
+  //         //   case (icount32_tdata1_d[tselect_q].action) 
+  //         //breakpoint_from_tigger_module_o = 1'b1;
+  //               //6'd1 : debug_from_trigger_module = 1'b1 //into debug mode;
+  // //              default: ;
+  //   //         endcase
+  //    // end
+  //     end
+  //     end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// if (CVA6Cfg.SDTRIG) begin

// if (trigger_type_d[tselect_q] == 4'd3) begin

// // case(priv_lvl_o) // trigger will only fire if current priv lvl is same as the trigger wants to fire in

// // riscv::PRIV_LVL_M : if (icount32_tdata1_d[tselect_q].m) priv_match = 1'b1;

// // riscv::PRIV_LVL_S : if (icount32_tdata1_d[tselect_q].s) priv_match = 1'b1;

// // riscv::PRIV_LVL_U : if (icount32_tdata1_d[tselect_q].u) priv_match = 1'b1;

// // endcase

// // if (commit_ack_i) begin

// // icount_d--;

// // end

// // if ((icache_d == 0) && priv_match) begin

// //icount32_tdata1_q[tselect_q].pending = 1'b1;

// //icount32_tdata1_q[tselect_q].hit = 1'b1;

// // case (icount32_tdata1_d[tselect_q].action)

// //breakpoint_from_tigger_module_o = 1'b1;

// //6'd1 : debug_from_trigger_module = 1'b1 //into debug mode;

// // default: ;

// // endcase

// // end

// end

// end

// if (CVA6Cfg.SDTRIG) begin

// if (trigger_type_d[tselect_q] == 4'd3) begin

// // case(priv_lvl_o) // trigger will only fire if current priv lvl is same as the trigger wants to fire in

// // riscv::PRIV_LVL_M : if (icount32_tdata1_d[tselect_q].m) priv_match = 1'b1;

// // riscv::PRIV_LVL_S : if (icount32_tdata1_d[tselect_q].s) priv_match = 1'b1;

// // riscv::PRIV_LVL_U : if (icount32_tdata1_d[tselect_q].u) priv_match = 1'b1;

// // endcase

// // if (commit_ack_i) begin

// // icount_d--;

// // end

// // if ((icache_d == 0) && priv_match) begin

// //icount32_tdata1_q[tselect_q].pending = 1'b1;

// //icount32_tdata1_q[tselect_q].hit = 1'b1;

// // case (icount32_tdata1_d[tselect_q].action)

// //breakpoint_from_tigger_module_o = 1'b1;

// //6'd1 : debug_from_trigger_module = 1'b1 //into debug mode;

// // default: ;

// // endcase

// // end

// end

// end

github-actions · 2025-05-07T10:16:25Z

core/csr_regfile.sv

@@ -2604,6 +2737,21 @@ module csr_regfile
        vsatp_q                  <= {CVA6Cfg.XLEN{1'b0}};
        en_ld_st_g_translation_q <= 1'b0;
      end
+      if (CVA6Cfg.SDTRIG) begin
+        scontext_q <= '0;
+        tselect_q <= '0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

tselect_q <= '0;

tselect_q <= '0;

github-actions · 2025-05-21T09:48:32Z

core/csr_regfile.sv

@@ -2174,6 +2284,36 @@ module csr_regfile
        debug_mode_d = 1'b0;
      end
    end
+
+  // Triggers Match Logic


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Triggers Match Logic

// Triggers Match Logic

github-actions · 2025-05-21T09:48:32Z

core/csr_regfile.sv

+        if (trigger_type_d[tselect_q] == 4'd3) begin  // icount match logic
+              case(priv_lvl_o) // trigger will only fire if current priv lvl is same as the trigger wants to fire in
+                riscv::PRIV_LVL_M : if (icount32_tdata1_d[tselect_q].m) priv_match = 1'b1;
+                riscv::PRIV_LVL_S : if (icount32_tdata1_d[tselect_q].s) priv_match = 1'b1;
+                riscv::PRIV_LVL_U : if (icount32_tdata1_d[tselect_q].u) priv_match = 1'b1;
+                default: priv_match = 1'b0;
+              endcase
+              if (ex_i.valid) begin
+                in_trap_handler = 1'b1;
+                icount32_tdata1_d[tselect_q].count = icount32_tdata1_d[tselect_q].count - 1;
+              end
+              if (commit_ack_i && mret) in_trap_handler = 1'b0;
+              if (|commit_ack_i && !in_trap_handler && icount32_tdata1_q[tselect_q].count != 0) begin
+                icount32_tdata1_d[tselect_q].count = icount32_tdata1_d[tselect_q].count - 1;
+              end
+              if ((icount32_tdata1_d[tselect_q].count == 0) && priv_match) begin
+                icount32_tdata1_d[tselect_q].pending = 1'b1;
+                //icount32_tdata1_d[tselect_q].hit = 1'b1;
+                case (icount32_tdata1_d[tselect_q].action) 
+                  6'd0 : breakpoint_from_tigger_module = 1'b1;
+                  6'd1 : breakpoint_from_tigger_module = 1'b1; //into debug mode;
+                  default: ;
+                endcase
+              end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (trigger_type_d[tselect_q] == 4'd3) begin // icount match logic

case(priv_lvl_o) // trigger will only fire if current priv lvl is same as the trigger wants to fire in

riscv::PRIV_LVL_M : if (icount32_tdata1_d[tselect_q].m) priv_match = 1'b1;

riscv::PRIV_LVL_S : if (icount32_tdata1_d[tselect_q].s) priv_match = 1'b1;

riscv::PRIV_LVL_U : if (icount32_tdata1_d[tselect_q].u) priv_match = 1'b1;

default: priv_match = 1'b0;

endcase

if (ex_i.valid) begin

in_trap_handler = 1'b1;

icount32_tdata1_d[tselect_q].count = icount32_tdata1_d[tselect_q].count - 1;

end

if (commit_ack_i && mret) in_trap_handler = 1'b0;

if (|commit_ack_i && !in_trap_handler && icount32_tdata1_q[tselect_q].count != 0) begin

icount32_tdata1_d[tselect_q].count = icount32_tdata1_d[tselect_q].count - 1;

end

if ((icount32_tdata1_d[tselect_q].count == 0) && priv_match) begin

icount32_tdata1_d[tselect_q].pending = 1'b1;

//icount32_tdata1_d[tselect_q].hit = 1'b1;

case (icount32_tdata1_d[tselect_q].action)

6'd0 : breakpoint_from_tigger_module = 1'b1;

6'd1 : breakpoint_from_tigger_module = 1'b1; //into debug mode;

default: ;

endcase

end

if (trigger_type_d[tselect_q] == 4'd3) begin // icount match logic

case(priv_lvl_o) // trigger will only fire if current priv lvl is same as the trigger wants to fire in

riscv::PRIV_LVL_M: if (icount32_tdata1_d[tselect_q].m) priv_match = 1'b1;

riscv::PRIV_LVL_S: if (icount32_tdata1_d[tselect_q].s) priv_match = 1'b1;

riscv::PRIV_LVL_U: if (icount32_tdata1_d[tselect_q].u) priv_match = 1'b1;

default: priv_match = 1'b0;

endcase

if (ex_i.valid) begin

in_trap_handler = 1'b1;

icount32_tdata1_d[tselect_q].count = icount32_tdata1_d[tselect_q].count - 1;

end

if (commit_ack_i && mret) in_trap_handler = 1'b0;

if (|commit_ack_i && !in_trap_handler && icount32_tdata1_q[tselect_q].count != 0) begin

icount32_tdata1_d[tselect_q].count = icount32_tdata1_d[tselect_q].count - 1;

end

if ((icount32_tdata1_d[tselect_q].count == 0) && priv_match) begin

icount32_tdata1_d[tselect_q].pending = 1'b1;

//icount32_tdata1_d[tselect_q].hit = 1'b1;

case (icount32_tdata1_d[tselect_q].action)

6'd0: breakpoint_from_tigger_module = 1'b1;

6'd1: breakpoint_from_tigger_module = 1'b1; //into debug mode;

default: ;

endcase

github-actions · 2025-05-21T09:48:33Z

core/csr_regfile.sv

+                endcase
+              end
+        end
+    end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

end

end

github-actions · 2025-05-21T09:48:33Z

core/csr_regfile.sv

@@ -2604,6 +2744,21 @@ module csr_regfile
        vsatp_q                  <= {CVA6Cfg.XLEN{1'b0}};
        en_ld_st_g_translation_q <= 1'b0;
      end
+      if (CVA6Cfg.SDTRIG) begin
+        scontext_q <= '0;
+        tselect_q  <= '0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

tselect_q <= '0;

tselect_q <= '0;

github-actions · 2025-05-21T09:48:33Z

core/cva6.sv

      .dcache_req_ports_i(dcache_req_ports_cache_id),
      .dcache_req_ports_o(dcache_req_ports_id_cache)


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.dcache_req_ports_i(dcache_req_ports_cache_id),

.dcache_req_ports_o(dcache_req_ports_id_cache)

.dcache_req_ports_i (dcache_req_ports_cache_id),

.dcache_req_ports_o (dcache_req_ports_id_cache)

github-actions · 2025-05-21T09:48:33Z

core/cva6.sv

@@ -1199,6 +1202,7 @@ module cva6
      .pmpaddr_o               (pmpaddr),
      .mcountinhibit_o         (mcountinhibit_csr_perf),
      .jvt_o                   (jvt),
+      .breakpoint_from_tigger_module_o (breakpoint_from_tigger_module),
      //RVFI
      .rvfi_csr_o              (rvfi_csr)


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.rvfi_csr_o (rvfi_csr)

.rvfi_csr_o (rvfi_csr)

github-actions · 2025-05-21T09:48:33Z

core/id_stage.sv

        .instruction_o             (decoded_instruction[i]),
        .orig_instr_o              (orig_instr[i]),
-        .is_control_flow_instr_o   (is_control_flow_instr[i])
+        .is_control_flow_instr_o   (is_control_flow_instr[i]),
+        .breakpoint_from_tigger_module_i (breakpoint_from_tigger_module_i)


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.instruction_o (decoded_instruction[i]),

.orig_instr_o (orig_instr[i]),

.is_control_flow_instr_o (is_control_flow_instr[i])

.is_control_flow_instr_o (is_control_flow_instr[i]),

.breakpoint_from_tigger_module_i (breakpoint_from_tigger_module_i)

.instruction_o (decoded_instruction[i]),

.orig_instr_o (orig_instr[i]),

.is_control_flow_instr_o (is_control_flow_instr[i]),

.breakpoint_from_tigger_module_i(breakpoint_from_tigger_module_i)

github-actions · 2025-05-21T09:48:33Z

core/id_stage.sv

@@ -439,6 +442,10 @@ module id_stage #(
            is_control_flow_instr[0]
        };
      end
+


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

github-actions · 2025-05-28T07:12:05Z

core/csr_regfile.sv

+          default: priv_match = 1'b0;
+        endcase
+        // execute with address
+        if (mcontrol6_32_tdata1_d[tselect_q].execute && tdata2_d[tselect_q] == commit_instr_i.pc && commit_ack_i && !mcontrol6_32_tdata1_d[tselect_q].select) matched = 1'b1;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (mcontrol6_32_tdata1_d[tselect_q].execute && tdata2_d[tselect_q] == commit_instr_i.pc && commit_ack_i && !mcontrol6_32_tdata1_d[tselect_q].select) matched = 1'b1;

if (mcontrol6_32_tdata1_d[tselect_q].execute && tdata2_d[tselect_q] == commit_instr_i.pc && commit_ack_i && !mcontrol6_32_tdata1_d[tselect_q].select)

matched = 1'b1;

github-actions · 2025-05-28T07:12:05Z

core/csr_regfile.sv

+        // execute with address
+        if (mcontrol6_32_tdata1_d[tselect_q].execute && tdata2_d[tselect_q] == commit_instr_i.pc && commit_ack_i && !mcontrol6_32_tdata1_d[tselect_q].select) matched = 1'b1;
+        // execute with instruction
+        if (mcontrol6_32_tdata1_d[tselect_q].execute && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == orig_instr_i)) matched = 1'b1;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (mcontrol6_32_tdata1_d[tselect_q].execute && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == orig_instr_i)) matched = 1'b1;

if (mcontrol6_32_tdata1_d[tselect_q].execute && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == orig_instr_i))

matched = 1'b1;

github-actions · 2025-05-28T07:12:05Z

core/csr_regfile.sv

+        // execute with instruction
+        if (mcontrol6_32_tdata1_d[tselect_q].execute && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == orig_instr_i)) matched = 1'b1;
+        // store with data
+        if (mcontrol6_32_tdata1_d[tselect_q].store && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result)) matched = 1'b1;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (mcontrol6_32_tdata1_d[tselect_q].store && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result)) matched = 1'b1;

if (mcontrol6_32_tdata1_d[tselect_q].store && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result))

matched = 1'b1;

github-actions · 2025-05-28T07:12:05Z

core/csr_regfile.sv

+        // store with data
+        if (mcontrol6_32_tdata1_d[tselect_q].store && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result)) matched = 1'b1;
+        // store with address
+        if (mcontrol6_32_tdata1_d[tselect_q].store && !mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == vaddr_from_lsu_i)) matched = 1'b1;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (mcontrol6_32_tdata1_d[tselect_q].store && !mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == vaddr_from_lsu_i)) matched = 1'b1;

if (mcontrol6_32_tdata1_d[tselect_q].store && !mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == vaddr_from_lsu_i))

matched = 1'b1;

github-actions · 2025-05-28T07:12:06Z

core/csr_regfile.sv

+        // store with address
+        if (mcontrol6_32_tdata1_d[tselect_q].store && !mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == vaddr_from_lsu_i)) matched = 1'b1;
+        // load with data
+        if (mcontrol6_32_tdata1_d[tselect_q].load && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result && commit_instr_i.op == 8'h27)) matched = 1'b1;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (mcontrol6_32_tdata1_d[tselect_q].load && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result && commit_instr_i.op == 8'h27)) matched = 1'b1;

if (mcontrol6_32_tdata1_d[tselect_q].load && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result && commit_instr_i.op == 8'h27))

matched = 1'b1;

github-actions · 2025-05-28T07:12:06Z

core/csr_regfile.sv

+        // load with data
+        if (mcontrol6_32_tdata1_d[tselect_q].load && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result && commit_instr_i.op == 8'h27)) matched = 1'b1;
+        // load with address
+        if (mcontrol6_32_tdata1_d[tselect_q].load && !mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == vaddr_from_lsu_i)) matched = 1'b1;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (mcontrol6_32_tdata1_d[tselect_q].load && !mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == vaddr_from_lsu_i)) matched = 1'b1;

if (mcontrol6_32_tdata1_d[tselect_q].load && !mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == vaddr_from_lsu_i))

matched = 1'b1;

github-actions bot reviewed Apr 16, 2025

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YazanHussnain-10x reviewed Apr 18, 2025

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github-actions bot reviewed May 7, 2025

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github-actions bot reviewed May 21, 2025

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munailwaqar added 6 commits May 28, 2025 12:08

basic trigger CSRs

47d04a3

updated and tested trigger CSRs

7f772ac

only csrs

64b4596

verible format fix

f96ca65

icount with action 1

2d8c62f

mcontrol6 with debug action added

3ab0da7

munailwaqar force-pushed the trig-ext branch from 8ace909 to 3ab0da7 Compare May 28, 2025 07:11

github-actions bot reviewed May 28, 2025

View reviewed changes

adding support for 64bit mcontrol6

59079ae

		if (CVA6Cfg.SDTRIG) begin
		csr_rdata = triggers_q[tselect_idx_q][0]; // tdata1

		if (CVA6Cfg.SDTRIG) begin
		csr_rdata = triggers_q[tselect_idx_q][1]; // tdata2

		if (CVA6Cfg.SDTRIG) begin
		csr_rdata = triggers_q[tselect_idx_q][2]; // tdata3

	update_access_exception = 1'b1;
	update_access_exception = 1'b1;

	triggers_d[tselect_idx_d][2] = csr_wdata; // tdata3
	triggers_d[tselect_idx_d][2] = csr_wdata; // tdata3

		.dcache_req_ports_i(dcache_req_ports_cache_id),
		.dcache_req_ports_o(dcache_req_ports_id_cache)

	if (mcontrol6_32_tdata1_d[tselect_q].execute && tdata2_d[tselect_q] == commit_instr_i.pc && commit_ack_i && !mcontrol6_32_tdata1_d[tselect_q].select) matched = 1'b1;
	if (mcontrol6_32_tdata1_d[tselect_q].execute && tdata2_d[tselect_q] == commit_instr_i.pc && commit_ack_i && !mcontrol6_32_tdata1_d[tselect_q].select)
	matched = 1'b1;

	if (mcontrol6_32_tdata1_d[tselect_q].store && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result)) matched = 1'b1;
	if (mcontrol6_32_tdata1_d[tselect_q].store && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result))
	matched = 1'b1;

	if (mcontrol6_32_tdata1_d[tselect_q].load && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result && commit_instr_i.op == 8'h27)) matched = 1'b1;
	if (mcontrol6_32_tdata1_d[tselect_q].load && mcontrol6_32_tdata1_d[tselect_q].select && (tdata2_d[tselect_q] == commit_instr_i.result && commit_instr_i.op == 8'h27))
	matched = 1'b1;

Sdtrig #28

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Sdtrig #28

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munailwaqar commented Apr 16, 2025

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