M.Tech (VLSI), NIT Delhi |
Research Focus: Full-Custom Analog IC Design & Device-Aware Analysis |
Tools: Cadence Virtuoso & Silvaco TCAD
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National Institute of Technology Delhi
- Delhi
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14:28
(UTC +05:30) - https://orcid.org/0009-0006-5028-3207
- https://www.researchgate.net/profile/Sambhav-Saxena?ev=hdr_xprf
- in/sambhavsaxena1107
Popular repositories Loading
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Half-Adder-Full-Adder-Design-on-Xilinx-Vivado
Half-Adder-Full-Adder-Design-on-Xilinx-Vivado PublicVerilog 1
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