Computer Engineering @ Georgia Tech ('28), strongly interested about computer architecture and RTL design.

I like building processors and figuring out how hardware actually works!

• RTL design and design verification (RISC-V, out-of-order microarchitecture)
• Computer architecture — branch prediction, register renaming, memory ordering
• HIL / bench verification and test automation

• Out-Of-Order-Processor-RISC-V — A from-scratch out-of-order RV32IM core in Chisel, BOOM-style: register renaming, a unified physical register file, reorder buffer, age-matrix issue queue, an LSU with store-to-load forwarding, and gshare + BTB + RAS branch prediction. Sim'd with ChiselSim + ScalaTest, CI runs Verilator. 🚀
• HLSFactory — Helping out on Georgia Tech Sharc Lab's open framework for ML-driven high-level synthesis datasets.