dev(timer): add S_L5TI_01 timer frequency test

SrikarJosyula · chetan-rathore · commit b44c0429ac96 · 2026-05-06T20:29:36.000+05:30
- Add timer test t006 for S_L5TI_01 to verify that the OS-visible generic counter reports a 1GHz frequency through CNTFRQ_EL0
 - Add a platform time API for an independent timer source and use it as a sanity check against CNTPCT_EL0 progression
 - Include the new test into SBSA rule metadata, timer execution, UEFI build files, CMake test lists, and the SBSA checklist
 - Add UEFI ACPI/DT implementations using GetTime and baremetal stubs for RD platforms

Signed-off-by: Srikar Josyula &lt;srikar.josyula@arm.com&gt;
Change-Id: I553fbdde5804312ba556601d4d4dce3421d2068f
diff --git a/apps/uefi/Bsa.inf b/apps/uefi/Bsa.inf
@@ -83,6 +83,7 @@
   ../../test_pool/timer/t003.c
   ../../test_pool/timer/t004.c
   ../../test_pool/timer/t005.c
+  ../../test_pool/timer/t006.c
   ../../test_pool/timer/t008.c
   ../../test_pool/watchdog/w001.c
   ../../test_pool/watchdog/w002.c
diff --git a/apps/uefi/Sbsa.inf b/apps/uefi/Sbsa.inf
@@ -86,6 +86,7 @@
   ../../test_pool/timer/t003.c
   ../../test_pool/timer/t004.c
   ../../test_pool/timer/t005.c
+  ../../test_pool/timer/t006.c
   ../../test_pool/timer/t008.c
   ../../test_pool/watchdog/w001.c
   ../../test_pool/watchdog/w002.c
diff --git a/apps/uefi/SbsaNist.inf b/apps/uefi/SbsaNist.inf
@@ -80,6 +80,7 @@
   ../../test_pool/gic/g014.c
   ../../test_pool/gic/g015.c
   ../../test_pool/gic/g016.c
+  ../../test_pool/timer/t006.c
   ../../test_pool/watchdog/w003.c
   ../../test_pool/smmu/i008.c
   ../../test_pool/smmu/i009.c
diff --git a/apps/uefi/Vbsa.inf b/apps/uefi/Vbsa.inf
@@ -85,6 +85,7 @@
   ../../test_pool/timer/t003.c
   ../../test_pool/timer/t004.c
   ../../test_pool/timer/t005.c
+  ../../test_pool/timer/t006.c
   ../../test_pool/timer/t008.c
   ../../test_pool/watchdog/w001.c
   ../../test_pool/watchdog/w002.c
diff --git a/apps/uefi/pc_bsa.inf b/apps/uefi/pc_bsa.inf
@@ -86,6 +86,7 @@
   ../../test_pool/timer/t003.c
   ../../test_pool/timer/t004.c
   ../../test_pool/timer/t005.c
+  ../../test_pool/timer/t006.c
   ../../test_pool/timer/t008.c
   ../../test_pool/watchdog/w001.c
   ../../test_pool/watchdog/w002.c
diff --git a/apps/uefi/xbsa_acpi.inf b/apps/uefi/xbsa_acpi.inf
@@ -192,6 +192,7 @@
   ../../test_pool/gic/g014.c
   ../../test_pool/gic/g015.c
   ../../test_pool/gic/g016.c
+  ../../test_pool/timer/t006.c
   ../../test_pool/timer/t008.c
   ../../test_pool/watchdog/w003.c
   ../../test_pool/smmu/i008.c
diff --git a/docs/sbsa/arm_sbsa_testcase_checklist.md b/docs/sbsa/arm_sbsa_testcase_checklist.md
@@ -474,11 +474,11 @@ The checklist provides information about:
       <td>L5</td>
       <td>S_L5TI_01</td>
       <td>S_L5TI_01</td>
-      <td>Not Covered</td>
-      <td></td>
-      <td></td>
-      <td></td>
-      <td></td>
+      <td>406</td>
+      <td>Check OS visible counter reports 1GHz</td>
+      <td>Yes</td>
+      <td>Yes</td>
+      <td>No</td>
       <td></td>
     </tr>
     <tr>
diff --git a/pal/baremetal/target/RDN2/src/pal_sbsa.c b/pal/baremetal/target/RDN2/src/pal_sbsa.c
@@ -32,6 +32,19 @@ extern const PLATFORM_OVERRIDE_MEMORY_INFO_TABLE  platform_mem_cfg;
 extern const PCIE_INFO_TABLE                      platform_pcie_cfg;
 extern const WD_INFO_TABLE                        platform_wd_cfg;
 
+/** Timer API **/
+/**
+  @brief  Platform defined method to read time in microseconds from an independent timer source
+
+  @return PAL_STATUS_NOT_IMPLEMENTED - API not implemented, Other values - Success
+**/
+uint64_t
+pal_get_platform_time_us(void)
+{
+  pal_warn_not_implemented(__func__);
+  return PAL_STATUS_NOT_IMPLEMENTED;
+}
+
 /** SMMU API's **/
 /**
   @brief  Platform defined method to check if CATU is behind an ETR device
diff --git a/pal/baremetal/target/RDV3/src/pal_sbsa.c b/pal/baremetal/target/RDV3/src/pal_sbsa.c
@@ -32,6 +32,19 @@ extern const PLATFORM_OVERRIDE_MEMORY_INFO_TABLE  platform_mem_cfg;
 extern const PCIE_INFO_TABLE                      platform_pcie_cfg;
 extern const WD_INFO_TABLE                        platform_wd_cfg;
 
+/** Timer API **/
+/**
+  @brief  Platform defined method to read time in microseconds from an independent timer source
+
+  @return PAL_STATUS_NOT_IMPLEMENTED - API not implemented, Other values - Success
+**/
+uint64_t
+pal_get_platform_time_us(void)
+{
+  pal_warn_not_implemented(__func__);
+  return PAL_STATUS_NOT_IMPLEMENTED;
+}
+
 /** SMMU API's **/
 /**
   @brief  Platform defined method to check if CATU is behind an ETR device
diff --git a/pal/baremetal/target/RDV3CFG1/src/pal_sbsa.c b/pal/baremetal/target/RDV3CFG1/src/pal_sbsa.c
@@ -32,6 +32,19 @@ extern const PLATFORM_OVERRIDE_MEMORY_INFO_TABLE  platform_mem_cfg;
 extern const PCIE_INFO_TABLE                      platform_pcie_cfg;
 extern const WD_INFO_TABLE                        platform_wd_cfg;
 
+/** Timer API **/
+/**
+  @brief  Platform defined method to read time in microseconds from an independent timer source
+
+  @return PAL_STATUS_NOT_IMPLEMENTED - API not implemented, Other values - Success
+**/
+uint64_t
+pal_get_platform_time_us(void)
+{
+  pal_warn_not_implemented(__func__);
+  return PAL_STATUS_NOT_IMPLEMENTED;
+}
+
 /** SMMU API's **/
 /**
   @brief  Platform defined method to check if CATU is behind an ETR device
diff --git a/pal/uefi_acpi/src/pal_timer_wd.c b/pal/uefi_acpi/src/pal_timer_wd.c
@@ -17,6 +17,7 @@
 
 #include <Library/UefiLib.h>
 #include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
 #include <Library/BaseLib.h>
 #include <Library/BaseMemoryLib.h>
 
@@ -31,6 +32,27 @@ static EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE *gGtdtHdr;
 UINT64
 pal_get_gtdt_ptr();
 
+UINT64
+pal_get_platform_time_us (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  EFI_TIME Time;
+  UINT64 TimeUs;
+
+  Status = gRT->GetTime(&Time, NULL);
+  if (EFI_ERROR(Status)) {
+    pal_print_msg(ACS_PRINT_WARN, " GetTime failed: %x\n", Status);
+    return ~0ULL;
+  }
+
+  TimeUs = (((UINT64)Time.Hour * 60 + Time.Minute) * 60 + Time.Second) * 1000000ULL;
+  TimeUs += (UINT64)Time.Nanosecond / 1000ULL;
+
+  return TimeUs;
+}
+
 /**
   @brief This API overrides the timer specified by TimerTable
          Note: Information about only one timer can be mentioned as an Override
diff --git a/pal/uefi_dt/src/pal_timer_wd.c b/pal/uefi_dt/src/pal_timer_wd.c
@@ -17,6 +17,7 @@
 
 #include <Library/UefiLib.h>
 #include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
 #include <Library/BaseLib.h>
 #include <Library/BaseMemoryLib.h>
 
@@ -48,6 +49,27 @@ static char wd_dt_arr[][WD_COMPATIBLE_STR_LEN] = {
 UINT64
 pal_get_gtdt_ptr();
 
+UINT64
+pal_get_platform_time_us (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  EFI_TIME Time;
+  UINT64 TimeUs;
+
+  Status = gRT->GetTime(&Time, NULL);
+  if (EFI_ERROR(Status)) {
+    pal_print_msg(ACS_PRINT_WARN, " GetTime failed: %x\n", Status);
+    return ~0ULL;
+  }
+
+  TimeUs = (((UINT64)Time.Hour * 60 + Time.Minute) * 60 + Time.Second) * 1000000ULL;
+  TimeUs += (UINT64)Time.Nanosecond / 1000ULL;
+
+  return TimeUs;
+}
+
 /**
   @brief This API overrides the timer specified by TimerTable
          Note: Information about only one timer can be mentioned as an Override
diff --git a/test_pool/timer/t006.c b/test_pool/timer/t006.c
@@ -0,0 +1,145 @@
+/** @file
+ * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved.
+ * SPDX-License-Identifier : Apache-2.0
+
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **/
+
+#include "acs_val.h"
+#include "acs_timer.h"
+#include "acs_timer_support.h"
+
+#define TEST_NUM   (ACS_TIMER_TEST_NUM_BASE + 6)
+#define TEST_RULE  "S_L5TI_01"
+#define TEST_DESC  "Check OS visible counter reports 1GHz "
+
+#define MICROSECONDS_PER_SECOND  1000000ULL
+#define MAX_DELTA_PERCENT        1ULL
+
+static
+void
+payload()
+{
+  uint64_t counter_freq, print_freq = 0;
+  uint64_t counter_start_value, counter_end_value;
+  uint64_t time_start_us, time_end_us;
+  uint64_t counter_delta, elapsed_time_us;
+  uint64_t est_freq_hz, freq_delta_hz;
+  uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
+  uint32_t print_mhz = 0;
+  uint32_t iter;
+
+  counter_freq = val_timer_get_info(TIMER_INFO_CNTFREQ, 0);
+
+  if (counter_freq != 0) {
+    print_freq = counter_freq/1000;
+    if (print_freq > 1000) {
+      print_freq = print_freq/1000;
+      print_mhz = 1;
+    }
+  }
+
+  if (print_mhz)
+    val_print(INFO, "\n       Counter frequency is %ld MHz", print_freq);
+  else
+    val_print(INFO, "\n       Counter frequency is %ld KHz", print_freq);
+
+  /* Acc to S_L5TI_01, the OS visible counter should be able to count in nanosecond units.
+     That means the reported effective freq by CNTFRQ_EL0 should be exactly 1GHz,
+     consistent with post Armv8.6 systems that mandate a fixed 1GHz counter freq */
+  if (counter_freq == (1000 * 1000 * 1000))
+      val_set_status(index, RESULT_PASS);
+  else
+      val_set_status(index, RESULT_FAIL(1));
+
+  /* The test below is only a sanity check. It will not measure the compliance of the system against
+     S_L5TI_01.
+
+     Sanity Check: CNTFRQ_EL0 is programmed by the firmware and software relies on it to derive the
+     timer resolution. CNTPCT_EL0 is a hardware managed physical counter which progresses at the
+     rate mentioned by CNTFID and if scaling is implemented the counter increments based on the
+     scale value mentioned in CNTSCR.ScaleVal.
+
+     The purpose of this check is to verify that the observed progression of CNTPCT_EL0 is
+     consistent with the frequency reported to software through CNTFRQ_EL0.
+  */
+
+  /* Algorithm: Sample CNTPCT_EL0 at two points separated by 1000 ms while tracking the same
+                interval with an independent timer source.  Use the elapsed counter delta
+                and the independent time delta to estimate the effective frequency of CNTPCT_EL0.
+  */
+
+  for (iter = 0; iter < 5; iter++) {
+      isb();
+      counter_start_value = read_cntpct_el0();
+      time_start_us = val_get_platform_time_us();
+      if ((time_start_us == PAL_TIME_US_INVALID) ||
+          (time_start_us == ACS_STATUS_PAL_NOT_IMPLEMENTED)) {
+          val_print(DEBUG, "\n       Platform time source unavailable; skipping sanity check");
+          return;
+      }
+
+      val_time_delay_ms(1000 * ONE_MILLISECOND);
+
+      isb();
+      counter_end_value = read_cntpct_el0();
+      time_end_us = val_get_platform_time_us();
+      if (time_end_us == PAL_TIME_US_INVALID) {
+          val_print(DEBUG, "\n       Platform time source unavailable; skipping sanity check");
+          return;
+      }
+
+      counter_delta   = counter_end_value - counter_start_value;
+      elapsed_time_us = time_end_us - time_start_us;
+
+      if (elapsed_time_us == 0) {
+          val_print(DEBUG, "\n       Platform time delta is zero; skipping sanity check");
+          return;
+      }
+
+      est_freq_hz = (counter_delta * MICROSECONDS_PER_SECOND) / elapsed_time_us;
+      val_print(DEBUG, "\n       Estimated CNTPCT_EL0 frequency is %ld Hz", est_freq_hz);
+
+      if (est_freq_hz >= counter_freq)
+        freq_delta_hz = est_freq_hz - counter_freq;
+      else
+        freq_delta_hz = counter_freq - est_freq_hz;
+
+      if (((freq_delta_hz * 100ULL) / counter_freq) > MAX_DELTA_PERCENT)
+          val_print(WARN, "\n       Sanity check: CNTPCT_EL0 progression is not consistent with"
+                        " CNTFRQ_EL0");
+      else
+          val_print(DEBUG, "\n       Sanity check: CNTPCT_EL0 progression is consistent with"
+                        " CNTFRQ_EL0");
+  }
+}
+
+uint32_t
+t006_entry(uint32_t num_pe)
+{
+
+  uint32_t status = ACS_STATUS_FAIL;
+
+  num_pe = 1;  //This Timer test is run on single processor
+
+  val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__);
+  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
+  if (status != ACS_STATUS_SKIP)
+      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
+
+  /* get the result from all PE and check for failure */
+  status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);
+
+  val_report_status(0, ACS_END(TEST_NUM), TEST_RULE);
+  return status;
+}
diff --git a/tools/cmake/infra/sbsa_test.txt b/tools/cmake/infra/sbsa_test.txt
@@ -41,6 +41,7 @@ g013.c
 g014.c
 g015.c
 g016.c
+t006.c
 w003.c
 i008.c
 i009.c
diff --git a/val/include/acs_timer.h b/val/include/acs_timer.h
@@ -47,5 +47,6 @@ uint32_t t002_entry(uint32_t num_pe);
 uint32_t t003_entry(uint32_t num_pe);
 uint32_t t004_entry(uint32_t num_pe);
 uint32_t t005_entry(uint32_t num_pe);
+uint32_t t006_entry(uint32_t num_pe);
 uint32_t t008_entry(uint32_t num_pe);
 #endif // __ACS_TIMER_H__
diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h
@@ -126,6 +126,7 @@
 /* The following are common across all platform unless guarded explicitly */
 
 #define ONE_MILLISECOND 1000
+#define PAL_TIME_US_INVALID (~0ULL)
 
 #define PCIE_SUCCESS            0x00000000  /* Operation completed successfully */
 #define PCIE_NO_MAPPING         0x10000001  /* A mapping to a Function does not exist */
@@ -805,6 +806,7 @@ void    *pal_mem_virt_to_phys(void *va);
 void    *pal_mem_phys_to_virt(uint64_t pa);
 
 uint64_t pal_time_delay_ms(uint64_t time_ms);
+uint64_t pal_get_platform_time_us(void);
 void     pal_mem_allocate_shared(uint32_t num_pe, uint32_t sizeofentry);
 void     pal_mem_free_shared(void);
 uint64_t pal_mem_get_shared_addr(void);
diff --git a/val/include/rule_based_execution_enum.h b/val/include/rule_based_execution_enum.h
@@ -763,6 +763,7 @@ typedef enum {
     T003_ENTRY,
     T004_ENTRY,
     T005_ENTRY,
+    T006_ENTRY,
     T008_ENTRY,
     W001_ENTRY,
     W002_ENTRY,
diff --git a/val/include/val_interface.h b/val/include/val_interface.h
@@ -111,6 +111,7 @@ void val_print_acs_test_status_summary(void);
 
 uint32_t execute_tests(void);
 uint64_t val_time_delay_ms(uint64_t time_ms);
+uint64_t val_get_platform_time_us(void);
 
 /* VAL PE APIs */
 typedef enum {
diff --git a/val/src/acs_test_infra.c b/val/src/acs_test_infra.c
diff --git a/val/src/rule_metadata.c b/val/src/rule_metadata.c
diff --git a/val/src/sbsa_execute_test.c b/val/src/sbsa_execute_test.c
