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Removal of offsets #2

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1 change: 1 addition & 0 deletions pal/uefi_dt/UnifiedPalLib.inf
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Expand Up @@ -48,6 +48,7 @@
ShellPkg/ShellPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
StdLib/StdLib.dec

[LibraryClasses]
IoLib
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2 changes: 1 addition & 1 deletion test_pool/gic/g009.c
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Expand Up @@ -22,7 +22,7 @@
#include "val/include/acs_gic_support.h"
#include "val/include/val_interface.h"

#define TEST_NUM (ACS_GIC_HYP_TEST_NUM_BASE + 9)
#define TEST_NUM (ACS_GIC_TEST_NUM_BASE + 9)
#define TEST_RULE "B_PPI_00"
#define TEST_DESC "Check NS EL2-Virt timer PPI Assignment"

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2 changes: 1 addition & 1 deletion test_pool/gic/g010.c
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Expand Up @@ -22,7 +22,7 @@
#include "val/include/acs_gic.h"
#include "val/include/acs_gic_support.h"

#define TEST_NUM (ACS_GIC_HYP_TEST_NUM_BASE + 10)
#define TEST_NUM (ACS_GIC_TEST_NUM_BASE + 10)
#define TEST_RULE "B_PPI_00"
#define TEST_DESC "Check NS EL2-Phy timer PPI Assignment "

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2 changes: 1 addition & 1 deletion test_pool/gic/g011.c
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Expand Up @@ -22,7 +22,7 @@
#include "val/include/acs_gic.h"
#include "val/include/acs_gic_support.h"

#define TEST_NUM (ACS_GIC_HYP_TEST_NUM_BASE + 11)
#define TEST_NUM (ACS_GIC_TEST_NUM_BASE + 11)
#define TEST_RULE "B_PPI_00"
#define TEST_DESC "Check GIC Maintenance PPI Assignment "

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2 changes: 1 addition & 1 deletion test_pool/pcie/p101.c
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Expand Up @@ -19,7 +19,7 @@
#include "val/include/acs_pcie.h"
#include "val/include/acs_memory.h"

#define TEST_NUM (ACS_PCIE_TEST_NUM_BASE + 61)
#define TEST_NUM (ACS_PCIE_TEST_NUM_BASE + 94)
#define TEST_RULE "PCI_MM_01, PCI_MM_02, PCI_MM_03"
#define TEST_DESC "PCIe Unaligned access "

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2 changes: 1 addition & 1 deletion test_pool/pcie/p102.c
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Expand Up @@ -21,7 +21,7 @@
#include "val/include/acs_pcie.h"
#include "val/include/val_interface.h"

#define TEST_NUM (ACS_PCIE_TEST_NUM_BASE + 62)
#define TEST_NUM (ACS_PCIE_TEST_NUM_BASE + 95)
#define TEST_RULE "PCI_MM_05, PCI_MM_06, PCI_MM_07"
#define TEST_DESC "No extra address translation "

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2 changes: 1 addition & 1 deletion test_pool/pcie/p103.c
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Expand Up @@ -18,7 +18,7 @@
#include "val/include/acs_memory.h"
#include "val/include/acs_pcie.h"

#define TEST_NUM (ACS_PCIE_TEST_NUM_BASE + 63)
#define TEST_NUM (ACS_PCIE_TEST_NUM_BASE + 96)
#define TEST_RULE "PCI_LI_02"
#define TEST_DESC "PCI legacy intr SPI ID unique "

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2 changes: 1 addition & 1 deletion test_pool/pcie/p104.c
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Expand Up @@ -18,7 +18,7 @@
#include "val/include/acs_pcie.h"
#include "val/include/acs_memory.h"

#define TEST_NUM (ACS_PCIE_TEST_NUM_BASE + 64)
#define TEST_NUM (ACS_PCIE_TEST_NUM_BASE + 97)
#define TEST_RULE "PCI_MSI_2"
#define TEST_DESC "Check MSI(X) vectors uniqueness "

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2 changes: 1 addition & 1 deletion test_pool/pe/pe017.c
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Expand Up @@ -18,7 +18,7 @@
#include "val/include/acs_val.h"
#include "val/include/acs_pe.h"

#define TEST_NUM (ACS_PE_HYP_TEST_NUM_BASE + 17)
#define TEST_NUM (ACS_PE_TEST_NUM_BASE + 17)
#define TEST_RULE "B_PE_18"
#define TEST_DESC "Check EL2 implementation "

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2 changes: 1 addition & 1 deletion test_pool/pe/pe018.c
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Expand Up @@ -18,7 +18,7 @@
#include "val/include/acs_val.h"
#include "val/include/acs_pe.h"

#define TEST_NUM (ACS_PE_HYP_TEST_NUM_BASE + 18)
#define TEST_NUM (ACS_PE_TEST_NUM_BASE + 18)
#define TEST_RULE "B_PE_19"
#define TEST_DESC "Check Stage 2 4KB Granule Support "

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2 changes: 1 addition & 1 deletion test_pool/pe/pe019.c
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Expand Up @@ -18,7 +18,7 @@
#include "val/include/acs_val.h"
#include "val/include/acs_pe.h"

#define TEST_NUM (ACS_PE_HYP_TEST_NUM_BASE + 19)
#define TEST_NUM (ACS_PE_TEST_NUM_BASE + 19)
#define TEST_RULE "B_PE_20"
#define TEST_DESC "Check Stage2 and Stage1 Granule match "

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2 changes: 1 addition & 1 deletion test_pool/pe/pe020.c
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Expand Up @@ -18,7 +18,7 @@
#include "val/include/acs_val.h"
#include "val/include/acs_pe.h"

#define TEST_NUM (ACS_PE_HYP_TEST_NUM_BASE + 20)
#define TEST_NUM (ACS_PE_TEST_NUM_BASE + 20)
#define TEST_RULE "B_PE_21"
#define TEST_DESC "Check for PMU counters "

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2 changes: 1 addition & 1 deletion test_pool/pe/pe021.c
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Expand Up @@ -18,7 +18,7 @@
#include "val/include/acs_val.h"
#include "val/include/acs_pe.h"

#define TEST_NUM (ACS_PE_HYP_TEST_NUM_BASE + 21)
#define TEST_NUM (ACS_PE_TEST_NUM_BASE + 21)
#define TEST_RULE "B_PE_22"
#define TEST_DESC "Check VMID breakpoint number "

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2 changes: 1 addition & 1 deletion test_pool/pe/pe022.c
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Expand Up @@ -18,7 +18,7 @@
#include "val/include/acs_val.h"
#include "val/include/acs_pe.h"

#define TEST_NUM (ACS_PE_PS_TEST_NUM_BASE + 22)
#define TEST_NUM (ACS_PE_TEST_NUM_BASE + 22)
#define TEST_RULE "B_PE_23, B_PE_24"
#define TEST_DESC "Check EL3 implementation "

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2 changes: 1 addition & 1 deletion test_pool/smmu/i005.c
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Expand Up @@ -20,7 +20,7 @@
#include "val/include/acs_smmu.h"
#include "val/include/acs_pcie.h"

#define TEST_NUM (ACS_SMMU_HYP_TEST_NUM_BASE + 5)
#define TEST_NUM (ACS_SMMU_TEST_NUM_BASE + 5)
#define TEST_RULE "B_SMMU_16, B_SMMU_17, B_SMMU_18"
#define TEST_DESC "Check SMMU S-EL2 & stage2 support "

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2 changes: 1 addition & 1 deletion test_pool/smmu/i006.c
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Expand Up @@ -18,7 +18,7 @@
#include "val/include/acs_val.h"
#include "val/include/acs_iovirt.h"

#define TEST_NUM (ACS_SMMU_HYP_TEST_NUM_BASE + 6)
#define TEST_NUM (ACS_SMMU_TEST_NUM_BASE + 6)
#define TEST_RULE "B_SMMU_19"
#define TEST_DESC "SMMUv2 unique intr per ctxt bank "

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2 changes: 1 addition & 1 deletion test_pool/smmu/i007.c
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Expand Up @@ -19,7 +19,7 @@
#include "val/include/acs_smmu.h"
#include "val/include/acs_pcie.h"

#define TEST_NUM (ACS_SMMU_HYP_TEST_NUM_BASE + 7)
#define TEST_NUM (ACS_SMMU_TEST_NUM_BASE + 7)
#define TEST_RULE "B_SMMU_21, SMMU_01"
#define TEST_DESC "SMMUv3 Integration compliance "

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6 changes: 1 addition & 5 deletions val/include/acs_common.h
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Expand Up @@ -27,15 +27,11 @@
#define G_SW_PS 2

#define ACS_PE_TEST_NUM_BASE 0
#define ACS_PE_HYP_TEST_NUM_BASE (ACS_PE_TEST_NUM_BASE + 50)
#define ACS_PE_PS_TEST_NUM_BASE (ACS_PE_HYP_TEST_NUM_BASE + 25)
#define ACS_MEMORY_MAP_TEST_NUM_BASE 100
#define ACS_GIC_TEST_NUM_BASE 200
#define ACS_GIC_HYP_TEST_NUM_BASE (ACS_GIC_TEST_NUM_BASE + 25)
#define ACS_GIC_V2M_TEST_NUM_BASE (ACS_GIC_HYP_TEST_NUM_BASE + 25)
#define ACS_GIC_V2M_TEST_NUM_BASE (ACS_GIC_TEST_NUM_BASE + 25)
#define ACS_GIC_ITS_TEST_NUM_BASE (ACS_GIC_V2M_TEST_NUM_BASE + 25)
#define ACS_SMMU_TEST_NUM_BASE 300
#define ACS_SMMU_HYP_TEST_NUM_BASE (ACS_SMMU_TEST_NUM_BASE + 50)
#define ACS_TIMER_TEST_NUM_BASE 400
#define ACS_WAKEUP_TEST_NUM_BASE 500
#define ACS_PER_TEST_NUM_BASE 600
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2 changes: 1 addition & 1 deletion val/src/acs_pcie.c
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Expand Up @@ -1382,7 +1382,7 @@ val_pcie_register_bitfields_check(uint64_t *bf_info_table, uint32_t num_bitfield
{

uint32_t bdf;
uint32_t dp_type;
uint32_t dp_type = 0;
uint32_t tbl_index;
uint32_t num_fails;
uint32_t num_pass;
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