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VeriMap is a design kit for converting single-rail RTL netlists into a dual-rail circuits resistant to DPA attacks

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ARandomOWL/verimap

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VeriMap is a design kit for converting single-rail RTL netlists into a dual-rail circuits resistant to DPA attacks

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  • C 77.2%
  • C++ 11.8%
  • Yacc 6.7%
  • Lex 3.3%
  • Makefile 1.0%